Commit 835c065f authored by Gilles Chanteperdrix's avatar Gilles Chanteperdrix Committed by Philippe Gerum

gpio: omap: ipipe: enable interrupt pipelining

Fix up the omap GPIO driver in order to channel interrupts through the
interrupt pipeline.
parent 420b167b
......@@ -26,6 +26,7 @@
#include <linux/of_device.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>
#include <linux/ipipe.h>
#include <linux/platform_data/gpio-omap.h>
#define OFF_MODE 1
......@@ -58,7 +59,11 @@ struct gpio_bank {
u32 saved_datain;
u32 level_mask;
u32 toggle_mask;
#ifdef CONFIG_IPIPE
ipipe_spinlock_t lock;
#else
raw_spinlock_t lock;
#endif
raw_spinlock_t wa_lock;
struct gpio_chip chip;
struct clk *dbck;
......@@ -728,20 +733,17 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
* line's interrupt handler has been run, we may miss some nested
* interrupts.
*/
static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
static void __omap_gpio_irq_handler(struct gpio_bank *bank)
{
void __iomem *isr_reg = NULL;
u32 enabled, isr, level_mask;
unsigned int bit;
struct gpio_bank *bank = gpiobank;
unsigned long wa_lock_flags;
unsigned long lock_flags;
isr_reg = bank->base + bank->regs->irqstatus;
if (WARN_ON(!isr_reg))
goto exit;
pm_runtime_get_sync(bank->chip.parent);
return;
while (1) {
raw_spin_lock_irqsave(&bank->lock, lock_flags);
......@@ -784,18 +786,38 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
ipipe_handle_demuxed_irq(irq_find_mapping(bank->chip.irq.domain,
bit));
raw_spin_unlock_irqrestore(&bank->wa_lock,
wa_lock_flags);
}
}
exit:
}
#ifdef CONFIG_IPIPE
static void omap_gpio_irq_handler(struct irq_desc *d)
{
struct gpio_bank *bank = irq_desc_get_handler_data(d);
__omap_gpio_irq_handler(bank);
}
#else
static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
{
struct gpio_bank *bank = gpiobank;
pm_runtime_get_sync(bank->chip.parent);
__omap_gpio_irq_handler(bank);
pm_runtime_put(bank->chip.parent);
return IRQ_HANDLED;
}
#endif
static unsigned int omap_gpio_irq_startup(struct irq_data *d)
{
struct gpio_bank *bank = omap_irq_data_get_bank(d);
......@@ -877,6 +899,19 @@ static void omap_gpio_mask_irq(struct irq_data *d)
raw_spin_unlock_irqrestore(&bank->lock, flags);
}
static void omap_gpio_mask_ack_irq(struct irq_data *d)
{
struct gpio_bank *bank = omap_irq_data_get_bank(d);
unsigned offset = d->hwirq;
unsigned long flags;
raw_spin_lock_irqsave(&bank->lock, flags);
omap_set_gpio_irqenable(bank, offset, 0);
omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
omap_clear_gpio_irqstatus(bank, offset);
raw_spin_unlock_irqrestore(&bank->lock, flags);
}
static void omap_gpio_unmask_irq(struct irq_data *d)
{
struct gpio_bank *bank = omap_irq_data_get_bank(d);
......@@ -1206,11 +1241,16 @@ static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
return ret;
}
#ifdef CONFIG_IPIPE
irq_set_chained_handler_and_data(bank->irq,
omap_gpio_irq_handler, bank);
#else
ret = devm_request_irq(bank->chip.parent, bank->irq,
omap_gpio_irq_handler,
0, dev_name(bank->chip.parent), bank);
if (ret)
gpiochip_remove(&bank->chip);
#endif
if (!bank->is_mpuio)
gpio += bank->width;
......@@ -1249,13 +1289,14 @@ static int omap_gpio_probe(struct platform_device *pdev)
irqc->irq_shutdown = omap_gpio_irq_shutdown,
irqc->irq_ack = omap_gpio_ack_irq,
irqc->irq_mask = omap_gpio_mask_irq,
irqc->irq_mask_ack = omap_gpio_mask_ack_irq,
irqc->irq_unmask = omap_gpio_unmask_irq,
irqc->irq_set_type = omap_gpio_irq_type,
irqc->irq_set_wake = omap_gpio_wake_enable,
irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
irqc->name = dev_name(&pdev->dev);
irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
irqc->flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_PIPELINE_SAFE;
bank->irq = platform_get_irq(pdev, 0);
if (bank->irq <= 0) {
......
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