...
 
Commits (336)
......@@ -33,8 +33,8 @@ config ARM
select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
select HAVE_ARCH_TRACEHOOK
select HAVE_BPF_JIT
select HAVE_CONTEXT_TRACKING if !IPIPE
select HAVE_CC_STACKPROTECTOR
select HAVE_CONTEXT_TRACKING
select HAVE_C_RECORDMCOUNT
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_API_DEBUG
......@@ -67,6 +67,7 @@ config ARM
select HAVE_SYSCALL_TRACEPOINTS
select HAVE_UID16
select HAVE_VIRT_CPU_ACCOUNTING_GEN
select IPIPE_WANT_PTE_PINNING if IPIPE && !(CPU_V6K || CPU_V7)
select IRQ_FORCED_THREADING
select MODULES_USE_ELF_REL
select NO_BOOTMEM
......@@ -85,6 +86,11 @@ config ARM
Europe. There is an ARM Linux project with a web page at
<http://www.arm.linux.org.uk/>.
if IPIPE
config IPIPE_WANT_ACTIVE_MM
def_bool y
endif
config ARM_HAS_SG_CHAIN
select ARCH_HAS_SG_CHAIN
bool
......@@ -377,6 +383,7 @@ config ARCH_AT91
select NEED_MACH_IO_H if PCCARD
select PINCTRL
select PINCTRL_AT91 if USE_OF
select ATMEL_TCLIB if IPIPE
help
This enables support for systems based on Atmel
AT91RM9200 and AT91SAM9* processors.
......@@ -515,6 +522,7 @@ config ARCH_IXP4XX
select CLKSRC_MMIO
select CPU_XSCALE
select DMABOUNCE if PCI
select IPIPE_ARM_KUSER_TSC if IPIPE
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_PCI
select NEED_MACH_IO_H
......@@ -710,6 +718,7 @@ config ARCH_SA1100
config ARCH_S3C24XX
bool "Samsung S3C24XX SoCs"
select IPIPE_ARM_KUSER_TSC if IPIPE
select ARCH_REQUIRE_GPIOLIB
select ATAGS
select CLKDEV_LOOKUP
......@@ -1005,6 +1014,14 @@ config ARM_TIMER_SP804
select CLKSRC_MMIO
select CLKSRC_OF if OF
if IPIPE
config IPIPE_ARM_KUSER_TSC
bool
select GENERIC_TIME_VSYSCALL
select IPIPE_HAVE_HOSTRT if IPIPE
default y if ARCH_AT91 || ARM_TIMER_SP804 || ARCH_MXC || ARCH_OMAP || PLAT_PXA || PLAT_S3C24XX || ARCH_SA1100
endif
source "arch/arm/firmware/Kconfig"
source arch/arm/mm/Kconfig
......@@ -1515,6 +1532,8 @@ config ARCH_NR_GPIO
If unsure, leave the default value.
source kernel/ipipe/Kconfig
source kernel/Kconfig.preempt
config HZ_FIXED
......
#define _LINUX_STRING_H_
#include <linux/compiler.h> /* for inline */
#include <linux/types.h> /* for size_t */
#include <linux/stddef.h> /* for NULL */
#include <linux/linkage.h>
#include <asm/string.h>
#include <linux/string.h>
extern unsigned long free_mem_ptr;
extern unsigned long free_mem_end_ptr;
......
......@@ -1272,6 +1272,15 @@ memdump: mov r12, r0
mov pc, r10
#endif
#ifdef CONFIG_IPIPE_TRACE_MCOUNT
.text
.align 0
.type mcount %function
.global mcount
mcount:
mov pc, lr @ just return
#endif
.ltorg
#ifdef CONFIG_ARM_VIRT_EXT
......
......@@ -93,6 +93,23 @@ int strcmp(const char *cs, const char *ct)
return res;
}
char *strstr(const char *s1, const char *s2)
{
size_t l1, l2;
l2 = strlen(s2);
if (!l2)
return (char *)s1;
l1 = strlen(s1);
while (l1 >= l2) {
l1--;
if (!memcmp(s1, s2, l2))
return (char *)s1;
s1++;
}
return NULL;
}
void *memchr(const void *s, int c, size_t count)
{
const unsigned char *p = s;
......
omap3-igep0020-3430.dts: omap3-igep0020.dts omap3430-igep.dtsi
sed 's/omap3-igep\.dtsi/omap3430-igep.dtsi/' $< > $@
omap3430-igep.dtsi: omap3-igep.dtsi Makefile
sed 's/omap36xx\.dtsi/omap34xx.dtsi/' $< > $@
ifeq ($(CONFIG_OF),y)
# Keep at91 dtb files sorted alphabetically for each SoC
......
......@@ -125,6 +125,12 @@
clocks = <&clks IMX6QDL_CLK_TWD>;
};
timer@00a00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x00a00200 0x20>;
clocks = <&clks 15>;
};
L2: l2-cache@00a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
......
/*
* Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x)
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "omap3430-igep.dtsi"
#include "omap-gpmc-smsc9221.dtsi"
/ {
model = "IGEPv2 (TI OMAP AM/DM37x)";
compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
leds {
pinctrl-names = "default";
pinctrl-0 = <&leds_pins>;
compatible = "gpio-leds";
boot {
label = "omap3:green:boot";
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
user0 {
label = "omap3:red:user0";
gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
user1 {
label = "omap3:red:user1";
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
user2 {
label = "omap3:green:user1";
gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
};
};
/* HS USB Port 1 Power */
hsusb1_power: hsusb1_power_reg {
compatible = "regulator-fixed";
regulator-name = "hsusb1_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
startup-delay-us = <70000>;
};
/* HS USB Host PHY on PORT 1 */
hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
vcc-supply = <&hsusb1_power>;
};
tfp410: encoder@0 {
compatible = "ti,tfp410";
powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint@0 {
remote-endpoint = <&dpi_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint@0 {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
dvi0: connector@0 {
compatible = "dvi-connector";
label = "dvi";
digital;
ddc-i2c-bus = <&i2c3>;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
};
&omap3_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&tfp410_pins
&dss_dpi_pins
>;
tfp410_pins: pinmux_tfp410_pins {
pinctrl-single,pins = <
0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
>;
};
dss_dpi_pins: pinmux_dss_dpi_pins {
pinctrl-single,pins = <
0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
};
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <
&hsusbb1_pins
>;
hsusbb1_pins: pinmux_hsusbb1_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
>;
};
};
&i2c3 {
clock-frequency = <100000>;
/*
* Display monitor features are burnt in the EEPROM
* as EDID data.
*/
eeprom@50 {
compatible = "ti,eeprom";
reg = <0x50>;
};
};
&gpmc {
ranges = <0 0 0x00000000 0x20000000>,
<5 0 0x2c000000 0x01000000>;
nand@0,0 {
linux,mtd-name= "micron,mt29c4g96maz";
reg = <0 0 0>;
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-off-ns = <40>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SPL";
reg = <0 0x100000>;
};
partition@80000 {
label = "U-Boot";
reg = <0x100000 0x180000>;
};
partition@1c0000 {
label = "Environment";
reg = <0x280000 0x100000>;
};
partition@280000 {
label = "Kernel";
reg = <0x380000 0x300000>;
};
partition@780000 {
label = "Filesystem";
reg = <0x680000 0x1f980000>;
};
};
ethernet@gpmc {
pinctrl-names = "default";
pinctrl-0 = <&smsc9221_pins>;
reg = <5 0 0xff>;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
};
};
&usbhshost {
port1-mode = "ehci-phy";
};
&usbhsehci {
phys = <&hsusb1_phy>;
};
&vpll2 {
/* Needed for DSS */
regulator-name = "vdds_dsi";
};
&dss {
status = "ok";
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
};
/*
* Common device tree for IGEP boards based on AM/DM37x
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "omap34xx-hs.dtsi"
/ {
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "igep2";
ti,mcbsp = <&mcbsp2>;
ti,codec = <&twl_audio>;
};
vdd33: regulator-vdd33 {
compatible = "regulator-fixed";
regulator-name = "vdd33";
regulator-always-on;
};
lbee1usjyc_vmmc: lbee1usjyc_vmmc {
pinctrl-names = "default";
pinctrl-0 = <&lbee1usjyc_pins>;
compatible = "regulator-fixed";
regulator-name = "regulator-lbee1usjyc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */
startup-delay-us = <10000>;
enable-active-high;
vin-supply = <&vdd33>;
};
};
&omap3_pmx_core {
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
>;
};
/* WiFi/BT combo */
lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
pinctrl-single,pins = <
0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */
0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
>;
};
mcbsp2_pins: pinmux_mcbsp2_pins {
pinctrl-single,pins = <
0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
0x10e (PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
0x110 (PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
0x112 (PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
>;
};
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
>;
};
smsc9221_pins: pinmux_smsc9221_pins {
pinctrl-single,pins = <
0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
0x18c (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
};
};
#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
};
&mcbsp2 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vmmc1>;
vmmc_aux-supply = <&vsim>;
bus-width = <4>;
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&lbee1usjyc_vmmc>;
bus-width = <4>;
non-removable;
};
&mmc3 {
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
};
&twl_gpio {
ti,use-leds;
};
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
phys = <&usb2_phy>;
phy-names = "usb2-phy";
mode = <3>;
power = <50>;
};
......@@ -72,6 +72,12 @@
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
};
global_timer: timer@48240200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x48240200 0x20>;
clocks = <&mpu_periphclk>;
};
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
......
......@@ -26,6 +26,7 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/export.h>
#include <linux/ipipe.h>
#include <asm/mach/pci.h>
#include <asm/hardware/it8152.h>
......@@ -124,21 +125,21 @@ void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
while (bits_pd) {
i = __ffs(bits_pd);
generic_handle_irq(IT8152_PD_IRQ(i));
ipipe_handle_demuxed_irq(IT8152_PD_IRQ(i));
bits_pd &= ~(1 << i);
}
bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
while (bits_lp) {
i = __ffs(bits_lp);
generic_handle_irq(IT8152_LP_IRQ(i));
ipipe_handle_demuxed_irq(IT8152_LP_IRQ(i));
bits_lp &= ~(1 << i);
}
bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
while (bits_ld) {
i = __ffs(bits_ld);
generic_handle_irq(IT8152_LD_IRQ(i));
ipipe_handle_demuxed_irq(IT8152_LD_IRQ(i));
bits_ld &= ~(1 << i);
}
}
......
......@@ -29,10 +29,24 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>
#include <linux/module.h>
#include <linux/ipipe.h>
#include <linux/ipipe_tickdev.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/timer-sp.h>
#ifdef CONFIG_IPIPE
static struct __ipipe_tscinfo tsc_info = {
.type = IPIPE_TSC_TYPE_FREERUNNING_COUNTDOWN,
.u = {
{
.mask = 0xffffffff,
},
},
};
#endif /* CONFIG_IPIPE */
static long __init sp804_get_clock_rate(struct clk *clk)
{
long rate;
......@@ -72,6 +86,7 @@ static u64 notrace sp804_read(void)
}
void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
unsigned long phys,
const char *name,
struct clk *clk,
int use_sched_clock)
......@@ -106,12 +121,25 @@ void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
sched_clock_base = base;
sched_clock_register(sp804_read, 32, rate);
}
#ifdef CONFIG_IPIPE
tsc_info.freq = rate;
tsc_info.counter_vaddr = (unsigned long)base + TIMER_VALUE;
tsc_info.u.counter_paddr = phys + TIMER_VALUE;
__ipipe_tsc_register(&tsc_info);
#endif
}
static void __iomem *clkevt_base;
static unsigned long clkevt_reload;
static inline void sp804_timer_ack(void)
{
/* clear the interrupt */
writel(1, clkevt_base + TIMER_INTCLR);
}
/*
* IRQ handler for the timer
*/
......@@ -119,8 +147,8 @@ static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
/* clear the interrupt */
writel(1, clkevt_base + TIMER_INTCLR);
if (!clockevent_ipipe_stolen(evt))
sp804_timer_ack();
evt->event_handler(evt);
......@@ -165,12 +193,21 @@ static int sp804_set_next_event(unsigned long next,
return 0;
}
#ifdef CONFIG_IPIPE
static struct ipipe_timer sp804_itimer = {
.ack = sp804_timer_ack,
};
#endif /* CONFIG_IPIPE */
static struct clock_event_device sp804_clockevent = {
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
CLOCK_EVT_FEAT_DYNIRQ,
.set_mode = sp804_set_mode,
.set_next_event = sp804_set_next_event,
.rating = 300,
#ifdef CONFIG_IPIPE
.ipipe_timer = &sp804_itimer,
#endif /* CONFIG_IPIPE */
};
static struct irqaction sp804_timer_irq = {
......@@ -205,6 +242,10 @@ void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struc
writel(0, base + TIMER_CTRL);
#ifdef CONFIG_IPIPE
sp804_itimer.irq = irq;
#endif /* CONFIG_IPIPE */
setup_irq(irq, &sp804_timer_irq);
clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
}
......@@ -212,6 +253,7 @@ void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struc
static void __init sp804_of_init(struct device_node *np)
{
static bool initialized = false;
struct resource res;
void __iomem *base;
int irq;
u32 irq_num = 0;
......@@ -248,13 +290,18 @@ static void __init sp804_of_init(struct device_node *np)
if (irq <= 0)
goto err;
if (of_address_to_resource(np, 0, &res))
res.start = 0;
of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
if (irq_num == 2) {
__sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
__sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
__sp804_clocksource_and_sched_clock_init(base, res.start,
name, clk1, 1);
} else {
__sp804_clockevents_init(base, irq, clk1 , name);
__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
res.start + TIMER_2_BASE,
name, clk2, 1);
}
initialized = true;
......@@ -268,6 +315,7 @@ CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
static void __init integrator_cp_of_init(struct device_node *np)
{
static int init_count = 0;
struct resource res;
void __iomem *base;
int irq;
const char *name = of_get_property(np, "compatible", NULL);
......@@ -286,8 +334,12 @@ static void __init integrator_cp_of_init(struct device_node *np)
if (init_count == 2 || !of_device_is_available(np))
goto err;
if (of_address_to_resource(np, 0, &res))
res.start = 0;
if (!init_count)
__sp804_clocksource_and_sched_clock_init(base, name, clk, 0);
__sp804_clocksource_and_sched_clock_init(base, res.start,
name, clk, 0);
else {
irq = irq_of_parse_and_map(np, 0);
if (irq <= 0)
......
......@@ -96,6 +96,10 @@ static inline u32 arch_timer_get_cntkctl(void)
static inline void arch_timer_set_cntkctl(u32 cntkctl)
{
#ifdef CONFIG_IPIPE
/* Enable access to user-space (may not be needed) */
cntkctl |= ARCH_TIMER_USR_PCT_ACCESS_EN;
#endif
asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
}
......
......@@ -98,6 +98,18 @@
.macro enable_irq_notrace
cpsie i
.endm
.macro disable_irq_cond
#ifdef CONFIG_IPIPE
cpsid i
#endif /* CONFIG_IPIPE */
.endm
.macro enable_irq_cond
#ifdef CONFIG_IPIPE
cpsie i
#endif /* CONFIG_IPIPE */
.endm
#else
.macro disable_irq_notrace
msr cpsr_c, #PSR_I_BIT | SVC_MODE
......@@ -106,10 +118,22 @@
.macro enable_irq_notrace
msr cpsr_c, #SVC_MODE
.endm
.macro disable_irq_cond
#ifdef CONFIG_IPIPE
msr cpsr_c, #PSR_I_BIT | SVC_MODE
#endif /* CONFIG_IPIPE */
.endm
.macro enable_irq_cond
#ifdef CONFIG_IPIPE
msr cpsr_c, #SVC_MODE
#endif /* CONFIG_IPIPE */
.endm
#endif
.macro asm_trace_hardirqs_off
#if defined(CONFIG_TRACE_IRQFLAGS)
#if defined(CONFIG_TRACE_IRQFLAGS) && !defined(CONFIG_IPIPE)
stmdb sp!, {r0-r3, ip, lr}
bl trace_hardirqs_off
ldmia sp!, {r0-r3, ip, lr}
......@@ -117,7 +141,7 @@
.endm
.macro asm_trace_hardirqs_on_cond, cond
#if defined(CONFIG_TRACE_IRQFLAGS)
#if defined(CONFIG_TRACE_IRQFLAGS) && !defined(CONFIG_IPIPE)
/*
* actually the registers should be pushed and pop'd conditionally, but
* after bl the flags are certainly clobbered
......
......@@ -142,9 +142,9 @@ static inline void atomic_##op(int i, atomic_t *v) \
{ \
unsigned long flags; \
\
raw_local_irq_save(flags); \
flags = hard_local_irq_save(); \
v->counter c_op i; \
raw_local_irq_restore(flags); \
hard_local_irq_restore(flags); \
} \
#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
......@@ -153,10 +153,10 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \
unsigned long flags; \
int val; \
\
raw_local_irq_save(flags); \
flags = hard_local_irq_save(); \
v->counter c_op i; \
val = v->counter; \
raw_local_irq_restore(flags); \
hard_local_irq_restore(flags); \
\
return val; \
}
......@@ -166,11 +166,11 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
int ret;
unsigned long flags;
raw_local_irq_save(flags);
flags = hard_local_irq_save();
ret = v->counter;
if (likely(ret == old))
v->counter = new;
raw_local_irq_restore(flags);
hard_local_irq_restore(flags);
return ret;
}
......@@ -346,7 +346,6 @@ static inline long long atomic64_cmpxchg(atomic64_t *ptr, long long old,
: "cc");
} while (res);
smp_mb();
return oldval;
}
......
......@@ -16,27 +16,35 @@
#if __LINUX_ARM_ARCH__ >= 7
#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")
#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")
#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")
#define DMB(option) "dmb " #option
#define DMB_IN
#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
: : "r" (0) : "memory")
#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
#define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
: : "r" (0) : "memory")
#define DMB(option) "mcr p15, 0, %0, c7, c10, 5"
#define DMB_IN "r" (0)
#elif defined(CONFIG_CPU_FA526)
#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
: : "r" (0) : "memory")
#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
#else
#define isb(x) __asm__ __volatile__ ("" : : : "memory")
#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
: : "r" (0) : "memory")
#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
#endif
#ifdef DMB
#define dmb(option) __asm__ __volatile__(DMB(option) : : DMB_IN : "memory")
#else
#define dmb(option) __asm__ __volatile__("" : : : "memory")
#endif
#ifdef CONFIG_ARCH_HAS_BARRIERS
#include <mach/barriers.h>
#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
......@@ -54,9 +62,35 @@
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#else
#define smp_mb() dmb(ish)
#define smp_rmb() smp_mb()
#define smp_wmb() dmb(ishst)
#ifdef CONFIG_THUMB2_KERNEL
#define SMP_ONLY(smp) \
"9998: " smp "\n" \
" .pushsection \".alt.smp.init\", \"a\"\n" \
" .long 9998b\n" \
" nop.w\n" \
" .popsection\n"
#else
#define SMP_ONLY(smp) \
"9998: " smp "\n" \
" .pushsection \".alt.smp.init\", \"a\"\n" \
" .long 9998b\n" \
" nop\n" \
" .popsection\n"
#endif
#ifdef DMB
#define smp_mb() \
__asm__ __volatile__ (SMP_ONLY(DMB(ish)) : : DMB_IN : "memory")
#define smp_rmb() \
__asm__ __volatile__ (SMP_ONLY(DMB(ish)) : : DMB_IN : "memory")
#define smp_wmb() \
__asm__ __volatile__ (SMP_ONLY(DMB(ishst)) : : DMB_IN : "memory")
#else
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#endif
#endif
#define smp_store_release(p, v) \
......
......@@ -39,9 +39,9 @@ static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *
p += bit >> 5;
raw_local_irq_save(flags);
flags = hard_local_irq_save();
*p |= mask;
raw_local_irq_restore(flags);
hard_local_irq_restore(flags);
}
static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
......@@ -51,9 +51,9 @@ static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long
p += bit >> 5;
raw_local_irq_save(flags);
flags = hard_local_irq_save();
*p &= ~mask;
raw_local_irq_restore(flags);
hard_local_irq_restore(flags);
}
static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
......@@ -63,9 +63,9 @@ static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned lon
p += bit >> 5;
raw_local_irq_save(flags);
flags = hard_local_irq_save();
*p ^= mask;
raw_local_irq_restore(flags);
hard_local_irq_restore(flags);
}
static inline int
......@@ -77,10 +77,10 @@ ____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
p += bit >> 5;
raw_local_irq_save(flags);
flags = hard_local_irq_save();
res = *p;
*p = res | mask;
raw_local_irq_restore(flags);
hard_local_irq_restore(flags);
r