spmi-pmic-arb.c 36.2 KB
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/*
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 * Copyright (c) 2012-2015, 2017, The Linux Foundation. All rights reserved.
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
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#include <linux/bitmap.h>
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#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
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#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
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#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spmi.h>

/* PMIC Arbiter configuration registers */
#define PMIC_ARB_VERSION		0x0000
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#define PMIC_ARB_VERSION_V2_MIN		0x20010000
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#define PMIC_ARB_VERSION_V3_MIN		0x30000000
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#define PMIC_ARB_VERSION_V5_MIN		0x50000000
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#define PMIC_ARB_INT_EN			0x0004

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/* PMIC Arbiter channel registers offsets */
#define PMIC_ARB_CMD			0x00
#define PMIC_ARB_CONFIG			0x04
#define PMIC_ARB_STATUS			0x08
#define PMIC_ARB_WDATA0			0x10
#define PMIC_ARB_WDATA1			0x14
#define PMIC_ARB_RDATA0			0x18
#define PMIC_ARB_RDATA1			0x1C
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/* Mapping Table */
#define SPMI_MAPPING_TABLE_REG(N)	(0x0B00 + (4 * (N)))
#define SPMI_MAPPING_BIT_INDEX(X)	(((X) >> 18) & 0xF)
#define SPMI_MAPPING_BIT_IS_0_FLAG(X)	(((X) >> 17) & 0x1)
#define SPMI_MAPPING_BIT_IS_0_RESULT(X)	(((X) >> 9) & 0xFF)
#define SPMI_MAPPING_BIT_IS_1_FLAG(X)	(((X) >> 8) & 0x1)
#define SPMI_MAPPING_BIT_IS_1_RESULT(X)	(((X) >> 0) & 0xFF)

#define SPMI_MAPPING_TABLE_TREE_DEPTH	16	/* Maximum of 16-bits */
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#define PMIC_ARB_MAX_PPID		BIT(12) /* PPID is 12bit */
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#define PMIC_ARB_APID_VALID		BIT(15)
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#define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg)	((reg) & BIT(24))
#define INVALID_EE				0xFF
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/* Ownership Table */
#define SPMI_OWNERSHIP_TABLE_REG(N)	(0x0700 + (4 * (N)))
#define SPMI_OWNERSHIP_PERIPH2OWNER(X)	((X) & 0x7)

/* Channel Status fields */
enum pmic_arb_chnl_status {
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	PMIC_ARB_STATUS_DONE	= BIT(0),
	PMIC_ARB_STATUS_FAILURE	= BIT(1),
	PMIC_ARB_STATUS_DENIED	= BIT(2),
	PMIC_ARB_STATUS_DROPPED	= BIT(3),
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};

/* Command register fields */
#define PMIC_ARB_CMD_MAX_BYTE_COUNT	8

/* Command Opcodes */
enum pmic_arb_cmd_op_code {
	PMIC_ARB_OP_EXT_WRITEL = 0,
	PMIC_ARB_OP_EXT_READL = 1,
	PMIC_ARB_OP_EXT_WRITE = 2,
	PMIC_ARB_OP_RESET = 3,
	PMIC_ARB_OP_SLEEP = 4,
	PMIC_ARB_OP_SHUTDOWN = 5,
	PMIC_ARB_OP_WAKEUP = 6,
	PMIC_ARB_OP_AUTHENTICATE = 7,
	PMIC_ARB_OP_MSTR_READ = 8,
	PMIC_ARB_OP_MSTR_WRITE = 9,
	PMIC_ARB_OP_EXT_READ = 13,
	PMIC_ARB_OP_WRITE = 14,
	PMIC_ARB_OP_READ = 15,
	PMIC_ARB_OP_ZERO_WRITE = 16,
};

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/*
 * PMIC arbiter version 5 uses different register offsets for read/write vs
 * observer channels.
 */
enum pmic_arb_channel {
	PMIC_ARB_CHANNEL_RW,
	PMIC_ARB_CHANNEL_OBS,
};

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/* Maximum number of support PMIC peripherals */
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#define PMIC_ARB_MAX_PERIPHS		512
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#define PMIC_ARB_TIMEOUT_US		100
#define PMIC_ARB_MAX_TRANS_BYTES	(8)

#define PMIC_ARB_APID_MASK		0xFF
#define PMIC_ARB_PPID_MASK		0xFFF

/* interrupt enable bit */
#define SPMI_PIC_ACC_ENABLE_BIT		BIT(0)

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#define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
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	((((slave_id) & 0xF)   << 28) | \
	(((periph_id) & 0xFF)  << 20) | \
	(((irq_id)    & 0x7)   << 16) | \
	(((apid)      & 0x1FF) << 0))

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#define hwirq_to_sid(hwirq)  (((hwirq) >> 28) & 0xF)
#define hwirq_to_per(hwirq)  (((hwirq) >> 20) & 0xFF)
#define hwirq_to_irq(hwirq)  (((hwirq) >> 16) & 0x7)
#define hwirq_to_apid(hwirq) (((hwirq) >> 0)  & 0x1FF)
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struct pmic_arb_ver_ops;

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struct apid_data {
	u16		ppid;
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	u8		write_ee;
	u8		irq_ee;
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};

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/**
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 * spmi_pmic_arb - SPMI PMIC Arbiter object
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 *
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 * @rd_base:		on v1 "core", on v2 "observer" register base off DT.
 * @wr_base:		on v1 "core", on v2 "chnls"    register base off DT.
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 * @intr:		address of the SPMI interrupt control registers.
 * @cnfg:		address of the PMIC Arbiter configuration registers.
 * @lock:		lock to synchronize accesses.
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 * @channel:		execution environment channel to use for accesses.
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 * @irq:		PMIC ARB interrupt.
 * @ee:			the current Execution Environment
 * @min_apid:		minimum APID (used for bounding IRQ search)
 * @max_apid:		maximum APID
 * @mapping_table:	in-memory copy of PPID -> APID mapping table.
 * @domain:		irq domain object for PMIC IRQ domain
 * @spmic:		SPMI controller object
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 * @ver_ops:		version dependent operations.
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 * @ppid_to_apid	in-memory copy of PPID -> APID mapping table.
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 */
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struct spmi_pmic_arb {
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	void __iomem		*rd_base;
	void __iomem		*wr_base;
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	void __iomem		*intr;
	void __iomem		*cnfg;
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	void __iomem		*core;
	resource_size_t		core_size;
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	raw_spinlock_t		lock;
	u8			channel;
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	int			irq;
	u8			ee;
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	u16			min_apid;
	u16			max_apid;
	u32			*mapping_table;
	DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
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	struct irq_domain	*domain;
	struct spmi_controller	*spmic;
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	const struct pmic_arb_ver_ops *ver_ops;
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	u16			*ppid_to_apid;
	u16			last_apid;
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	struct apid_data	apid_data[PMIC_ARB_MAX_PERIPHS];
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};

/**
 * pmic_arb_ver: version dependent functionality.
 *
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 * @ver_str:		version string.
 * @ppid_to_apid:	finds the apid for a given ppid.
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 * @non_data_cmd:	on v1 issues an spmi non-data command.
 *			on v2 no HW support, returns -EOPNOTSUPP.
 * @offset:		on v1 offset of per-ee channel.
 *			on v2 offset of per-ee and per-ppid channel.
 * @fmt_cmd:		formats a GENI/SPMI command.
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 * @owner_acc_status:	on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
 *			on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn.
 * @acc_enable:		on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
 *			on v2 address of SPMI_PIC_ACC_ENABLEn.
 * @irq_status:		on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
 *			on v2 address of SPMI_PIC_IRQ_STATUSn.
 * @irq_clear:		on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
 *			on v2 address of SPMI_PIC_IRQ_CLEARn.
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 * @apid_map_offset:	offset of PMIC_ARB_REG_CHNLn
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 */
struct pmic_arb_ver_ops {
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	const char *ver_str;
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	int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
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	/* spmi commands (read_cmd, write_cmd, cmd) functionality */
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	int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
			enum pmic_arb_channel ch_type);
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	u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
	int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
	/* Interrupts controller functionality (offset of PIC registers) */
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	void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
					  u16 n);
	void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
	void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
	void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
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	u32 (*apid_map_offset)(u16 n);
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};

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static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
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				       u32 offset, u32 val)
{
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	writel_relaxed(val, pmic_arb->wr_base + offset);
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}

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static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,
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				       u32 offset, u32 val)
{
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	writel_relaxed(val, pmic_arb->rd_base + offset);
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}

/**
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 * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
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 * @bc:		byte count -1. range: 0..3
 * @reg:	register's address
 * @buf:	output parameter, length must be bc + 1
 */
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static void
pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)
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{
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	u32 data = __raw_readl(pmic_arb->rd_base + reg);
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	memcpy(buf, &data, (bc & 3) + 1);
}

/**
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 * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register
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 * @bc:		byte-count -1. range: 0..3.
 * @reg:	register's address.
 * @buf:	buffer to write. length must be bc + 1.
 */
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static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,
				u32 reg, u8 bc)
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{
	u32 data = 0;
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	memcpy(&data, buf, (bc & 3) + 1);
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	__raw_writel(data, pmic_arb->wr_base + reg);
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}

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static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
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				  void __iomem *base, u8 sid, u16 addr,
				  enum pmic_arb_channel ch_type)
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{
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	struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
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	u32 status = 0;
	u32 timeout = PMIC_ARB_TIMEOUT_US;
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	u32 offset;
	int rc;

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	rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
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	if (rc < 0)
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		return rc;

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	offset = rc;
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	offset += PMIC_ARB_STATUS;
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	while (timeout--) {
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		status = readl_relaxed(base + offset);
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		if (status & PMIC_ARB_STATUS_DONE) {
			if (status & PMIC_ARB_STATUS_DENIED) {
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				dev_err(&ctrl->dev, "%s: transaction denied (0x%x)\n",
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					__func__, status);
				return -EPERM;
			}

			if (status & PMIC_ARB_STATUS_FAILURE) {
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				dev_err(&ctrl->dev, "%s: transaction failed (0x%x)\n",
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					__func__, status);
				return -EIO;
			}

			if (status & PMIC_ARB_STATUS_DROPPED) {
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				dev_err(&ctrl->dev, "%s: transaction dropped (0x%x)\n",
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					__func__, status);
				return -EIO;
			}

			return 0;
		}
		udelay(1);
	}

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	dev_err(&ctrl->dev, "%s: timeout, status 0x%x\n",
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		__func__, status);
	return -ETIMEDOUT;
}

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static int
pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
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{
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	struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
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	unsigned long flags;
	u32 cmd;
	int rc;
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	u32 offset;

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	rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
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	if (rc < 0)
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		return rc;
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	offset = rc;
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	cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);

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	raw_spin_lock_irqsave(&pmic_arb->lock, flags);
	pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
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	rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,
				    PMIC_ARB_CHANNEL_RW);
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	raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
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	return rc;
}

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static int
pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)
{
	return -EOPNOTSUPP;
}

/* Non-data command */
static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
{
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	struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
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	dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);

	/* Check for valid non-data command */
	if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
		return -EINVAL;

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	return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
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}

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static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
			     u16 addr, u8 *buf, size_t len)
{
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	struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
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	unsigned long flags;
	u8 bc = len - 1;
	u32 cmd;
	int rc;
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	u32 offset;

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	rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
				       PMIC_ARB_CHANNEL_OBS);
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	if (rc < 0)
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		return rc;
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	offset = rc;
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	if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
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		dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
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			PMIC_ARB_MAX_TRANS_BYTES, len);
		return  -EINVAL;
	}

	/* Check the opcode */
	if (opc >= 0x60 && opc <= 0x7F)
		opc = PMIC_ARB_OP_READ;
	else if (opc >= 0x20 && opc <= 0x2F)
		opc = PMIC_ARB_OP_EXT_READ;
	else if (opc >= 0x38 && opc <= 0x3F)
		opc = PMIC_ARB_OP_EXT_READL;
	else
		return -EINVAL;

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	cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
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	raw_spin_lock_irqsave(&pmic_arb->lock, flags);
	pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
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	rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,
				    PMIC_ARB_CHANNEL_OBS);
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	if (rc)
		goto done;

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	pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
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		     min_t(u8, bc, 3));

	if (bc > 3)
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		pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1,
					bc - 4);
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done:
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	raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
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	return rc;
}

static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
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			u16 addr, const u8 *buf, size_t len)
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{
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	struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
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	unsigned long flags;
	u8 bc = len - 1;
	u32 cmd;
	int rc;
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	u32 offset;

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	rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
					PMIC_ARB_CHANNEL_RW);
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	if (rc < 0)
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		return rc;
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	offset = rc;
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	if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
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		dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
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			PMIC_ARB_MAX_TRANS_BYTES, len);
		return  -EINVAL;
	}

	/* Check the opcode */
	if (opc >= 0x40 && opc <= 0x5F)
		opc = PMIC_ARB_OP_WRITE;
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	else if (opc <= 0x0F)
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		opc = PMIC_ARB_OP_EXT_WRITE;
	else if (opc >= 0x30 && opc <= 0x37)
		opc = PMIC_ARB_OP_EXT_WRITEL;
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	else if (opc >= 0x80)
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		opc = PMIC_ARB_OP_ZERO_WRITE;
	else
		return -EINVAL;

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	cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
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	/* Write data to FIFOs */
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	raw_spin_lock_irqsave(&pmic_arb->lock, flags);
	pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
				min_t(u8, bc, 3));
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	if (bc > 3)
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		pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1,
					bc - 4);
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	/* Start the transaction */
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	pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
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	rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,
				    PMIC_ARB_CHANNEL_RW);
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	raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
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	return rc;
}

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enum qpnpint_regs {
	QPNPINT_REG_RT_STS		= 0x10,
	QPNPINT_REG_SET_TYPE		= 0x11,
	QPNPINT_REG_POLARITY_HIGH	= 0x12,
	QPNPINT_REG_POLARITY_LOW	= 0x13,
	QPNPINT_REG_LATCHED_CLR		= 0x14,
	QPNPINT_REG_EN_SET		= 0x15,
	QPNPINT_REG_EN_CLR		= 0x16,
	QPNPINT_REG_LATCHED_STS		= 0x18,
};

struct spmi_pmic_arb_qpnpint_type {
	u8 type; /* 1 -> edge */
	u8 polarity_high;
	u8 polarity_low;
} __packed;

/* Simplified accessor functions for irqchip callbacks */
static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
			       size_t len)
{
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	struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
	u8 sid = hwirq_to_sid(d->hwirq);
	u8 per = hwirq_to_per(d->hwirq);
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	if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
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			       (per << 8) + reg, buf, len))
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		dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
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				    d->irq);
}

static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
{
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	struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
	u8 sid = hwirq_to_sid(d->hwirq);
	u8 per = hwirq_to_per(d->hwirq);
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	if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid,
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			      (per << 8) + reg, buf, len))
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		dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
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				    d->irq);
}

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static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
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{
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	u16 ppid = pmic_arb->apid_data[apid].ppid;
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	u8 sid = ppid >> 8;
	u8 per = ppid & 0xFF;
	u8 irq_mask = BIT(id);

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	writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
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	if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
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			(per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1))
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		dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
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				irq_mask, ppid);

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	if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
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			       (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1))
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		dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
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				irq_mask, ppid);
}

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static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
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{
	unsigned int irq;
	u32 status;
	int id;
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	u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF;
	u8 per = pmic_arb->apid_data[apid].ppid & 0xFF;
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	status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid));
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	while (status) {
		id = ffs(status) - 1;
524
		status &= ~BIT(id);
525 526
		irq = irq_find_mapping(pmic_arb->domain,
					spec_to_hwirq(sid, per, id, apid));
527
		if (irq == 0) {
528
			cleanup_irq(pmic_arb, apid, id);
529 530
			continue;
		}
531 532 533 534
		generic_handle_irq(irq);
	}
}

535
static void pmic_arb_chained_irq(struct irq_desc *desc)
536
{
537
	struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc);
538
	const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
539
	struct irq_chip *chip = irq_desc_get_chip(desc);
540 541
	int first = pmic_arb->min_apid >> 5;
	int last = pmic_arb->max_apid >> 5;
542
	u8 ee = pmic_arb->ee;
543 544
	u32 status, enable;
	int i, id, apid;
545 546 547 548

	chained_irq_enter(chip, desc);

	for (i = first; i <= last; ++i) {
549 550
		status = readl_relaxed(
				ver_ops->owner_acc_status(pmic_arb, ee, i));
551 552
		while (status) {
			id = ffs(status) - 1;
553
			status &= ~BIT(id);
554
			apid = id + i * 32;
555 556
			enable = readl_relaxed(
					ver_ops->acc_enable(pmic_arb, apid));
557
			if (enable & SPMI_PIC_ACC_ENABLE_BIT)
558
				periph_interrupt(pmic_arb, apid);
559 560 561 562 563 564 565 566
		}
	}

	chained_irq_exit(chip, desc);
}

static void qpnpint_irq_ack(struct irq_data *d)
{
567 568 569
	struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
	u8 irq = hwirq_to_irq(d->hwirq);
	u16 apid = hwirq_to_apid(d->hwirq);
570 571
	u8 data;

572
	writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
573

574
	data = BIT(irq);
575 576 577 578 579
	qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
}

static void qpnpint_irq_mask(struct irq_data *d)
{
580
	u8 irq = hwirq_to_irq(d->hwirq);
581
	u8 data = BIT(irq);
582 583 584 585 586 587

	qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
}

static void qpnpint_irq_unmask(struct irq_data *d)
{
588
	struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
589
	const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
590 591
	u8 irq = hwirq_to_irq(d->hwirq);
	u16 apid = hwirq_to_apid(d->hwirq);
592
	u8 buf[2];
593

594
	writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
595
			ver_ops->acc_enable(pmic_arb, apid));
596

597 598 599 600 601 602 603 604 605 606 607
	qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);
	if (!(buf[0] & BIT(irq))) {
		/*
		 * Since the interrupt is currently disabled, write to both the
		 * LATCHED_CLR and EN_SET registers so that a spurious interrupt
		 * cannot be triggered when the interrupt is enabled
		 */
		buf[0] = BIT(irq);
		buf[1] = BIT(irq);
		qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2);
	}
608 609 610 611 612
}

static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct spmi_pmic_arb_qpnpint_type type;
613
	irq_flow_handler_t flow_handler;
614
	u8 irq = hwirq_to_irq(d->hwirq);
615 616 617 618

	qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));

	if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
619
		type.type |= BIT(irq);
620
		if (flow_type & IRQF_TRIGGER_RISING)
621
			type.polarity_high |= BIT(irq);
622
		if (flow_type & IRQF_TRIGGER_FALLING)
623 624 625
			type.polarity_low  |= BIT(irq);

		flow_handler = handle_edge_irq;
626 627 628 629 630
	} else {
		if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
		    (flow_type & (IRQF_TRIGGER_LOW)))
			return -EINVAL;

631
		type.type &= ~BIT(irq); /* level trig */
632
		if (flow_type & IRQF_TRIGGER_HIGH)
633
			type.polarity_high |= BIT(irq);
634
		else
635 636 637
			type.polarity_low  |= BIT(irq);

		flow_handler = handle_level_irq;
638 639 640
	}

	qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
641
	irq_set_handler_locked(d, flow_handler);
642

643 644 645
	return 0;
}

646 647 648 649 650 651 652
static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);

	return irq_set_irq_wake(pmic_arb->irq, on);
}

653 654 655 656
static int qpnpint_get_irqchip_state(struct irq_data *d,
				     enum irqchip_irq_state which,
				     bool *state)
{
657
	u8 irq = hwirq_to_irq(d->hwirq);
658 659 660 661 662 663 664 665 666 667 668
	u8 status = 0;

	if (which != IRQCHIP_STATE_LINE_LEVEL)
		return -EINVAL;

	qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1);
	*state = !!(status & BIT(irq));

	return 0;
}

669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686
static int qpnpint_irq_request_resources(struct irq_data *d)
{
	struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
	u16 periph = hwirq_to_per(d->hwirq);
	u16 apid = hwirq_to_apid(d->hwirq);
	u16 sid = hwirq_to_sid(d->hwirq);
	u16 irq = hwirq_to_irq(d->hwirq);

	if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
		dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
			sid, periph, irq, pmic_arb->ee,
			pmic_arb->apid_data[apid].irq_ee);
		return -ENODEV;
	}

	return 0;
}

687 688 689 690 691 692
static struct irq_chip pmic_arb_irqchip = {
	.name		= "pmic_arb",
	.irq_ack	= qpnpint_irq_ack,
	.irq_mask	= qpnpint_irq_mask,
	.irq_unmask	= qpnpint_irq_unmask,
	.irq_set_type	= qpnpint_irq_set_type,
693
	.irq_set_wake	= qpnpint_irq_set_wake,
694
	.irq_get_irqchip_state	= qpnpint_get_irqchip_state,
695
	.irq_request_resources = qpnpint_irq_request_resources,
696
	.flags		= IRQCHIP_MASK_ON_SUSPEND,
697 698 699 700 701 702 703 704 705
};

static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
					   struct device_node *controller,
					   const u32 *intspec,
					   unsigned int intsize,
					   unsigned long *out_hwirq,
					   unsigned int *out_type)
{
706
	struct spmi_pmic_arb *pmic_arb = d->host_data;
707
	u16 apid, ppid;
708
	int rc;
709

710
	dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
711 712
		intspec[0], intspec[1], intspec[2]);

713
	if (irq_domain_get_of_node(d) != controller)
714 715 716 717 718 719
		return -EINVAL;
	if (intsize != 4)
		return -EINVAL;
	if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
		return -EINVAL;

720 721
	ppid = intspec[0] << 8 | intspec[1];
	rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
722
	if (rc < 0) {
723
		dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
724 725 726
		intspec[0], intspec[1], intspec[2], rc);
		return rc;
	}
727

728
	apid = rc;
729
	/* Keep track of {max,min}_apid for bounding search during interrupt */
730 731 732 733
	if (apid > pmic_arb->max_apid)
		pmic_arb->max_apid = apid;
	if (apid < pmic_arb->min_apid)
		pmic_arb->min_apid = apid;
734

735
	*out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid);
736 737
	*out_type  = intspec[3] & IRQ_TYPE_SENSE_MASK;

738
	dev_dbg(&pmic_arb->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
739 740 741 742 743 744 745 746

	return 0;
}

static int qpnpint_irq_domain_map(struct irq_domain *d,
				  unsigned int virq,
				  irq_hw_number_t hwirq)
{
747
	struct spmi_pmic_arb *pmic_arb = d->host_data;
748

749
	dev_dbg(&pmic_arb->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq);
750 751 752 753 754 755 756

	irq_set_chip_and_handler(virq, &pmic_arb_irqchip, handle_level_irq);
	irq_set_chip_data(virq, d->host_data);
	irq_set_noprobe(virq);
	return 0;
}

757
static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
758
{
759
	u32 *mapping_table = pmic_arb->mapping_table;
760 761
	int index = 0, i;
	u16 apid_valid;
762
	u16 apid;
763 764
	u32 data;

765 766
	apid_valid = pmic_arb->ppid_to_apid[ppid];
	if (apid_valid & PMIC_ARB_APID_VALID) {
767 768
		apid = apid_valid & ~PMIC_ARB_APID_VALID;
		return apid;
769 770 771
	}

	for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
772 773
		if (!test_and_set_bit(index, pmic_arb->mapping_table_valid))
			mapping_table[index] = readl_relaxed(pmic_arb->cnfg +
774 775 776 777 778 779 780 781
						SPMI_MAPPING_TABLE_REG(index));

		data = mapping_table[index];

		if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) {
			if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
				index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
			} else {
782
				apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
783
				pmic_arb->ppid_to_apid[ppid]
784 785 786
					= apid | PMIC_ARB_APID_VALID;
				pmic_arb->apid_data[apid].ppid = ppid;
				return apid;
787 788 789 790 791
			}
		} else {
			if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
				index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
			} else {
792
				apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
793
				pmic_arb->ppid_to_apid[ppid]
794 795 796
					= apid | PMIC_ARB_APID_VALID;
				pmic_arb->apid_data[apid].ppid = ppid;
				return apid;
797 798 799 800 801 802 803
			}
		}
	}

	return -ENODEV;
}

804
/* v1 offset per ee */
805 806
static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
			enum pmic_arb_channel ch_type)
807
{
808
	return 0x800 + 0x80 * pmic_arb->channel;
809 810
}

811
static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
812
{
813
	struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
814
	u32 regval, offset;
815
	u16 id, apid;
816

817
	for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
818
		offset = pmic_arb->ver_ops->apid_map_offset(apid);
819
		if (offset >= pmic_arb->core_size)
820 821
			break;

822
		regval = readl_relaxed(pmic_arb->cnfg +
823
				      SPMI_OWNERSHIP_TABLE_REG(apid));
824 825
		apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
		apidd->write_ee = apidd->irq_ee;
826

827
		regval = readl_relaxed(pmic_arb->core + offset);
828 829 830 831
		if (!regval)
			continue;

		id = (regval >> 8) & PMIC_ARB_PPID_MASK;
832
		pmic_arb->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
833
		apidd->ppid = id;
834
		if (id == ppid) {
835
			apid |= PMIC_ARB_APID_VALID;
836 837 838
			break;
		}
	}
839
	pmic_arb->last_apid = apid & ~PMIC_ARB_APID_VALID;
840

841
	return apid;
842 843
}

844
static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
845
{
846
	u16 apid_valid;
847

848 849 850 851
	apid_valid = pmic_arb->ppid_to_apid[ppid];
	if (!(apid_valid & PMIC_ARB_APID_VALID))
		apid_valid = pmic_arb_find_apid(pmic_arb, ppid);
	if (!(apid_valid & PMIC_ARB_APID_VALID))
852 853
		return -ENODEV;

854
	return apid_valid & ~PMIC_ARB_APID_VALID;
855 856
}

857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931
static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
{
	struct apid_data *apidd = pmic_arb->apid_data;
	struct apid_data *prev_apidd;
	u16 i, apid, ppid;
	bool valid, is_irq_ee;
	u32 regval, offset;

	/*
	 * In order to allow multiple EEs to write to a single PPID in arbiter
	 * version 5, there is more than one APID mapped to each PPID.
	 * The owner field for each of these mappings specifies the EE which is
	 * allowed to write to the APID.  The owner of the last (highest) APID
	 * for a given PPID will receive interrupts from the PPID.
	 */
	for (i = 0; ; i++, apidd++) {
		offset = pmic_arb->ver_ops->apid_map_offset(i);
		if (offset >= pmic_arb->core_size)
			break;

		regval = readl_relaxed(pmic_arb->core + offset);
		if (!regval)
			continue;
		ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
		is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);

		regval = readl_relaxed(pmic_arb->cnfg +
				      SPMI_OWNERSHIP_TABLE_REG(i));
		apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);

		apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;

		valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
		apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
		prev_apidd = &pmic_arb->apid_data[apid];

		if (valid && is_irq_ee &&
				prev_apidd->write_ee == pmic_arb->ee) {
			/*
			 * Duplicate PPID mapping after the one for this EE;
			 * override the irq owner
			 */
			prev_apidd->irq_ee = apidd->irq_ee;
		} else if (!valid || is_irq_ee) {
			/* First PPID mapping or duplicate for another EE */
			pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
		}

		apidd->ppid = ppid;
		pmic_arb->last_apid = i;
	}

	/* Dump the mapping table for debug purposes. */
	dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
	for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {
		apid = pmic_arb->ppid_to_apid[ppid];
		if (apid & PMIC_ARB_APID_VALID) {
			apid &= ~PMIC_ARB_APID_VALID;
			apidd = &pmic_arb->apid_data[apid];
			dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
			      ppid, apid, apidd->write_ee, apidd->irq_ee);
		}
	}

	return 0;
}

static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
{
	if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
		return -ENODEV;

	return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
}

932
/* v2 offset per ppid and per ee */
933 934
static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
			   enum pmic_arb_channel ch_type)
935
{
936
	u16 apid;
937
	u16 ppid;
938
	int rc;
939

940 941
	ppid = sid << 8 | ((addr >> 8) & 0xFF);
	rc = pmic_arb_ppid_to_apid_v2(pmic_arb, ppid);
942 943
	if (rc < 0)
		return rc;
944

945 946
	apid = rc;
	return 0x1000 * pmic_arb->ee + 0x8000 * apid;
947 948
}

949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977
/*
 * v5 offset per ee and per apid for observer channels and per apid for
 * read/write channels.
 */
static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
			   enum pmic_arb_channel ch_type)
{
	u16 apid;
	int rc;
	u32 offset = 0;
	u16 ppid = (sid << 8) | (addr >> 8);

	rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
	if (rc < 0)
		return rc;

	apid = rc;
	switch (ch_type) {
	case PMIC_ARB_CHANNEL_OBS:
		offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
		break;
	case PMIC_ARB_CHANNEL_RW:
		offset = 0x10000 * apid;
		break;
	}

	return offset;
}

978 979 980 981 982 983 984 985 986 987
static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
{
	return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
}

static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
{
	return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
}

988 989
static void __iomem *
pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
990
{
991
	return pmic_arb->intr + 0x20 * m + 0x4 * n;
992 993
}

994 995
static void __iomem *
pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
996
{
997
	return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n;
998 999
}

1000 1001
static void __iomem *
pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1002
{
1003
	return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
1004 1005
}

1006 1007 1008 1009 1010 1011
static void __iomem *
pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
{
	return pmic_arb->intr + 0x10000 * m + 0x4 * n;
}

1012 1013
static void __iomem *
pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1014
{
1015
	return pmic_arb->intr + 0x200 + 0x4 * n;
1016 1017
}

1018 1019
static void __iomem *
pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1020
{
1021
	return pmic_arb->intr + 0x1000 * n;
1022 1023
}

1024 1025 1026 1027 1028 1029
static void __iomem *
pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
{
	return pmic_arb->wr_base + 0x100 + 0x10000 * n;
}

1030 1031
static void __iomem *
pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1032
{
1033
	return pmic_arb->intr + 0x600 + 0x4 * n;
1034 1035
}

1036 1037
static void __iomem *
pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1038
{
1039
	return pmic_arb->intr + 0x4 + 0x1000 * n;
1040 1041
}

1042 1043 1044 1045 1046 1047
static void __iomem *
pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
{
	return pmic_arb->wr_base + 0x104 + 0x10000 * n;
}

1048 1049
static void __iomem *
pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1050
{
1051
	return pmic_arb->intr + 0xA00 + 0x4 * n;
1052 1053
}

1054 1055
static void __iomem *
pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1056
{
1057
	return pmic_arb->intr + 0x8 + 0x1000 * n;
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}

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static void __iomem *
pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
{
	return pmic_arb->wr_base + 0x108 + 0x10000 * n;
}

static u32 pmic_arb_apid_map_offset_v2(u16 n)
{
	return 0x800 + 0x4 * n;
}

static u32 pmic_arb_apid_map_offset_v5(u16 n)
{
	return 0x900 + 0x4 * n;
}

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static const struct pmic_arb_ver_ops pmic_arb_v1 = {
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	.ver_str		= "v1",
1078
	.ppid_to_apid		= pmic_arb_ppid_to_apid_v1,
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	.non_data_cmd		= pmic_arb_non_data_cmd_v1,
	.offset			= pmic_arb_offset_v1,
	.fmt_cmd		= pmic_arb_fmt_cmd_v1,
	.owner_acc_status	= pmic_arb_owner_acc_status_v1,
	.acc_enable		= pmic_arb_acc_enable_v1,
	.irq_status		= pmic_arb_irq_status_v1,
	.irq_clear		= pmic_arb_irq_clear_v1,
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	.apid_map_offset	= pmic_arb_apid_map_offset_v2,
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};

static const struct pmic_arb_ver_ops pmic_arb_v2 = {
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	.ver_str		= "v2",
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	.ppid_to_apid		= pmic_arb_ppid_to_apid_v2,
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	.non_data_cmd		= pmic_arb_non_data_cmd_v2,
	.offset			= pmic_arb_offset_v2,
	.fmt_cmd		= pmic_arb_fmt_cmd_v2,
	.owner_acc_status	= pmic_arb_owner_acc_status_v2,
	.acc_enable		= pmic_arb_acc_enable_v2,
	.irq_status		= pmic_arb_irq_status_v2,
	.irq_clear		= pmic_arb_irq_clear_v2,
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	.apid_map_offset	= pmic_arb_apid_map_offset_v2,
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};

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static const struct pmic_arb_ver_ops pmic_arb_v3 = {
	.ver_str		= "v3",
	.ppid_to_apid		= pmic_arb_ppid_to_apid_v2,
	.non_data_cmd		= pmic_arb_non_data_cmd_v2,
	.offset			= pmic_arb_offset_v2,
	.fmt_cmd		= pmic_arb_fmt_cmd_v2,
	.owner_acc_status	= pmic_arb_owner_acc_status_v3,
	.acc_enable		= pmic_arb_acc_enable_v2,
	.irq_status		= pmic_arb_irq_status_v2,
	.irq_clear		= pmic_arb_irq_clear_v2,
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	.apid_map_offset	= pmic_arb_apid_map_offset_v2,
};

static const struct pmic_arb_ver_ops pmic_arb_v5 = {
	.ver_str		= "v5",
	.ppid_to_apid		= pmic_arb_ppid_to_apid_v5,
	.non_data_cmd		= pmic_arb_non_data_cmd_v2,
	.offset			= pmic_arb_offset_v5,
	.fmt_cmd		= pmic_arb_fmt_cmd_v2,
	.owner_acc_status	= pmic_arb_owner_acc_status_v5,
	.acc_enable		= pmic_arb_acc_enable_v5,
	.irq_status		= pmic_arb_irq_status_v5,
	.irq_clear		= pmic_arb_irq_clear_v5,
	.apid_map_offset	= pmic_arb_apid_map_offset_v5,