pciehp_hpc.c 23.9 KB
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// SPDX-License-Identifier: GPL-2.0+
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/*
 * PCI Express PCI Hot Plug Driver
 *
 * Copyright (C) 1995,2001 Compaq Computer Corporation
 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
 * Copyright (C) 2001 IBM Corp.
 * Copyright (C) 2003-2004 Intel Corporation
 *
 * All rights reserved.
 *
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 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
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 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
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#include <linux/signal.h>
#include <linux/jiffies.h>
#include <linux/timer.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/slab.h>
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#include "../pci.h"
#include "pciehp.h"

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static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
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{
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	return ctrl->pcie->port;
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}
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static irqreturn_t pcie_isr(int irq, void *dev_id);
static void start_int_poll_timer(struct controller *ctrl, int sec);
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/* This is the interrupt polling timeout function. */
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static void int_poll_timeout(struct timer_list *t)
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{
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	struct controller *ctrl = from_timer(ctrl, t, poll_timer);
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	/* Poll for interrupt events.  regs == NULL => polling */
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	pcie_isr(0, ctrl);
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	if (!pciehp_poll_time)
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		pciehp_poll_time = 2; /* default polling interval is 2 sec */
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	start_int_poll_timer(ctrl, pciehp_poll_time);
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}

/* This function starts the interrupt polling timer. */
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static void start_int_poll_timer(struct controller *ctrl, int sec)
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{
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	/* Clamp to sane value */
	if ((sec <= 0) || (sec > 60))
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		sec = 2;
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	ctrl->poll_timer.expires = jiffies + sec * HZ;
	add_timer(&ctrl->poll_timer);
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}

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static inline int pciehp_request_irq(struct controller *ctrl)
{
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	int retval, irq = ctrl->pcie->irq;
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	/* Install interrupt polling timer. Start with 10 sec delay */
	if (pciehp_poll_mode) {
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		timer_setup(&ctrl->poll_timer, int_poll_timeout, 0);
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		start_int_poll_timer(ctrl, 10);
		return 0;
	}

	/* Installs the interrupt handler */
	retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
	if (retval)
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		ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
			 irq);
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	return retval;
}

static inline void pciehp_free_irq(struct controller *ctrl)
{
	if (pciehp_poll_mode)
		del_timer_sync(&ctrl->poll_timer);
	else
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		free_irq(ctrl->pcie->irq, ctrl);
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}

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static int pcie_poll_cmd(struct controller *ctrl, int timeout)
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{
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	struct pci_dev *pdev = ctrl_dev(ctrl);
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	u16 slot_status;

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	while (true) {
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		pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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		if (slot_status == (u16) ~0) {
			ctrl_info(ctrl, "%s: no response from device\n",
				  __func__);
			return 0;
		}

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		if (slot_status & PCI_EXP_SLTSTA_CC) {
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			pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
						   PCI_EXP_SLTSTA_CC);
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			return 1;
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		}
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		if (timeout < 0)
			break;
		msleep(10);
		timeout -= 10;
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	}
	return 0;	/* timeout */
}

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static void pcie_wait_cmd(struct controller *ctrl)
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{
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	unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
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	unsigned long duration = msecs_to_jiffies(msecs);
	unsigned long cmd_timeout = ctrl->cmd_started + duration;
	unsigned long now, timeout;
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	int rc;

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	/*
	 * If the controller does not generate notifications for command
	 * completions, we never need to wait between writes.
	 */
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	if (NO_CMD_CMPL(ctrl))
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		return;

	if (!ctrl->cmd_busy)
		return;

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	/*
	 * Even if the command has already timed out, we want to call
	 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
	 */
	now = jiffies;
	if (time_before_eq(cmd_timeout, now))
		timeout = 1;
	else
		timeout = cmd_timeout - now;

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	if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
	    ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
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		rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
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	else
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		rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
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	if (!rc)
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		ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
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			  ctrl->slot_ctrl,
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			  jiffies_to_msecs(jiffies - ctrl->cmd_started));
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}

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#define CC_ERRATUM_MASK		(PCI_EXP_SLTCTL_PCC |	\
				 PCI_EXP_SLTCTL_PIC |	\
				 PCI_EXP_SLTCTL_AIC |	\
				 PCI_EXP_SLTCTL_EIC)

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static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
			      u16 mask, bool wait)
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{
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	struct pci_dev *pdev = ctrl_dev(ctrl);
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	u16 slot_ctrl_orig, slot_ctrl;
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	mutex_lock(&ctrl->ctrl_lock);

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	/*
	 * Always wait for any previous command that might still be in progress
	 */
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	pcie_wait_cmd(ctrl);

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	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
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	if (slot_ctrl == (u16) ~0) {
		ctrl_info(ctrl, "%s: no response from device\n", __func__);
		goto out;
	}

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	slot_ctrl_orig = slot_ctrl;
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	slot_ctrl &= ~mask;
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	slot_ctrl |= (cmd & mask);
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	ctrl->cmd_busy = 1;
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	smp_mb();
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	pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
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	ctrl->cmd_started = jiffies;
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	ctrl->slot_ctrl = slot_ctrl;
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	/*
	 * Controllers with the Intel CF118 and similar errata advertise
	 * Command Completed support, but they only set Command Completed
	 * if we change the "Control" bits for power, power indicator,
	 * attention indicator, or interlock.  If we only change the
	 * "Enable" bits, they never set the Command Completed bit.
	 */
	if (pdev->broken_cmd_compl &&
	    (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
		ctrl->cmd_busy = 0;

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	/*
	 * Optionally wait for the hardware to be ready for a new command,
	 * indicating completion of the above issued command.
	 */
	if (wait)
		pcie_wait_cmd(ctrl);

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out:
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	mutex_unlock(&ctrl->ctrl_lock);
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}

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/**
 * pcie_write_cmd - Issue controller command
 * @ctrl: controller to which the command is issued
 * @cmd:  command value written to slot control register
 * @mask: bitmask of slot control register to be modified
 */
static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
{
	pcie_do_write_cmd(ctrl, cmd, mask, true);
}

/* Same as above without waiting for the hardware to latch */
static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
{
	pcie_do_write_cmd(ctrl, cmd, mask, false);
}

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bool pciehp_check_link_active(struct controller *ctrl)
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{
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	struct pci_dev *pdev = ctrl_dev(ctrl);
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	u16 lnk_status;
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	bool ret;
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	pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
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	ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);

	if (ret)
		ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);

	return ret;
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}

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static void pcie_wait_link_active(struct controller *ctrl)
{
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	struct pci_dev *pdev = ctrl_dev(ctrl);

	pcie_wait_for_link(pdev, true);
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}

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static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
{
	u32 l;
	int count = 0;
	int delay = 1000, step = 20;
	bool found = false;

	do {
		found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
		count++;

		if (found)
			break;

		msleep(step);
		delay -= step;
	} while (delay > 0);

	if (count > 1 && pciehp_debug)
		printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
			pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
			PCI_FUNC(devfn), count, step, l);

	return found;
}

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int pciehp_check_link_status(struct controller *ctrl)
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{
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	struct pci_dev *pdev = ctrl_dev(ctrl);
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	bool found;
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	u16 lnk_status;

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	/*
	 * Data Link Layer Link Active Reporting must be capable for
	 * hot-plug capable downstream port. But old controller might
	 * not implement it. In this case, we wait for 1000 ms.
	*/
	if (ctrl->link_active_reporting)
		pcie_wait_link_active(ctrl);
	else
		msleep(1000);
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	/* wait 100ms before read pci conf, and try in 1s */
	msleep(100);
	found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
					PCI_DEVFN(0, 0));
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	pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
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	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
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	if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
	    !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
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		ctrl_err(ctrl, "link training error: status %#06x\n",
			 lnk_status);
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		return -1;
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	}

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	pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);

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	if (!found)
		return -1;
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	return 0;
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}

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static int __pciehp_link_set(struct controller *ctrl, bool enable)
{
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	struct pci_dev *pdev = ctrl_dev(ctrl);
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	u16 lnk_ctrl;

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	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
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	if (enable)
		lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
	else
		lnk_ctrl |= PCI_EXP_LNKCTL_LD;

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	pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
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	ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
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	return 0;
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}

static int pciehp_link_enable(struct controller *ctrl)
{
	return __pciehp_link_set(ctrl, true);
}

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int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
				    u8 *status)
{
	struct slot *slot = hotplug_slot->private;
	struct pci_dev *pdev = ctrl_dev(slot->ctrl);
	u16 slot_ctrl;

	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
	*status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
	return 0;
}

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void pciehp_get_attention_status(struct slot *slot, u8 *status)
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{
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	struct controller *ctrl = slot->ctrl;
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	struct pci_dev *pdev = ctrl_dev(ctrl);
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	u16 slot_ctrl;

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	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
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	switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
	case PCI_EXP_SLTCTL_ATTN_IND_ON:
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		*status = 1;	/* On */
		break;
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	case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
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		*status = 2;	/* Blink */
		break;
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	case PCI_EXP_SLTCTL_ATTN_IND_OFF:
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		*status = 0;	/* Off */
		break;
	default:
		*status = 0xFF;
		break;
	}
}

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void pciehp_get_power_status(struct slot *slot, u8 *status)
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{
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	struct controller *ctrl = slot->ctrl;
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	struct pci_dev *pdev = ctrl_dev(ctrl);
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	u16 slot_ctrl;

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	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
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	switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
	case PCI_EXP_SLTCTL_PWR_ON:
		*status = 1;	/* On */
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		break;
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	case PCI_EXP_SLTCTL_PWR_OFF:
		*status = 0;	/* Off */
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		break;
	default:
		*status = 0xFF;
		break;
	}
}

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void pciehp_get_latch_status(struct slot *slot, u8 *status)
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{
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	struct pci_dev *pdev = ctrl_dev(slot->ctrl);
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	u16 slot_status;

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	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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	*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
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}

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void pciehp_get_adapter_status(struct slot *slot, u8 *status)
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{
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	struct pci_dev *pdev = ctrl_dev(slot->ctrl);
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	u16 slot_status;

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	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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	*status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
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}

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int pciehp_query_power_fault(struct slot *slot)
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{
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	struct pci_dev *pdev = ctrl_dev(slot->ctrl);
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	u16 slot_status;

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	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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	return !!(slot_status & PCI_EXP_SLTSTA_PFD);
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}

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int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
				    u8 status)
{
	struct slot *slot = hotplug_slot->private;
	struct controller *ctrl = slot->ctrl;

	pcie_write_cmd_nowait(ctrl, status << 6,
			      PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
	return 0;
}

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void pciehp_set_attention_status(struct slot *slot, u8 value)
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{
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	struct controller *ctrl = slot->ctrl;
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	u16 slot_cmd;
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	if (!ATTN_LED(ctrl))
		return;

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	switch (value) {
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	case 0:		/* turn off */
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		slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
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		break;
	case 1:		/* turn on */
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		slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
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		break;
	case 2:		/* turn blink */
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		slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
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		break;
	default:
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		return;
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	}
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	pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
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}

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void pciehp_green_led_on(struct slot *slot)
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{
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	struct controller *ctrl = slot->ctrl;
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	if (!PWR_LED(ctrl))
		return;

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	pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
			      PCI_EXP_SLTCTL_PIC);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
		 PCI_EXP_SLTCTL_PWR_IND_ON);
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}

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void pciehp_green_led_off(struct slot *slot)
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{
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	struct controller *ctrl = slot->ctrl;
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	if (!PWR_LED(ctrl))
		return;

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	pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
			      PCI_EXP_SLTCTL_PIC);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
		 PCI_EXP_SLTCTL_PWR_IND_OFF);
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}

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void pciehp_green_led_blink(struct slot *slot)
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{
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	struct controller *ctrl = slot->ctrl;
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	if (!PWR_LED(ctrl))
		return;

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	pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
			      PCI_EXP_SLTCTL_PIC);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
		 PCI_EXP_SLTCTL_PWR_IND_BLINK);
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}

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int pciehp_power_on_slot(struct slot *slot)
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{
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	struct controller *ctrl = slot->ctrl;
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	struct pci_dev *pdev = ctrl_dev(ctrl);
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	u16 slot_status;
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	int retval;
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	/* Clear sticky power-fault bit from previous power failures */
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	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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	if (slot_status & PCI_EXP_SLTSTA_PFD)
		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
					   PCI_EXP_SLTSTA_PFD);
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	ctrl->power_fault_detected = 0;
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	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
		 PCI_EXP_SLTCTL_PWR_ON);
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	retval = pciehp_link_enable(ctrl);
	if (retval)
		ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);

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	return retval;
}

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void pciehp_power_off_slot(struct slot *slot)
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{
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	struct controller *ctrl = slot->ctrl;
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	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
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		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
		 PCI_EXP_SLTCTL_PWR_OFF);
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}

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static irqreturn_t pciehp_isr(int irq, void *dev_id)
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{
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	struct controller *ctrl = (struct controller *)dev_id;
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	struct pci_dev *pdev = ctrl_dev(ctrl);
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	struct slot *slot = ctrl->slot;
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	u16 status, events;
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	u8 present;
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	bool link;
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	/* Interrupts cannot originate from a controller that's asleep */
	if (pdev->current_state == PCI_D3cold)
		return IRQ_NONE;

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	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
	if (status == (u16) ~0) {
		ctrl_info(ctrl, "%s: no response from device\n", __func__);
		return IRQ_NONE;
	}

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	/*
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	 * Slot Status contains plain status bits as well as event
	 * notification bits; right now we only want the event bits.
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	 */
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	events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
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			   PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
			   PCI_EXP_SLTSTA_DLLSC);
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	/*
	 * If we've already reported a power fault, don't report it again
	 * until we've done something to handle it.
	 */
	if (ctrl->power_fault_detected)
		events &= ~PCI_EXP_SLTSTA_PFD;

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	if (!events)
		return IRQ_NONE;
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	/* Capture link status before clearing interrupts */
	if (events & PCI_EXP_SLTSTA_DLLSC)
		link = pciehp_check_link_active(ctrl);

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	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
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	ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
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	/* Check Command Complete Interrupt Pending */
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	if (events & PCI_EXP_SLTSTA_CC) {
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		ctrl->cmd_busy = 0;
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		smp_mb();
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		wake_up(&ctrl->queue);
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	}

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	if (pdev->ignore_hotplug) {
		ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
		return IRQ_HANDLED;
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	}

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	/* Check Attention Button Pressed */
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	if (events & PCI_EXP_SLTSTA_ABP) {
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		ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
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			  slot_name(slot));
		pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS);
	}
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	/*
	 * Check Link Status Changed at higher precedence than Presence
	 * Detect Changed.  The PDS value may be set to "card present" from
	 * out-of-band detection, which may be in conflict with a Link Down
	 * and cause the wrong event to queue.
	 */
	if (events & PCI_EXP_SLTSTA_DLLSC) {
		ctrl_info(ctrl, "Slot(%s): Link %s\n", slot_name(slot),
			  link ? "Up" : "Down");
		pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP :
					     INT_LINK_DOWN);
	} else if (events & PCI_EXP_SLTSTA_PDC) {
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		present = !!(status & PCI_EXP_SLTSTA_PDS);
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		ctrl_info(ctrl, "Slot(%s): Card %spresent\n", slot_name(slot),
			  present ? "" : "not ");
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		pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON :
					     INT_PRESENCE_OFF);
	}
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	/* Check Power Fault Detected */
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	if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
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		ctrl->power_fault_detected = 1;
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		ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
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		pciehp_queue_interrupt_event(slot, INT_POWER_FAULT);
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	}
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	return IRQ_HANDLED;
}

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static irqreturn_t pcie_isr(int irq, void *dev_id)
{
	irqreturn_t rc, handled = IRQ_NONE;

	/*
	 * To guarantee that all interrupt events are serviced, we need to
	 * re-inspect Slot Status register after clearing what is presumed
	 * to be the last pending interrupt.
	 */
	do {
		rc = pciehp_isr(irq, dev_id);
		if (rc == IRQ_HANDLED)
			handled = IRQ_HANDLED;
	} while (rc == IRQ_HANDLED);

	/* Return IRQ_HANDLED if we handled one or more events */
	return handled;
}

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static void pcie_enable_notification(struct controller *ctrl)
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{
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	u16 cmd, mask;
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	/*
	 * TBD: Power fault detected software notification support.
	 *
	 * Power fault detected software notification is not enabled
	 * now, because it caused power fault detected interrupt storm
	 * on some machines. On those machines, power fault detected
	 * bit in the slot status register was set again immediately
	 * when it is cleared in the interrupt service routine, and
	 * next power fault detected interrupt was notified again.
	 */
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	/*
	 * Always enable link events: thus link-up and link-down shall
	 * always be treated as hotplug and unplug respectively. Enable
	 * presence detect only if Attention Button is not present.
	 */
	cmd = PCI_EXP_SLTCTL_DLLSCE;
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	if (ATTN_BUTTN(ctrl))
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		cmd |= PCI_EXP_SLTCTL_ABPE;
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	else
		cmd |= PCI_EXP_SLTCTL_PDCE;
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	if (!pciehp_poll_mode)
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		cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
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	mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
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		PCI_EXP_SLTCTL_PFDE |
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		PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
		PCI_EXP_SLTCTL_DLLSCE);
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	pcie_write_cmd_nowait(ctrl, cmd, mask);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
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}

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void pcie_reenable_notification(struct controller *ctrl)
{
	/*
	 * Clear both Presence and Data Link Layer Changed to make sure
	 * those events still fire after we have re-enabled them.
	 */
	pcie_capability_write_word(ctrl->pcie->port, PCI_EXP_SLTSTA,
				   PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
	pcie_enable_notification(ctrl);
}

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static void pcie_disable_notification(struct controller *ctrl)
{
	u16 mask;
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	mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
		PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
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		PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
		PCI_EXP_SLTCTL_DLLSCE);
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	pcie_write_cmd(ctrl, 0, mask);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
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}

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/*
 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
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 * bus reset of the bridge, but at the same time we want to ensure that it is
 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
 * disable link state notification and presence detection change notification
 * momentarily, if we see that they could interfere. Also, clear any spurious
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 * events after.
 */
int pciehp_reset_slot(struct slot *slot, int probe)
{
	struct controller *ctrl = slot->ctrl;
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	struct pci_dev *pdev = ctrl_dev(ctrl);
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	u16 stat_mask = 0, ctrl_mask = 0;
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	if (probe)
		return 0;

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	if (!ATTN_BUTTN(ctrl)) {
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		ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
		stat_mask |= PCI_EXP_SLTSTA_PDC;
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	}
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	ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
	stat_mask |= PCI_EXP_SLTSTA_DLLSC;

	pcie_write_cmd(ctrl, 0, ctrl_mask);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
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	if (pciehp_poll_mode)
		del_timer_sync(&ctrl->poll_timer);
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	pci_reset_bridge_secondary_bus(ctrl->pcie->port);

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	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
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	pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
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	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
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	if (pciehp_poll_mode)
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		int_poll_timeout(&ctrl->poll_timer);
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	return 0;
}

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int pcie_init_notification(struct controller *ctrl)
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{
	if (pciehp_request_irq(ctrl))
		return -1;
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	pcie_enable_notification(ctrl);
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	ctrl->notification_enabled = 1;
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	return 0;
}

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void pcie_shutdown_notification(struct controller *ctrl)
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{
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	if (ctrl->notification_enabled) {
		pcie_disable_notification(ctrl);
		pciehp_free_irq(ctrl);
		ctrl->notification_enabled = 0;
	}
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}

static int pcie_init_slot(struct controller *ctrl)
{
	struct slot *slot;

	slot = kzalloc(sizeof(*slot), GFP_KERNEL);
	if (!slot)
		return -ENOMEM;

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	slot->wq = alloc_ordered_workqueue("pciehp-%u", 0, PSN(ctrl));
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	if (!slot->wq)
		goto abort;

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	slot->ctrl = ctrl;
	mutex_init(&slot->lock);
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	mutex_init(&slot->hotplug_lock);
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	INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
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	ctrl->slot = slot;
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	return 0;
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abort:
	kfree(slot);
	return -ENOMEM;
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}
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static void pcie_cleanup_slot(struct controller *ctrl)
{
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	struct slot *slot = ctrl->slot;
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	destroy_workqueue(slot->wq);
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	kfree(slot);
}

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static inline void dbg_ctrl(struct controller *ctrl)
802
{
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	struct pci_dev *pdev = ctrl->pcie->port;
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	u16 reg16;
805

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	if (!pciehp_debug)
		return;
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	ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
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	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
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	ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
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	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
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	ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
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}
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#define FLAG(x, y)	(((x) & (y)) ? '+' : '-')
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struct controller *pcie_init(struct pcie_device *dev)
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{
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	struct controller *ctrl;
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	u32 slot_cap, link_cap;
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	struct pci_dev *pdev = dev->port;
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	ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
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	if (!ctrl)
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		goto abort;
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	ctrl->pcie = dev;
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	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
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	if (pdev->hotplug_user_indicators)
		slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);

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	/*
	 * We assume no Thunderbolt controllers support Command Complete events,
	 * but some controllers falsely claim they do.
	 */
	if (pdev->is_thunderbolt)
		slot_cap |= PCI_EXP_SLTCAP_NCCS;

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	ctrl->slot_cap = slot_cap;
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	mutex_init(&ctrl->ctrl_lock);
	init_waitqueue_head(&ctrl->queue);
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	dbg_ctrl(ctrl);
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	/* Check if Data Link Layer Link Active Reporting is implemented */
	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
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	if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
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		ctrl->link_active_reporting = 1;
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	/*
	 * Clear all remaining event bits in Slot Status register except
	 * Presence Detect Changed. We want to make sure possible
	 * hotplug event is triggered when the interrupt is unmasked so
	 * that we don't lose that event.
	 */
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	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
		PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
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		PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
		PCI_EXP_SLTSTA_DLLSC);
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	ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c%s\n",
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		(slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
		FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
		FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
		FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
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		FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
		FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
		FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
		FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
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		FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
		FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
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		FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
		pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
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	if (pcie_init_slot(ctrl))
		goto abort_ctrl;
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	return ctrl;

abort_ctrl:
	kfree(ctrl);
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abort:
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	return NULL;
}

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void pciehp_release_ctrl(struct controller *ctrl)
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{
	pcie_cleanup_slot(ctrl);
	kfree(ctrl);
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}
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static void quirk_cmd_compl(struct pci_dev *pdev)
{
	u32 slot_cap;

	if (pci_is_pcie(pdev)) {
		pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
		if (slot_cap & PCI_EXP_SLTCAP_HPC &&
		    !(slot_cap & PCI_EXP_SLTCAP_NCCS))
			pdev->broken_cmd_compl = 1;
	}
}
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);