Commit 18a52b74 authored by Greg Gallagher's avatar Greg Gallagher Committed by Philippe Gerum

pinctrl: rockchip: enable interrupt pipelining

Fix up the pin controller driver of the Rockchip SoC in order to
channel interrupts through the interrupt pipeline.
parent e7c0ba7b
......@@ -2637,7 +2637,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
u32 polarity;
u32 level;
u32 data;
unsigned long flags;
unsigned long flags, flags2;
int ret;
/* make sure the pin is configured as gpio input */
......@@ -2660,7 +2660,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
irq_set_handler_locked(d, handle_level_irq);
raw_spin_lock_irqsave(&bank->slock, flags);
irq_gc_lock(gc);
flags2 = irq_gc_lock(gc);
level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
......@@ -2701,7 +2701,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
polarity &= ~mask;
break;
default:
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags2);
raw_spin_unlock_irqrestore(&bank->slock, flags);
clk_disable(bank->clk);
return -EINVAL;
......@@ -2710,7 +2710,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
irq_gc_unlock(gc);
irq_gc_unlock(gc, flags2);
raw_spin_unlock_irqrestore(&bank->slock, flags);
clk_disable(bank->clk);
......
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