Commit 3ca7ddda authored by Vladimir Zapolskiy's avatar Vladimir Zapolskiy Committed by Greg Kroah-Hartman

spi: sh-msiof: Fix bit field overflow writes to TSCR/RSCR

[ Upstream commit 10b46408 ]

The change fixes a bit field overflow which allows to write to higher
bits while calculating SPI transfer clock and setting BRPS and BRDV
bit fields, the problem is reproduced if 'parent_rate' to 'spi_hz'
ratio is greater than 1024, for instance

  p->min_div      = 2,
  MSO rate        = 33333333,
  SPI device rate = 10000

results in

  k          = 5, i.e. BRDV = 0b100 or 1/32 prescaler output,
  BRPS       = 105,
  TSCR value = 0x6804, thus MSSEL and MSIMM bit fields are non-zero.

Fixes: 65d5665b ("spi: sh-msiof: Update calculation of frequency dividing")
Signed-off-by: default avatarVladimir Zapolskiy <>
Signed-off-by: default avatarMark Brown <>
Signed-off-by: default avatarSasha Levin <>
Signed-off-by: default avatarGreg Kroah-Hartman <>
parent b3ccb8a7
......@@ -277,6 +277,7 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
brps = min_t(int, brps, 32);
scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
sh_msiof_write(p, TSCR, scr);
Markdown is supported
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment