Commit c6754712 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman

Merge tag 'iio-fixes-for-4.16a' of...

Merge tag 'iio-fixes-for-4.16a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-linus

Jonathan writes:

First round of IIO fixes for the 4.16 cycle.

One nasty very old crash around polling for buffers that aren't there
- though that can only cause effects on drivers that support events
but not buffers.

* buffer / kfifo handling in the core.
  - Check there is a buffer and return 0 from poll directly if there
    isn't.  Poll doesn't make sense in this circumstances, but best to close
    the hole.
* ad5933
  - Change the marked buffer mode to a software buffer as the meaning of
    the hardware buffer label has long since changed and this uses a front
    end software buffer anyway.
* ad7192
  - Fix the fact the external clock frequency was only set when using the
    internal clock which was less than helpful.
* adis_lib
  - Initialize the trigger before requesting the interrupt.  Some newer
    parts can power up with interrupt generation enabled so ordering now
    matters.
* aspeed-adc
  - Fix an errror handling path as labels and general ordering were wrong.
* srf08
  - Fix a link error due to undefined devm_iio_triggered_buffer_setup.
* stm32-adc
  - Fix error handling unwind squence in stm32h7_adc_enable.
parents 6d79bd5b 4cd140bd
......@@ -243,7 +243,7 @@ static int aspeed_adc_probe(struct platform_device *pdev)
ASPEED_ADC_INIT_POLLING_TIME,
ASPEED_ADC_INIT_TIMEOUT);
if (ret)
goto scaler_error;
goto poll_timeout_error;
}
/* Start all channels in normal mode. */
......@@ -274,9 +274,10 @@ static int aspeed_adc_probe(struct platform_device *pdev)
writel(ASPEED_OPERATION_MODE_POWER_DOWN,
data->base + ASPEED_REG_ENGINE_CONTROL);
clk_disable_unprepare(data->clk_scaler->clk);
reset_error:
reset_control_assert(data->rst);
clk_enable_error:
poll_timeout_error:
reset_control_assert(data->rst);
reset_error:
clk_hw_unregister_divider(data->clk_scaler);
scaler_error:
clk_hw_unregister_divider(data->clk_prescaler);
......
......@@ -722,8 +722,6 @@ static int stm32h7_adc_enable(struct stm32_adc *adc)
int ret;
u32 val;
/* Clear ADRDY by writing one, then enable ADC */
stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
/* Poll for ADRDY to be set (after adc startup time) */
......@@ -731,8 +729,11 @@ static int stm32h7_adc_enable(struct stm32_adc *adc)
val & STM32H7_ADRDY,
100, STM32_ADC_TIMEOUT_US);
if (ret) {
stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
dev_err(&indio_dev->dev, "Failed to enable ADC\n");
} else {
/* Clear ADRDY by writing one */
stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
}
return ret;
......
......@@ -46,6 +46,10 @@ int adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev)
if (adis->trig == NULL)
return -ENOMEM;
adis->trig->dev.parent = &adis->spi->dev;
adis->trig->ops = &adis_trigger_ops;
iio_trigger_set_drvdata(adis->trig, adis);
ret = request_irq(adis->spi->irq,
&iio_trigger_generic_data_rdy_poll,
IRQF_TRIGGER_RISING,
......@@ -54,9 +58,6 @@ int adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev)
if (ret)
goto error_free_trig;
adis->trig->dev.parent = &adis->spi->dev;
adis->trig->ops = &adis_trigger_ops;
iio_trigger_set_drvdata(adis->trig, adis);
ret = iio_trigger_register(adis->trig);
indio_dev->trig = iio_trigger_get(adis->trig);
......
......@@ -175,7 +175,7 @@ __poll_t iio_buffer_poll(struct file *filp,
struct iio_dev *indio_dev = filp->private_data;
struct iio_buffer *rb = indio_dev->buffer;
if (!indio_dev->info)
if (!indio_dev->info || rb == NULL)
return 0;
poll_wait(filp, &rb->pollq, wait);
......
......@@ -68,6 +68,8 @@ config SX9500
config SRF08
tristate "Devantech SRF02/SRF08/SRF10 ultrasonic ranger sensor"
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
depends on I2C
help
Say Y here to build a driver for Devantech SRF02/SRF08/SRF10
......
......@@ -141,6 +141,8 @@
#define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
#define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
#define AD7192_EXT_FREQ_MHZ_MIN 2457600
#define AD7192_EXT_FREQ_MHZ_MAX 5120000
#define AD7192_INT_FREQ_MHZ 4915200
/* NOTE:
......@@ -218,6 +220,12 @@ static int ad7192_calibrate_all(struct ad7192_state *st)
ARRAY_SIZE(ad7192_calib_arr));
}
static inline bool ad7192_valid_external_frequency(u32 freq)
{
return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
freq <= AD7192_EXT_FREQ_MHZ_MAX);
}
static int ad7192_setup(struct ad7192_state *st,
const struct ad7192_platform_data *pdata)
{
......@@ -243,17 +251,20 @@ static int ad7192_setup(struct ad7192_state *st,
id);
switch (pdata->clock_source_sel) {
case AD7192_CLK_EXT_MCLK1_2:
case AD7192_CLK_EXT_MCLK2:
st->mclk = AD7192_INT_FREQ_MHZ;
break;
case AD7192_CLK_INT:
case AD7192_CLK_INT_CO:
if (pdata->ext_clk_hz)
st->mclk = pdata->ext_clk_hz;
else
st->mclk = AD7192_INT_FREQ_MHZ;
st->mclk = AD7192_INT_FREQ_MHZ;
break;
case AD7192_CLK_EXT_MCLK1_2:
case AD7192_CLK_EXT_MCLK2:
if (ad7192_valid_external_frequency(pdata->ext_clk_hz)) {
st->mclk = pdata->ext_clk_hz;
break;
}
dev_err(&st->sd.spi->dev, "Invalid frequency setting %u\n",
pdata->ext_clk_hz);
ret = -EINVAL;
goto out;
default:
ret = -EINVAL;
goto out;
......
......@@ -648,8 +648,6 @@ static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev)
/* Ring buffer functions - here trigger setup related */
indio_dev->setup_ops = &ad5933_ring_setup_ops;
indio_dev->modes |= INDIO_BUFFER_HARDWARE;
return 0;
}
......@@ -762,7 +760,7 @@ static int ad5933_probe(struct i2c_client *client,
indio_dev->dev.parent = &client->dev;
indio_dev->info = &ad5933_info;
indio_dev->name = id->name;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->modes = (INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE);
indio_dev->channels = ad5933_channels;
indio_dev->num_channels = ARRAY_SIZE(ad5933_channels);
......
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