Commit c8fe6a68 authored by Zhi Wang's avatar Zhi Wang Committed by Zhenyu Wang

drm/i915/gvt: vGPU interrupt virtualization.

This patch introduces vGPU interrupt emulation framework.

The vGPU intrerrupt emulation framework is an event-based interrupt
emulation framework. It's responsible for emulating GEN hardware interrupts
during emulating other HW behaviour.

It consists several components:

- Descriptions of interrupt register bit
- Upper level <-> lower level interrupt mapping
- GEN HW IER/IMR/IIR register emulation routines
- Event-based interrupt propagation interface

When a GVT-g component wants to inject an interrupt to a VM during a
emulation, first it should specify the event needs to be emulated and the
framework will deal with the rest of emulation:

- Generating related virtual IIR bit according to virtual IER and IMRs,
- Generate related virtual upper level virtual IIR bit accodring to the
per-platform interrupt mapping
- Injecting a MSI to VM
Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 3f728236
GVT_DIR := gvt
GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o
GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
interrupt.o
ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) -Wall
i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
......@@ -30,8 +30,7 @@
#define gvt_dbg_core(fmt, args...) \
DRM_DEBUG_DRIVER("gvt: core: "fmt, ##args)
/*
* Other GVT debug stuff will be introduced in the GVT device model patches.
*/
#define gvt_dbg_irq(fmt, args...) \
DRM_DEBUG_DRIVER("gvt: irq: "fmt, ##args)
#endif
......@@ -97,9 +97,10 @@ static void init_device_info(struct intel_gvt *gvt)
if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {
info->max_support_vgpus = 8;
info->mmio_size = 2 * 1024 * 1024;
info->cfg_space_size = 256;
info->mmio_size = 2 * 1024 * 1024;
info->mmio_bar = 0;
info->msi_cap_offset = IS_SKYLAKE(gvt->dev_priv) ? 0xac : 0x90;
}
}
......@@ -118,6 +119,7 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv)
if (WARN_ON(!gvt->initialized))
return;
intel_gvt_clean_irq(gvt);
intel_gvt_clean_mmio_info(gvt);
intel_gvt_free_firmware(gvt);
......@@ -165,10 +167,16 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv)
if (ret)
goto out_clean_mmio_info;
ret = intel_gvt_init_irq(gvt);
if (ret)
goto out_free_firmware;
gvt_dbg_core("gvt device creation is done\n");
gvt->initialized = true;
return 0;
out_free_firmware:
intel_gvt_free_firmware(gvt);
out_clean_mmio_info:
intel_gvt_clean_mmio_info(gvt);
return ret;
......
......@@ -37,6 +37,7 @@
#include "hypercall.h"
#include "mmio.h"
#include "reg.h"
#include "interrupt.h"
#define GVT_MAX_VGPU 8
......@@ -56,9 +57,10 @@ extern struct intel_gvt_host intel_gvt_host;
/* Describe per-platform limitations. */
struct intel_gvt_device_info {
u32 max_support_vgpus;
u32 mmio_size;
u32 cfg_space_size;
u32 mmio_size;
u32 mmio_bar;
unsigned long msi_cap_offset;
};
/* GM resources owned by a vGPU */
......@@ -98,6 +100,10 @@ struct intel_vgpu_cfg_space {
#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
struct intel_vgpu_irq {
bool irq_warn_once[INTEL_GVT_EVENT_MAX];
};
struct intel_vgpu {
struct intel_gvt *gvt;
int id;
......@@ -109,6 +115,7 @@ struct intel_vgpu {
struct intel_vgpu_gm gm;
struct intel_vgpu_cfg_space cfg_space;
struct intel_vgpu_mmio mmio;
struct intel_vgpu_irq irq;
};
struct intel_gvt_gm {
......@@ -145,6 +152,7 @@ struct intel_gvt {
struct intel_gvt_fence fence;
struct intel_gvt_mmio mmio;
struct intel_gvt_firmware firmware;
struct intel_gvt_irq irq;
};
void intel_gvt_free_firmware(struct intel_gvt *gvt);
......
......@@ -41,6 +41,7 @@ struct intel_gvt_mpt {
int (*detect_host)(void);
int (*attach_vgpu)(void *vgpu, unsigned long *handle);
void (*detach_vgpu)(unsigned long handle);
int (*inject_msi)(unsigned long handle, u32 addr, u16 data);
};
extern struct intel_gvt_mpt xengt_mpt;
......
This diff is collapsed.
/*
* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors:
* Kevin Tian <kevin.tian@intel.com>
* Zhi Wang <zhi.a.wang@intel.com>
*
* Contributors:
* Min he <min.he@intel.com>
*
*/
#ifndef _GVT_INTERRUPT_H_
#define _GVT_INTERRUPT_H_
enum intel_gvt_event_type {
RCS_MI_USER_INTERRUPT = 0,
RCS_DEBUG,
RCS_MMIO_SYNC_FLUSH,
RCS_CMD_STREAMER_ERR,
RCS_PIPE_CONTROL,
RCS_L3_PARITY_ERR,
RCS_WATCHDOG_EXCEEDED,
RCS_PAGE_DIRECTORY_FAULT,
RCS_AS_CONTEXT_SWITCH,
RCS_MONITOR_BUFF_HALF_FULL,
VCS_MI_USER_INTERRUPT,
VCS_MMIO_SYNC_FLUSH,
VCS_CMD_STREAMER_ERR,
VCS_MI_FLUSH_DW,
VCS_WATCHDOG_EXCEEDED,
VCS_PAGE_DIRECTORY_FAULT,
VCS_AS_CONTEXT_SWITCH,
VCS2_MI_USER_INTERRUPT,
VCS2_MI_FLUSH_DW,
VCS2_AS_CONTEXT_SWITCH,
BCS_MI_USER_INTERRUPT,
BCS_MMIO_SYNC_FLUSH,
BCS_CMD_STREAMER_ERR,
BCS_MI_FLUSH_DW,
BCS_PAGE_DIRECTORY_FAULT,
BCS_AS_CONTEXT_SWITCH,
VECS_MI_USER_INTERRUPT,
VECS_MI_FLUSH_DW,
VECS_AS_CONTEXT_SWITCH,
PIPE_A_FIFO_UNDERRUN,
PIPE_B_FIFO_UNDERRUN,
PIPE_A_CRC_ERR,
PIPE_B_CRC_ERR,
PIPE_A_CRC_DONE,
PIPE_B_CRC_DONE,
PIPE_A_ODD_FIELD,
PIPE_B_ODD_FIELD,
PIPE_A_EVEN_FIELD,
PIPE_B_EVEN_FIELD,
PIPE_A_LINE_COMPARE,
PIPE_B_LINE_COMPARE,
PIPE_C_LINE_COMPARE,
PIPE_A_VBLANK,
PIPE_B_VBLANK,
PIPE_C_VBLANK,
PIPE_A_VSYNC,
PIPE_B_VSYNC,
PIPE_C_VSYNC,
PRIMARY_A_FLIP_DONE,
PRIMARY_B_FLIP_DONE,
PRIMARY_C_FLIP_DONE,
SPRITE_A_FLIP_DONE,
SPRITE_B_FLIP_DONE,
SPRITE_C_FLIP_DONE,
PCU_THERMAL,
PCU_PCODE2DRIVER_MAILBOX,
DPST_PHASE_IN,
DPST_HISTOGRAM,
GSE,
DP_A_HOTPLUG,
AUX_CHANNEL_A,
PERF_COUNTER,
POISON,
GTT_FAULT,
ERROR_INTERRUPT_COMBINED,
FDI_RX_INTERRUPTS_TRANSCODER_A,
AUDIO_CP_CHANGE_TRANSCODER_A,
AUDIO_CP_REQUEST_TRANSCODER_A,
FDI_RX_INTERRUPTS_TRANSCODER_B,
AUDIO_CP_CHANGE_TRANSCODER_B,
AUDIO_CP_REQUEST_TRANSCODER_B,
FDI_RX_INTERRUPTS_TRANSCODER_C,
AUDIO_CP_CHANGE_TRANSCODER_C,
AUDIO_CP_REQUEST_TRANSCODER_C,
ERR_AND_DBG,
GMBUS,
SDVO_B_HOTPLUG,
CRT_HOTPLUG,
DP_B_HOTPLUG,
DP_C_HOTPLUG,
DP_D_HOTPLUG,
AUX_CHANNEL_B,
AUX_CHANNEL_C,
AUX_CHANNEL_D,
AUDIO_POWER_STATE_CHANGE_B,
AUDIO_POWER_STATE_CHANGE_C,
AUDIO_POWER_STATE_CHANGE_D,
INTEL_GVT_EVENT_RESERVED,
INTEL_GVT_EVENT_MAX,
};
struct intel_gvt_irq;
struct intel_gvt;
typedef void (*gvt_event_virt_handler_t)(struct intel_gvt_irq *irq,
enum intel_gvt_event_type event, struct intel_vgpu *vgpu);
struct intel_gvt_irq_ops {
void (*init_irq)(struct intel_gvt_irq *irq);
void (*check_pending_irq)(struct intel_vgpu *vgpu);
};
/* the list of physical interrupt control register groups */
enum intel_gvt_irq_type {
INTEL_GVT_IRQ_INFO_GT,
INTEL_GVT_IRQ_INFO_DPY,
INTEL_GVT_IRQ_INFO_PCH,
INTEL_GVT_IRQ_INFO_PM,
INTEL_GVT_IRQ_INFO_MASTER,
INTEL_GVT_IRQ_INFO_GT0,
INTEL_GVT_IRQ_INFO_GT1,
INTEL_GVT_IRQ_INFO_GT2,
INTEL_GVT_IRQ_INFO_GT3,
INTEL_GVT_IRQ_INFO_DE_PIPE_A,
INTEL_GVT_IRQ_INFO_DE_PIPE_B,
INTEL_GVT_IRQ_INFO_DE_PIPE_C,
INTEL_GVT_IRQ_INFO_DE_PORT,
INTEL_GVT_IRQ_INFO_DE_MISC,
INTEL_GVT_IRQ_INFO_AUD,
INTEL_GVT_IRQ_INFO_PCU,
INTEL_GVT_IRQ_INFO_MAX,
};
#define INTEL_GVT_IRQ_BITWIDTH 32
/* device specific interrupt bit definitions */
struct intel_gvt_irq_info {
char *name;
i915_reg_t reg_base;
enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH];
unsigned long warned;
int group;
DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH);
bool has_upstream_irq;
};
/* per-event information */
struct intel_gvt_event_info {
int bit; /* map to register bit */
int policy; /* forwarding policy */
struct intel_gvt_irq_info *info; /* register info */
gvt_event_virt_handler_t v_handler; /* for v_event */
};
struct intel_gvt_irq_map {
int up_irq_group;
int up_irq_bit;
int down_irq_group;
u32 down_irq_bitmask;
};
/* structure containing device specific IRQ state */
struct intel_gvt_irq {
struct intel_gvt_irq_ops *ops;
struct intel_gvt_irq_info *info[INTEL_GVT_IRQ_INFO_MAX];
DECLARE_BITMAP(irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX);
struct intel_gvt_event_info events[INTEL_GVT_EVENT_MAX];
DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
struct intel_gvt_irq_map *irq_map;
};
int intel_gvt_init_irq(struct intel_gvt *gvt);
void intel_gvt_clean_irq(struct intel_gvt *gvt);
void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
enum intel_gvt_event_type event);
int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
void *p_data, unsigned int bytes);
int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
unsigned int reg, void *p_data, unsigned int bytes);
int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
unsigned int reg, void *p_data, unsigned int bytes);
int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
unsigned int reg, void *p_data, unsigned int bytes);
#endif /* _GVT_INTERRUPT_H_ */
......@@ -79,4 +79,42 @@ static inline void intel_gvt_hypervisor_detach_vgpu(struct intel_vgpu *vgpu)
intel_gvt_host.mpt->detach_vgpu(vgpu->handle);
}
#define MSI_CAP_CONTROL(offset) (offset + 2)
#define MSI_CAP_ADDRESS(offset) (offset + 4)
#define MSI_CAP_DATA(offset) (offset + 8)
#define MSI_CAP_EN 0x1
/**
* intel_gvt_hypervisor_inject_msi - inject a MSI interrupt into vGPU
*
* Returns:
* Zero on success, negative error code if failed.
*/
static inline int intel_gvt_hypervisor_inject_msi(struct intel_vgpu *vgpu)
{
unsigned long offset = vgpu->gvt->device_info.msi_cap_offset;
u16 control, data;
u32 addr;
int ret;
control = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_CONTROL(offset));
addr = *(u32 *)(vgpu_cfg_space(vgpu) + MSI_CAP_ADDRESS(offset));
data = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_DATA(offset));
/* Do not generate MSI if MSIEN is disable */
if (!(control & MSI_CAP_EN))
return 0;
if (WARN(control & GENMASK(15, 1), "only support one MSI format\n"))
return -EINVAL;
gvt_dbg_irq("vgpu%d: inject msi address %x data%x\n", vgpu->id, addr,
data);
ret = intel_gvt_host.mpt->inject_msi(vgpu->handle, addr, data);
if (ret)
return ret;
return 0;
}
#endif /* _GVT_MPT_H_ */
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