Commit dc2a2481 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'powerpc-4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull more powerpc updates from Michael Ellerman:
 "The change to the Linux page table geometry was delayed for more
  testing with 16G pages, and there's the new CPU features stuff which
  just needed one more polish before going in. Plus a few changes from
  Scott which came in a bit late. And then various fixes, mostly minor.

  Summary highlights:

   - rework the Linux page table geometry to lower memory usage on
     64-bit Book3S (IBM chips) using the Hash MMU.

   - support for a new device tree binding for discovering CPU features
     on future firmwares.

   - Freescale updates from Scott:
      "Includes a fix for a powerpc/next mm regression on 64e, a fix for
       a kernel hang on 64e when using a debugger inside a relocated
       kernel, a qman fix, and misc qe improvements."

  Thanks to: Christophe Leroy, Gavin Shan, Horia Geantă, LiuHailong,
  Nicholas Piggin, Roy Pledge, Scott Wood, Valentin Longchamp"

* tag 'powerpc-4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
  powerpc/64s: Support new device tree binding for discovering CPU features
  powerpc: Don't print cpu_spec->cpu_name if it's NULL
  of/fdt: introduce of_scan_flat_dt_subnodes and of_get_flat_dt_phandle
  powerpc/64s: Fix unnecessary machine check handler relocation branch
  powerpc/mm/book3s/64: Rework page table geometry for lower memory usage
  powerpc: Fix distclean with Makefile.postlink
  powerpc/64e: Don't place the stack beyond TASK_SIZE
  powerpc/powernv: Block PCI config access on BCM5718 during EEH recovery
  powerpc/8xx: Adding support of IRQ in MPC8xx GPIO
  soc/fsl/qbman: Disable IRQs for deferred QBMan work
  soc/fsl/qe: add EXPORT_SYMBOL for the 2 qe_tdm functions
  soc/fsl/qe: only apply QE_General4 workaround on affected SoCs
  soc/fsl/qe: round brg_freq to 1kHz granularity
  soc/fsl/qe: get rid of immrbar_virt_to_phys()
  net: ethernet: ucc_geth: fix MEM_PART_MURAM mode
  powerpc/64e: Fix hang when debugging programs with relocated kernel
parents ac3c4aa2 5a61ef74
*** NOTE ***
This document is copied from OPAL firmware
(skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
There is more complete overview and documentation of features in that
source tree. All patches and modifications should go there.
************
ibm,powerpc-cpu-features binding
================================
This device tree binding describes CPU features available to software, with
enablement, privilege, and compatibility metadata.
More general description of design and implementation of this binding is
found in design.txt, which also points to documentation of specific features.
/cpus/ibm,powerpc-cpu-features node binding
-------------------------------------------
Node: ibm,powerpc-cpu-features
Description: Container of CPU feature nodes.
The node name must be "ibm,powerpc-cpu-features".
It is implemented as a child of the node "/cpus", but this must not be
assumed by parsers.
The node is optional but should be provided by new OPAL firmware.
Properties:
- compatible
Usage: required
Value type: string
Definition: "ibm,powerpc-cpu-features"
This compatibility refers to backwards compatibility of the overall
design with parsers that behave according to these guidelines. This can
be extended in a backward compatible manner which would not warrant a
revision of the compatible property.
- isa
Usage: required
Value type: <u32>
Definition:
isa that the CPU is currently running in. This provides instruction set
compatibility, less the individual feature nodes. For example, an ISA v3.0
implementation that lacks the "transactional-memory" cpufeature node
should not use transactional memory facilities.
Value corresponds to the "Power ISA Version" multiplied by 1000.
For example, <3000> corresponds to Version 3.0, <2070> to Version 2.07.
The minor digit is available for revisions.
- display-name
Usage: optional
Value type: string
Definition:
A human readable name for the CPU.
/cpus/ibm,powerpc-cpu-features/example-feature node bindings
----------------------------------------------------------------
Each child node of cpu-features represents a CPU feature / capability.
Node: A string describing an architected CPU feature, e.g., "floating-point".
Description: A feature or capability supported by the CPUs.
The name of the node is a human readable string that forms the interface
used to describe features to software. Features are currently documented
in the code where they are implemented in skiboot/core/cpufeatures.c
Presence of the node indicates the feature is available.
Properties:
- isa
Usage: required
Value type: <u32>
Definition:
First level of the Power ISA that the feature appears in.
Software should filter out features when constraining the
environment to a particular ISA version.
Value is defined similarly to /cpus/features/isa
- usable-privilege
Usage: required
Value type: <u32> bit mask
Definition:
Bit numbers are LSB0
bit 0 - PR (problem state / user mode)
bit 1 - OS (privileged state)
bit 2 - HV (hypervisor state)
All other bits reserved and should be zero.
This property describes the privilege levels and/or software components
that can use the feature.
If bit 0 is set, then the hwcap-bit-nr property will exist.
- hv-support
Usage: optional
Value type: <u32> bit mask
Definition:
Bit numbers are LSB0
bit 0 - HFSCR
All other bits reserved and should be zero.
This property describes the HV privilege support required to enable the
feature to lesser privilege levels. If the property does not exist then no
support is required.
If no bits are set, the hypervisor must have explicit/custom support for
this feature.
If the HFSCR bit is set, then the hfscr-bit-nr property will exist and
the feature may be enabled by setting this bit in the HFSCR register.
- os-support
Usage: optional
Value type: <u32> bit mask
Definition:
Bit numbers are LSB0
bit 0 - FSCR
All other bits reserved and should be zero.
This property describes the OS privilege support required to enable the
feature to lesser privilege levels. If the property does not exist then no
support is required.
If no bits are set, the operating system must have explicit/custom support
for this feature.
If the FSCR bit is set, then the fscr-bit-nr property will exist and
the feature may be enabled by setting this bit in the FSCR register.
- hfscr-bit-nr
Usage: optional
Value type: <u32>
Definition: HFSCR bit position (LSB0)
This property exists when the hv-support property HFSCR bit is set. This
property describes the bit number in the HFSCR register that the
hypervisor must set in order to enable this feature.
This property also exists if an HFSCR bit corresponds with this feature.
This makes CPU feature parsing slightly simpler.
- fscr-bit-nr
Usage: optional
Value type: <u32>
Definition: FSCR bit position (LSB0)
This property exists when the os-support property FSCR bit is set. This
property describes the bit number in the FSCR register that the
operating system must set in order to enable this feature.
This property also exists if an FSCR bit corresponds with this feature.
This makes CPU feature parsing slightly simpler.
- hwcap-bit-nr
Usage: optional
Value type: <u32>
Definition: Linux ELF AUX vector bit position (LSB0)
This property may exist when the usable-privilege property value has PR bit set.
This property describes the bit number that should be set in the ELF AUX
hardware capability vectors in order to advertise this feature to userspace.
Bits 0-31 correspond to bits 0-31 in AT_HWCAP vector. Bits 32-63 correspond
to 0-31 in AT_HWCAP2 vector, and so on. Missing AT_HWCAPx vectors implies
that the feature is not enabled or can not be advertised. Operating systems
may provide a number of unassigned hardware capability bits to allow for new
features to be advertised.
Some properties representing features created before this binding are
advertised to userspace without a one-to-one hwcap bit number may not specify
this bit. Operating system will handle those bits specifically. All new
features usable by userspace will have a hwcap-bit-nr property.
- dependencies
Usage: optional
Value type: <prop-encoded-array>
Definition:
If this property exists then it is a list of phandles to cpu feature
nodes that must be enabled for this feature to be enabled.
Example
-------
/cpus/ibm,powerpc-cpu-features {
compatible = "ibm,powerpc-cpu-features";
isa = <3020>;
darn {
isa = <3000>;
usable-privilege = <1 | 2 | 4>;
hwcap-bit-nr = <xx>;
};
scv {
isa = <3000>;
usable-privilege = <1 | 2>;
os-support = <0>;
hwcap-bit-nr = <xx>;
};
stop {
isa = <3000>;
usable-privilege = <2 | 4>;
hv-support = <0>;
os-support = <0>;
};
vsx2 (hypothetical) {
isa = <3010>;
usable-privilege = <1 | 2 | 4>;
hv-support = <0>;
os-support = <0>;
hwcap-bit-nr = <xx>;
};
vsx2-newinsns {
isa = <3020>;
usable-privilege = <1 | 2 | 4>;
os-support = <1>;
fscr-bit-nr = <xx>;
hwcap-bit-nr = <xx>;
dependencies = <&vsx2>;
};
};
......@@ -13,8 +13,17 @@ Required properties:
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters (currently unused).
- gpio-controller : Marks the port as GPIO controller.
Optional properties:
- fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
on CPM1), this item tells which ports have an associated interrupt (ports are
listed in the same order as in PCINT register)
- interrupts : This property provides the list of interrupt for each GPIO having
one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
many interrupts as number of ones in the mask property. The first interrupt in
the list corresponds to the most significant bit of the mask.
- interrupt-parent : Parent for the above interrupt property.
Example of three SOC GPIO banks defined as gpio-controller nodes:
Example of four SOC GPIO banks defined as gpio-controller nodes:
CPM1_PIO_A: gpio-controller@950 {
#gpio-cells = <2>;
......@@ -30,6 +39,16 @@ Example of three SOC GPIO banks defined as gpio-controller nodes:
gpio-controller;
};
CPM1_PIO_C: gpio-controller@960 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-c";
reg = <0x960 0x10>;
fsl,cpm1-gpio-irq-mask = <0x0fff>;
interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>;
interrupt-parent = <&CPM_PIC>;
gpio-controller;
};
CPM1_PIO_E: gpio-controller@ac8 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-e";
......
......@@ -380,6 +380,22 @@ source "arch/powerpc/platforms/Kconfig"
menu "Kernel options"
config PPC_DT_CPU_FTRS
bool "Device-tree based CPU feature discovery & setup"
depends on PPC_BOOK3S_64
default n
help
This enables code to use a new device tree binding for describing CPU
compatibility and features. Saying Y here will attempt to use the new
binding if the firmware provides it. Currently only the skiboot
firmware provides this binding.
If you're not sure say Y.
config PPC_CPUFEATURES_ENABLE_UNKNOWN
bool "cpufeatures pass through unknown features to guest/userspace"
depends on PPC_DT_CPU_FTRS
default y
config HIGHMEM
bool "High memory support"
depends on PPC32
......
......@@ -7,7 +7,7 @@
PHONY := __archpost
__archpost:
include include/config/auto.conf
-include include/config/auto.conf
include scripts/Kbuild.include
quiet_cmd_relocs_check = CHKREL $@
......
......@@ -2,9 +2,9 @@
#define _ASM_POWERPC_BOOK3S_64_HASH_64K_H
#define H_PTE_INDEX_SIZE 8
#define H_PMD_INDEX_SIZE 5
#define H_PUD_INDEX_SIZE 5
#define H_PGD_INDEX_SIZE 15
#define H_PMD_INDEX_SIZE 10
#define H_PUD_INDEX_SIZE 7
#define H_PGD_INDEX_SIZE 8
/*
* 64k aligned address free up few of the lower bits of RPN for us
......
......@@ -560,6 +560,8 @@ typedef struct risc_timer_pram {
#define CPM_PIN_SECONDARY 2
#define CPM_PIN_GPIO 4
#define CPM_PIN_OPENDRAIN 8
#define CPM_PIN_FALLEDGE 16
#define CPM_PIN_ANYEDGE 0
enum cpm_port {
CPM_PORTA,
......
#ifndef __ASM_POWERPC_CPUFEATURES_H
#define __ASM_POWERPC_CPUFEATURES_H
#ifndef __ASM_POWERPC_CPU_HAS_FEATURE_H
#define __ASM_POWERPC_CPU_HAS_FEATURE_H
#ifndef __ASSEMBLY__
......@@ -52,4 +52,4 @@ static inline bool cpu_has_feature(unsigned long feature)
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ASM_POWERPC_CPUFEATURE_H */
#endif /* __ASM_POWERPC_CPU_HAS_FEATURE_H */
......@@ -118,7 +118,9 @@ extern struct cpu_spec *cur_cpu_spec;
extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
extern void set_cur_cpu_spec(struct cpu_spec *s);
extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
extern void identify_cpu_name(unsigned int pvr);
extern void do_feature_fixups(unsigned long value, void *fixup_start,
void *fixup_end);
......
#ifndef __ASM_POWERPC_DT_CPU_FTRS_H
#define __ASM_POWERPC_DT_CPU_FTRS_H
/*
* Copyright 2017, IBM Corporation
* cpufeatures is the new way to discover CPU features with /cpus/features
* devicetree. This supersedes PVR based discovery ("cputable"), and older
* device tree feature advertisement.
*/
#include <linux/types.h>
#include <asm/asm-compat.h>
#include <asm/feature-fixups.h>
#include <uapi/asm/cputable.h>
#ifdef CONFIG_PPC_DT_CPU_FTRS
bool dt_cpu_ftrs_init(void *fdt);
void dt_cpu_ftrs_scan(void);
bool dt_cpu_ftrs_in_use(void);
#else
static inline bool dt_cpu_ftrs_init(void *fdt) { return false; }
static inline void dt_cpu_ftrs_scan(void) { }
static inline bool dt_cpu_ftrs_in_use(void) { return false; }
#endif
#endif /* __ASM_POWERPC_DT_CPU_FTRS_H */
......@@ -151,8 +151,13 @@ void release_thread(struct task_struct *);
#ifdef __powerpc64__
#ifdef CONFIG_PPC_BOOK3S_64
/* Limit stack to 128TB */
#define STACK_TOP_USER64 TASK_SIZE_128TB
#else
#define STACK_TOP_USER64 TASK_SIZE_USER64
#endif
#define STACK_TOP_USER32 TASK_SIZE_USER32
#define STACK_TOP (is_32bit_task() ? \
......
......@@ -1229,6 +1229,7 @@
#define PVR_POWER8E 0x004B
#define PVR_POWER8NVL 0x004C
#define PVR_POWER8 0x004D
#define PVR_POWER9 0x004E
#define PVR_BE 0x0070
#define PVR_PA6T 0x0090
......
......@@ -47,4 +47,11 @@
#define PPC_FEATURE2_ARCH_3_00 0x00800000 /* ISA 3.00 */
#define PPC_FEATURE2_HAS_IEEE128 0x00400000 /* VSX IEEE Binary Float 128-bit */
/*
* IMPORTANT!
* All future PPC_FEATURE definitions should be allocated in cooperation with
* OPAL / skiboot firmware, in accordance with the ibm,powerpc-cpu-features
* device tree binding.
*/
#endif /* _UAPI__ASM_POWERPC_CPUTABLE_H */
......@@ -56,6 +56,7 @@ obj-$(CONFIG_PPC_RTAS) += rtas.o rtas-rtc.o $(rtaspci-y-y)
obj-$(CONFIG_PPC_RTAS_DAEMON) += rtasd.o
obj-$(CONFIG_RTAS_FLASH) += rtas_flash.o
obj-$(CONFIG_RTAS_PROC) += rtas-proc.o
obj-$(CONFIG_PPC_DT_CPU_FTRS) += dt_cpu_ftrs.o
obj-$(CONFIG_EEH) += eeh.o eeh_pe.o eeh_dev.o eeh_cache.o \
eeh_driver.o eeh_event.o eeh_sysfs.o
obj-$(CONFIG_GENERIC_TBSYNC) += smp-tbsync.o
......
......@@ -23,7 +23,9 @@
#include <asm/mmu.h>
#include <asm/setup.h>
struct cpu_spec* cur_cpu_spec = NULL;
static struct cpu_spec the_cpu_spec __read_mostly;
struct cpu_spec* cur_cpu_spec __read_mostly = NULL;
EXPORT_SYMBOL(cur_cpu_spec);
/* The platform string corresponding to the real PVR */
......@@ -2179,7 +2181,15 @@ static struct cpu_spec __initdata cpu_specs[] = {
#endif /* CONFIG_E500 */
};
static struct cpu_spec the_cpu_spec;
void __init set_cur_cpu_spec(struct cpu_spec *s)
{
struct cpu_spec *t = &the_cpu_spec;
t = PTRRELOC(t);
*t = *s;
*PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
}
static struct cpu_spec * __init setup_cpu_spec(unsigned long offset,
struct cpu_spec *s)
......@@ -2266,6 +2276,29 @@ struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
return NULL;
}
/*
* Used by cpufeatures to get the name for CPUs with a PVR table.
* If they don't hae a PVR table, cpufeatures gets the name from
* cpu device-tree node.
*/
void __init identify_cpu_name(unsigned int pvr)
{
struct cpu_spec *s = cpu_specs;
struct cpu_spec *t = &the_cpu_spec;
int i;
s = PTRRELOC(s);
t = PTRRELOC(t);
for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
if ((pvr & s->pvr_mask) == s->pvr_value) {
t->cpu_name = s->cpu_name;
return;
}
}
}
#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
struct static_key_true cpu_feature_keys[NUM_CPU_FTR_KEYS] = {
[0 ... NUM_CPU_FTR_KEYS - 1] = STATIC_KEY_TRUE_INIT
......
This diff is collapsed.
......@@ -735,8 +735,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
andis. r15,r14,(DBSR_IC|DBSR_BT)@h
beq+ 1f
#ifdef CONFIG_RELOCATABLE
ld r15,PACATOC(r13)
ld r14,interrupt_base_book3e@got(r15)
ld r15,__end_interrupts@got(r15)
#else
LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
LOAD_REG_IMMEDIATE(r15,__end_interrupts)
#endif
cmpld cr0,r10,r14
cmpld cr1,r10,r15
blt+ cr0,1f
......@@ -799,8 +805,14 @@ kernel_dbg_exc:
andis. r15,r14,(DBSR_IC|DBSR_BT)@h
beq+ 1f
#ifdef CONFIG_RELOCATABLE
ld r15,PACATOC(r13)
ld r14,interrupt_base_book3e@got(r15)
ld r15,__end_interrupts@got(r15)
#else
LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
LOAD_REG_IMMEDIATE(r15,__end_interrupts)
#endif
cmpld cr0,r10,r14
cmpld cr1,r10,r15
blt+ cr0,1f
......
......@@ -391,9 +391,7 @@ EXC_COMMON_BEGIN(machine_check_handle_early)
*/
BEGIN_FTR_SECTION
rlwinm. r11,r12,47-31,30,31
beq- 4f
BRANCH_TO_COMMON(r10, machine_check_idle_common)
4:
bne machine_check_idle_common
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
#endif
......
......@@ -57,6 +57,7 @@
#include <asm/fadump.h>
#include <asm/epapr_hcalls.h>
#include <asm/firmware.h>
#include <asm/dt_cpu_ftrs.h>
#include <mm/mmu_decl.h>
......@@ -375,23 +376,31 @@ static int __init early_init_dt_scan_cpus(unsigned long node,
* A POWER6 partition in "POWER6 architected" mode
* uses the 0x0f000002 PVR value; in POWER5+ mode
* it uses 0x0f000001.
*
* If we're using device tree CPU feature discovery then we don't
* support the cpu-version property, and it's the responsibility of the
* firmware/hypervisor to provide the correct feature set for the
* architecture level via the ibm,powerpc-cpu-features binding.
*/
prop = of_get_flat_dt_prop(node, "cpu-version", NULL);
if (prop && (be32_to_cpup(prop) & 0xff000000) == 0x0f000000)
identify_cpu(0, be32_to_cpup(prop));
if (!dt_cpu_ftrs_in_use()) {
prop = of_get_flat_dt_prop(node, "cpu-version", NULL);
if (prop && (be32_to_cpup(prop) & 0xff000000) == 0x0f000000)
identify_cpu(0, be32_to_cpup(prop));
identical_pvr_fixup(node);
check_cpu_feature_properties(node);
check_cpu_pa_features(node);
}
check_cpu_feature_properties(node);
check_cpu_pa_features(node);
identical_pvr_fixup(node);
init_mmu_slb_size(node);
#ifdef CONFIG_PPC64
if (nthreads > 1)
cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
else
if (nthreads == 1)
cur_cpu_spec->cpu_features &= ~CPU_FTR_SMT;
else if (!dt_cpu_ftrs_in_use())
cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
#endif
return 0;
}
......@@ -721,6 +730,8 @@ void __init early_init_devtree(void *params)
DBG("Scanning CPUs ...\n");
dt_cpu_ftrs_scan();
/* Retrieve CPU related informations from the flat tree
* (altivec support, boot CPU ID, ...)
*/
......
......@@ -261,7 +261,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "processor\t: %lu\n", cpu_id);
seq_printf(m, "cpu\t\t: ");
if (cur_cpu_spec->pvr_mask)
if (cur_cpu_spec->pvr_mask && cur_cpu_spec->cpu_name)
seq_printf(m, "%s", cur_cpu_spec->cpu_name);
else
seq_printf(m, "unknown (%08x)", pvr);
......
......@@ -49,6 +49,7 @@
#include <asm/paca.h>
#include <asm/time.h>
#include <asm/cputable.h>
#include <asm/dt_cpu_ftrs.h>
#include <asm/sections.h>
#include <asm/btext.h>
#include <asm/nvram.h>
......@@ -274,8 +275,10 @@ void __init early_setup(unsigned long dt_ptr)
/* -------- printk is _NOT_ safe to use here ! ------- */
/* Identify CPU type */
identify_cpu(0, mfspr(SPRN_PVR));
/* Try new device tree based feature discovery ... */
if (!dt_cpu_ftrs_init(__va(dt_ptr)))
/* Otherwise use the old style CPU table */
identify_cpu(0, mfspr(SPRN_PVR));
/* Assume we're on cpu 0 for now. Don't write to the paca yet! */
initialise_paca(&boot_paca, 0);
......@@ -541,6 +544,9 @@ void __init initialize_cache_info(void)
dcache_bsize = ppc64_caches.l1d.block_size;
icache_bsize = ppc64_caches.l1i.block_size;
cur_cpu_spec->dcache_bsize = dcache_bsize;
cur_cpu_spec->icache_bsize = icache_bsize;
DBG(" <- initialize_cache_info()\n");
}
......
......@@ -412,11 +412,14 @@ static void *pnv_eeh_probe(struct pci_dn *pdn, void *data)
* been set for the PE, we will set EEH_PE_CFG_BLOCKED for
* that PE to block its config space.
*
* Broadcom BCM5718 2-ports NICs (14e4:1656)
* Broadcom Austin 4-ports NICs (14e4:1657)