Commit efdffb75 authored by Gilles Chanteperdrix's avatar Gilles Chanteperdrix Committed by Philippe Gerum

drivers/dove: pmu: ipipe: enable interrupt pipelining

Fix up the PMU controller driver of the Marvell Dove SoC in order to
channel interrupts through the interrupt pipeline.
parent 7f22e17b
...@@ -231,6 +231,7 @@ static void pmu_irq_handler(struct irq_desc *desc) ...@@ -231,6 +231,7 @@ static void pmu_irq_handler(struct irq_desc *desc)
void __iomem *base = gc->reg_base; void __iomem *base = gc->reg_base;
u32 stat = readl_relaxed(base + PMC_IRQ_CAUSE) & gc->mask_cache; u32 stat = readl_relaxed(base + PMC_IRQ_CAUSE) & gc->mask_cache;
u32 done = ~0; u32 done = ~0;
unsigned long flags;
if (stat == 0) { if (stat == 0) {
handle_bad_irq(desc); handle_bad_irq(desc);
...@@ -243,7 +244,7 @@ static void pmu_irq_handler(struct irq_desc *desc) ...@@ -243,7 +244,7 @@ static void pmu_irq_handler(struct irq_desc *desc)
stat &= ~(1 << hwirq); stat &= ~(1 << hwirq);
done &= ~(1 << hwirq); done &= ~(1 << hwirq);
generic_handle_irq(irq_find_mapping(domain, hwirq)); ipipe_handle_demuxed_irq(irq_find_mapping(domain, hwirq));
} }
/* /*
...@@ -257,10 +258,10 @@ static void pmu_irq_handler(struct irq_desc *desc) ...@@ -257,10 +258,10 @@ static void pmu_irq_handler(struct irq_desc *desc)
* So, let's structure the code so that the window is as small as * So, let's structure the code so that the window is as small as
* possible. * possible.
*/ */
irq_gc_lock(gc); flags = irq_gc_lock(gc);
done &= readl_relaxed(base + PMC_IRQ_CAUSE); done &= readl_relaxed(base + PMC_IRQ_CAUSE);
writel_relaxed(done, base + PMC_IRQ_CAUSE); writel_relaxed(done, base + PMC_IRQ_CAUSE);
irq_gc_unlock(gc); irq_gc_unlock(gc, flags);
} }
static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq) static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq)
...@@ -296,6 +297,7 @@ static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq) ...@@ -296,6 +297,7 @@ static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq)
gc->chip_types[0].regs.mask = PMC_IRQ_MASK; gc->chip_types[0].regs.mask = PMC_IRQ_MASK;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
gc->chip_types[0].chip.flags |= IRQCHIP_PIPELINE_SAFE;
pmu->irq_domain = domain; pmu->irq_domain = domain;
pmu->irq_gc = gc; pmu->irq_gc = gc;
......
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