mma8452.c 43.9 KB
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/*
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 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
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 *
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 * device name	digital output	7-bit I2C slave address (pin selectable)
 * ---------------------------------------------------------------------
 * MMA8451Q	14 bit		0x1c / 0x1d
 * MMA8452Q	12 bit		0x1c / 0x1d
 * MMA8453Q	10 bit		0x1c / 0x1d
 * MMA8652FC	12 bit		0x1d
 * MMA8653FC	10 bit		0x1d
 * FXLS8471Q	14 bit		0x1e / 0x1d / 0x1c / 0x1f
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 *
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 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
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 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
 *
 * This file is subject to the terms and conditions of version 2 of
 * the GNU General Public License.  See the file COPYING in the main
 * directory of this archive for more details.
 *
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 * TODO: orientation events
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 */

#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
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#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/events.h>
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#include <linux/delay.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pm_runtime.h>
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#define MMA8452_STATUS				0x00
#define  MMA8452_STATUS_DRDY			(BIT(2) | BIT(1) | BIT(0))
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#define MMA8452_OUT_X				0x01 /* MSB first */
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#define MMA8452_OUT_Y				0x03
#define MMA8452_OUT_Z				0x05
#define MMA8452_INT_SRC				0x0c
#define MMA8452_WHO_AM_I			0x0d
#define MMA8452_DATA_CFG			0x0e
#define  MMA8452_DATA_CFG_FS_MASK		GENMASK(1, 0)
#define  MMA8452_DATA_CFG_FS_2G			0
#define  MMA8452_DATA_CFG_FS_4G			1
#define  MMA8452_DATA_CFG_FS_8G			2
#define  MMA8452_DATA_CFG_HPF_MASK		BIT(4)
#define MMA8452_HP_FILTER_CUTOFF		0x0f
#define  MMA8452_HP_FILTER_CUTOFF_SEL_MASK	GENMASK(1, 0)
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#define MMA8452_FF_MT_CFG			0x15
#define  MMA8452_FF_MT_CFG_OAE			BIT(6)
#define  MMA8452_FF_MT_CFG_ELE			BIT(7)
#define MMA8452_FF_MT_SRC			0x16
#define  MMA8452_FF_MT_SRC_XHE			BIT(1)
#define  MMA8452_FF_MT_SRC_YHE			BIT(3)
#define  MMA8452_FF_MT_SRC_ZHE			BIT(5)
#define MMA8452_FF_MT_THS			0x17
#define  MMA8452_FF_MT_THS_MASK			0x7f
#define MMA8452_FF_MT_COUNT			0x18
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#define MMA8452_TRANSIENT_CFG			0x1d
#define  MMA8452_TRANSIENT_CFG_HPF_BYP		BIT(0)
#define  MMA8452_TRANSIENT_CFG_ELE		BIT(4)
#define MMA8452_TRANSIENT_SRC			0x1e
#define  MMA8452_TRANSIENT_SRC_XTRANSE		BIT(1)
#define  MMA8452_TRANSIENT_SRC_YTRANSE		BIT(3)
#define  MMA8452_TRANSIENT_SRC_ZTRANSE		BIT(5)
#define MMA8452_TRANSIENT_THS			0x1f
#define  MMA8452_TRANSIENT_THS_MASK		GENMASK(6, 0)
#define MMA8452_TRANSIENT_COUNT			0x20
#define MMA8452_CTRL_REG1			0x2a
#define  MMA8452_CTRL_ACTIVE			BIT(0)
#define  MMA8452_CTRL_DR_MASK			GENMASK(5, 3)
#define  MMA8452_CTRL_DR_SHIFT			3
#define  MMA8452_CTRL_DR_DEFAULT		0x4 /* 50 Hz sample frequency */
#define MMA8452_CTRL_REG2			0x2b
#define  MMA8452_CTRL_REG2_RST			BIT(6)
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#define  MMA8452_CTRL_REG2_MODS_SHIFT		3
#define  MMA8452_CTRL_REG2_MODS_MASK		0x1b
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#define MMA8452_CTRL_REG4			0x2d
#define MMA8452_CTRL_REG5			0x2e
#define MMA8452_OFF_X				0x2f
#define MMA8452_OFF_Y				0x30
#define MMA8452_OFF_Z				0x31
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#define MMA8452_MAX_REG				0x31
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#define  MMA8452_INT_DRDY			BIT(0)
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#define  MMA8452_INT_FF_MT			BIT(2)
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#define  MMA8452_INT_TRANS			BIT(5)
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#define MMA8451_DEVICE_ID			0x1a
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#define MMA8452_DEVICE_ID			0x2a
#define MMA8453_DEVICE_ID			0x3a
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#define MMA8652_DEVICE_ID			0x4a
#define MMA8653_DEVICE_ID			0x5a
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#define FXLS8471_DEVICE_ID			0x6a
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#define MMA8452_AUTO_SUSPEND_DELAY_MS		2000

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struct mma8452_data {
	struct i2c_client *client;
	struct mutex lock;
	u8 ctrl_reg1;
	u8 data_cfg;
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	const struct mma_chip_info *chip_info;
};

/**
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 * struct mma_chip_info - chip specific data
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 * @chip_id:			WHO_AM_I register's value
 * @channels:			struct iio_chan_spec matching the device's
 *				capabilities
 * @num_channels:		number of channels
 * @mma_scales:			scale factors for converting register values
 *				to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
 *				per mode: m/s^2 and micro m/s^2
 * @ev_cfg:			event config register address
 * @ev_cfg_ele:			latch bit in event config register
 * @ev_cfg_chan_shift:		number of the bit to enable events in X
 *				direction; in event config register
 * @ev_src:			event source register address
 * @ev_src_xe:			bit in event source register that indicates
 *				an event in X direction
 * @ev_src_ye:			bit in event source register that indicates
 *				an event in Y direction
 * @ev_src_ze:			bit in event source register that indicates
 *				an event in Z direction
 * @ev_ths:			event threshold register address
 * @ev_ths_mask:		mask for the threshold value
 * @ev_count:			event count (period) register address
 *
 * Since not all chips supported by the driver support comparing high pass
 * filtered data for events (interrupts), different interrupt sources are
 * used for different chips and the relevant registers are included here.
 */
struct mma_chip_info {
	u8 chip_id;
	const struct iio_chan_spec *channels;
	int num_channels;
	const int mma_scales[3][2];
	u8 ev_cfg;
	u8 ev_cfg_ele;
	u8 ev_cfg_chan_shift;
	u8 ev_src;
	u8 ev_src_xe;
	u8 ev_src_ye;
	u8 ev_src_ze;
	u8 ev_ths;
	u8 ev_ths_mask;
	u8 ev_count;
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};

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enum {
	idx_x,
	idx_y,
	idx_z,
	idx_ts,
};

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static int mma8452_drdy(struct mma8452_data *data)
{
	int tries = 150;

	while (tries-- > 0) {
		int ret = i2c_smbus_read_byte_data(data->client,
			MMA8452_STATUS);
		if (ret < 0)
			return ret;
		if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
			return 0;
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		msleep(20);
	}

	dev_err(&data->client->dev, "data not ready\n");
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	return -EIO;
}

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static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
{
#ifdef CONFIG_PM
	int ret;

	if (on) {
		ret = pm_runtime_get_sync(&client->dev);
	} else {
		pm_runtime_mark_last_busy(&client->dev);
		ret = pm_runtime_put_autosuspend(&client->dev);
	}

	if (ret < 0) {
		dev_err(&client->dev,
			"failed to change power state to %d\n", on);
		if (on)
			pm_runtime_put_noidle(&client->dev);

		return ret;
	}
#endif

	return 0;
}

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static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
{
	int ret = mma8452_drdy(data);
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	if (ret < 0)
		return ret;
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	ret = mma8452_set_runtime_pm_state(data->client, true);
	if (ret)
		return ret;

	ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
					    3 * sizeof(__be16), (u8 *)buf);

	ret = mma8452_set_runtime_pm_state(data->client, false);

	return ret;
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}

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static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
					    int n)
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{
	size_t len = 0;

	while (n-- > 0)
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		len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
				 vals[n][0], vals[n][1]);
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	/* replace trailing space by newline */
	buf[len - 1] = '\n';

	return len;
}

static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
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					     int val, int val2)
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{
	while (n-- > 0)
		if (val == vals[n][0] && val2 == vals[n][1])
			return n;

	return -EINVAL;
}

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static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
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{
	return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
			MMA8452_CTRL_DR_SHIFT;
}

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static const int mma8452_samp_freq[8][2] = {
	{800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
	{6, 250000}, {1, 560000}
};

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/* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
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static const unsigned int mma8452_transient_time_step_us[4][8] = {
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	{ 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 },  /* normal */
	{ 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 },  /* l p l n */
	{ 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 },	  /* high res*/
	{ 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
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};

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/* Datasheet table "High-Pass Filter Cutoff Options" */
static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
	{ /* normal */
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	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} },		/* 800 Hz sample */
	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} },		/* 400 Hz sample */
	{ {8, 0}, {4, 0}, {2, 0}, {1, 0} },		/* 200 Hz sample */
	{ {4, 0}, {2, 0}, {1, 0}, {0, 500000} },	/* 100 Hz sample */
	{ {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },	/* 50 Hz sample */
	{ {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },	/* 12.5 Hz sample */
	{ {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },	/* 6.25 Hz sample */
	{ {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }	/* 1.56 Hz sample */
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	},
	{ /* low noise low power */
	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} },
	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} },
	{ {8, 0}, {4, 0}, {2, 0}, {1, 0} },
	{ {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
	{ {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
	{ {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
	{ {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
	{ {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
	},
	{ /* high resolution */
	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} },
	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} },
	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} },
	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} },
	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} },
	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} },
	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} },
	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} }
	},
	{ /* low power */
	{ {16, 0}, {8, 0}, {4, 0}, {2, 0} },
	{ {8, 0}, {4, 0}, {2, 0}, {1, 0} },
	{ {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
	{ {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
	{ {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
	{ {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
	{ {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
	{ {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
	}
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};

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/* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
static const u16 mma8452_os_ratio[4][8] = {
	/* 800 Hz, 400 Hz, ... , 1.56 Hz */
	{ 2, 4, 4, 4, 4, 16, 32, 128 },		/* normal */
	{ 2, 4, 4, 4, 4, 4, 8, 32 },		/* low power low noise */
	{ 2, 4, 8, 16, 32, 128, 256, 1024 },	/* high resolution */
	{ 2, 2, 2, 2, 2, 2, 4, 16 }		/* low power */
};

static int mma8452_get_power_mode(struct mma8452_data *data)
{
	int reg;

	reg = i2c_smbus_read_byte_data(data->client,
				       MMA8452_CTRL_REG2);
	if (reg < 0)
		return reg;

	return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
		MMA8452_CTRL_REG2_MODS_SHIFT);
}

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static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
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					    struct device_attribute *attr,
					    char *buf)
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{
	return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
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					    ARRAY_SIZE(mma8452_samp_freq));
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}

static ssize_t mma8452_show_scale_avail(struct device *dev,
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					struct device_attribute *attr,
					char *buf)
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{
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	struct mma8452_data *data = iio_priv(i2c_get_clientdata(
					     to_i2c_client(dev)));

	return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
		ARRAY_SIZE(data->chip_info->mma_scales));
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}

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static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
					    struct device_attribute *attr,
					    char *buf)
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{
	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
	struct mma8452_data *data = iio_priv(indio_dev);
	int i, j;

	i = mma8452_get_odr_index(data);
	j = mma8452_get_power_mode(data);
	if (j < 0)
		return j;

	return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
		ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
}

static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
					   struct device_attribute *attr,
					   char *buf)
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{
	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
	struct mma8452_data *data = iio_priv(indio_dev);
	int i = mma8452_get_odr_index(data);
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	int j;
	u16 val = 0;
	size_t len = 0;

	for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
		if (val == mma8452_os_ratio[j][i])
			continue;

		val = mma8452_os_ratio[j][i];

		len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
	}
	buf[len - 1] = '\n';
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	return len;
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}

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static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
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		       mma8452_show_scale_avail, NULL, 0);
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static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
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		       S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
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static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, S_IRUGO,
		       mma8452_show_os_ratio_avail, NULL, 0);
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static int mma8452_get_samp_freq_index(struct mma8452_data *data,
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				       int val, int val2)
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{
	return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
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						 ARRAY_SIZE(mma8452_samp_freq),
						 val, val2);
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}

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static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
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{
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	return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
			ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
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}

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static int mma8452_get_hp_filter_index(struct mma8452_data *data,
				       int val, int val2)
{
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	int i, j;

	i = mma8452_get_odr_index(data);
	j = mma8452_get_power_mode(data);
	if (j < 0)
		return j;
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	return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
		ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
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}

static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
{
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	int j, i, ret;
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	ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
	if (ret < 0)
		return ret;

	i = mma8452_get_odr_index(data);
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	j = mma8452_get_power_mode(data);
	if (j < 0)
		return j;

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	ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
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	*hz = mma8452_hp_filter_cutoff[j][i][ret][0];
	*uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
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	return 0;
}

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static int mma8452_read_raw(struct iio_dev *indio_dev,
			    struct iio_chan_spec const *chan,
			    int *val, int *val2, long mask)
{
	struct mma8452_data *data = iio_priv(indio_dev);
	__be16 buffer[3];
	int i, ret;

	switch (mask) {
	case IIO_CHAN_INFO_RAW:
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		ret = iio_device_claim_direct_mode(indio_dev);
		if (ret)
			return ret;
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		mutex_lock(&data->lock);
		ret = mma8452_read(data, buffer);
		mutex_unlock(&data->lock);
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		iio_device_release_direct_mode(indio_dev);
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		if (ret < 0)
			return ret;
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		*val = sign_extend32(be16_to_cpu(
			buffer[chan->scan_index]) >> chan->scan_type.shift,
			chan->scan_type.realbits - 1);
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		return IIO_VAL_INT;
	case IIO_CHAN_INFO_SCALE:
		i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
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		*val = data->chip_info->mma_scales[i][0];
		*val2 = data->chip_info->mma_scales[i][1];
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		return IIO_VAL_INT_PLUS_MICRO;
	case IIO_CHAN_INFO_SAMP_FREQ:
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		i = mma8452_get_odr_index(data);
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		*val = mma8452_samp_freq[i][0];
		*val2 = mma8452_samp_freq[i][1];
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		return IIO_VAL_INT_PLUS_MICRO;
	case IIO_CHAN_INFO_CALIBBIAS:
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		ret = i2c_smbus_read_byte_data(data->client,
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					       MMA8452_OFF_X +
					       chan->scan_index);
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		if (ret < 0)
			return ret;
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		*val = sign_extend32(ret, 7);
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		return IIO_VAL_INT;
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	case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
		if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
			ret = mma8452_read_hp_filter(data, val, val2);
			if (ret < 0)
				return ret;
		} else {
			*val = 0;
			*val2 = 0;
		}
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		return IIO_VAL_INT_PLUS_MICRO;
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	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
		ret = mma8452_get_power_mode(data);
		if (ret < 0)
			return ret;

		i = mma8452_get_odr_index(data);

		*val = mma8452_os_ratio[ret][i];
		return IIO_VAL_INT;
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	}
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	return -EINVAL;
}

static int mma8452_standby(struct mma8452_data *data)
{
	return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
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					data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
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}

static int mma8452_active(struct mma8452_data *data)
{
	return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
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					 data->ctrl_reg1);
535 536
}

537 538 539 540 541 542 543 544 545 546 547 548
/* returns >0 if active, 0 if in standby and <0 on error */
static int mma8452_is_active(struct mma8452_data *data)
{
	int reg;

	reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
	if (reg < 0)
		return reg;

	return reg & MMA8452_CTRL_ACTIVE;
}

549 550 551
static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
{
	int ret;
552
	int is_active;
553 554 555

	mutex_lock(&data->lock);

556 557 558
	is_active = mma8452_is_active(data);
	if (is_active < 0) {
		ret = is_active;
559
		goto fail;
560 561 562 563 564 565 566 567
	}

	/* config can only be changed when in standby */
	if (is_active > 0) {
		ret = mma8452_standby(data);
		if (ret < 0)
			goto fail;
	}
568 569 570 571 572

	ret = i2c_smbus_write_byte_data(data->client, reg, val);
	if (ret < 0)
		goto fail;

573 574 575 576 577
	if (is_active > 0) {
		ret = mma8452_active(data);
		if (ret < 0)
			goto fail;
	}
578 579 580 581

	ret = 0;
fail:
	mutex_unlock(&data->lock);
582

583 584 585
	return ret;
}

586 587 588 589 590 591 592 593 594 595 596 597 598 599 600
static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
{
	int reg;

	reg = i2c_smbus_read_byte_data(data->client,
				       MMA8452_CTRL_REG2);
	if (reg < 0)
		return reg;

	reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
	reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;

	return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
}

601
/* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638
static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
{
	int val;
	const struct mma_chip_info *chip = data->chip_info;

	val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
	if (val < 0)
		return val;

	return !(val & MMA8452_FF_MT_CFG_OAE);
}

static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
{
	int val;
	const struct mma_chip_info *chip = data->chip_info;

	if ((state && mma8452_freefall_mode_enabled(data)) ||
	    (!state && !(mma8452_freefall_mode_enabled(data))))
		return 0;

	val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
	if (val < 0)
		return val;

	if (state) {
		val |= BIT(idx_x + chip->ev_cfg_chan_shift);
		val |= BIT(idx_y + chip->ev_cfg_chan_shift);
		val |= BIT(idx_z + chip->ev_cfg_chan_shift);
		val &= ~MMA8452_FF_MT_CFG_OAE;
	} else {
		val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
		val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
		val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
		val |= MMA8452_FF_MT_CFG_OAE;
	}

639
	return mma8452_change_config(data, chip->ev_cfg, val);
640 641
}

642 643 644 645 646 647 648
static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
					   int val, int val2)
{
	int i, reg;

	i = mma8452_get_hp_filter_index(data, val, val2);
	if (i < 0)
649
		return i;
650 651 652 653 654

	reg = i2c_smbus_read_byte_data(data->client,
				       MMA8452_HP_FILTER_CUTOFF);
	if (reg < 0)
		return reg;
655

656 657 658 659 660 661
	reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
	reg |= i;

	return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
}

662 663 664 665 666
static int mma8452_write_raw(struct iio_dev *indio_dev,
			     struct iio_chan_spec const *chan,
			     int val, int val2, long mask)
{
	struct mma8452_data *data = iio_priv(indio_dev);
667
	int i, ret;
668

669 670 671
	ret = iio_device_claim_direct_mode(indio_dev);
	if (ret)
		return ret;
672 673 674 675

	switch (mask) {
	case IIO_CHAN_INFO_SAMP_FREQ:
		i = mma8452_get_samp_freq_index(data, val, val2);
676 677 678 679
		if (i < 0) {
			ret = i;
			break;
		}
680 681
		data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
		data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
682

683 684 685
		ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
					    data->ctrl_reg1);
		break;
686 687
	case IIO_CHAN_INFO_SCALE:
		i = mma8452_get_scale_index(data, val, val2);
688 689 690 691
		if (i < 0) {
			ret = i;
			break;
		}
692

693 694
		data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
		data->data_cfg |= i;
695

696 697 698
		ret = mma8452_change_config(data, MMA8452_DATA_CFG,
					    data->data_cfg);
		break;
699
	case IIO_CHAN_INFO_CALIBBIAS:
700 701 702 703
		if (val < -128 || val > 127) {
			ret = -EINVAL;
			break;
		}
704

705 706 707 708
		ret = mma8452_change_config(data,
					    MMA8452_OFF_X + chan->scan_index,
					    val);
		break;
709 710 711 712 713 714 715 716

	case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
		if (val == 0 && val2 == 0) {
			data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
		} else {
			data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
			ret = mma8452_set_hp_filter_frequency(data, val, val2);
			if (ret < 0)
717
				break;
718
		}
719

720
		ret = mma8452_change_config(data, MMA8452_DATA_CFG,
721
					     data->data_cfg);
722
		break;
723

724 725 726 727
	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
		ret = mma8452_get_odr_index(data);

		for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
728 729 730 731
			if (mma8452_os_ratio[i][ret] == val) {
				ret = mma8452_set_power_mode(data, i);
				break;
			}
732
		}
733
		break;
734
	default:
735 736
		ret = -EINVAL;
		break;
737
	}
738 739 740

	iio_device_release_direct_mode(indio_dev);
	return ret;
741 742
}

743 744 745 746 747 748 749 750
static int mma8452_read_thresh(struct iio_dev *indio_dev,
			       const struct iio_chan_spec *chan,
			       enum iio_event_type type,
			       enum iio_event_direction dir,
			       enum iio_event_info info,
			       int *val, int *val2)
{
	struct mma8452_data *data = iio_priv(indio_dev);
751
	int ret, us, power_mode;
752

753 754 755
	switch (info) {
	case IIO_EV_INFO_VALUE:
		ret = i2c_smbus_read_byte_data(data->client,
756
					       data->chip_info->ev_ths);
757 758 759
		if (ret < 0)
			return ret;

760
		*val = ret & data->chip_info->ev_ths_mask;
761

762
		return IIO_VAL_INT;
763

764 765
	case IIO_EV_INFO_PERIOD:
		ret = i2c_smbus_read_byte_data(data->client,
766
					       data->chip_info->ev_count);
767 768 769
		if (ret < 0)
			return ret;

770 771 772 773 774
		power_mode = mma8452_get_power_mode(data);
		if (power_mode < 0)
			return power_mode;

		us = ret * mma8452_transient_time_step_us[power_mode][
775 776 777
				mma8452_get_odr_index(data)];
		*val = us / USEC_PER_SEC;
		*val2 = us % USEC_PER_SEC;
778

779
		return IIO_VAL_INT_PLUS_MICRO;
780

781 782 783 784 785 786 787 788 789 790 791 792 793 794
	case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
		ret = i2c_smbus_read_byte_data(data->client,
					       MMA8452_TRANSIENT_CFG);
		if (ret < 0)
			return ret;

		if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
			*val = 0;
			*val2 = 0;
		} else {
			ret = mma8452_read_hp_filter(data, val, val2);
			if (ret < 0)
				return ret;
		}
795

796 797
		return IIO_VAL_INT_PLUS_MICRO;

798 799 800
	default:
		return -EINVAL;
	}
801 802 803 804 805 806 807 808 809 810
}

static int mma8452_write_thresh(struct iio_dev *indio_dev,
				const struct iio_chan_spec *chan,
				enum iio_event_type type,
				enum iio_event_direction dir,
				enum iio_event_info info,
				int val, int val2)
{
	struct mma8452_data *data = iio_priv(indio_dev);
811
	int ret, reg, steps;
812

813 814
	switch (info) {
	case IIO_EV_INFO_VALUE:
815 816 817
		if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
			return -EINVAL;

818 819
		return mma8452_change_config(data, data->chip_info->ev_ths,
					     val);
820 821

	case IIO_EV_INFO_PERIOD:
822 823 824 825
		ret = mma8452_get_power_mode(data);
		if (ret < 0)
			return ret;

826
		steps = (val * USEC_PER_SEC + val2) /
827
				mma8452_transient_time_step_us[ret][
828 829
					mma8452_get_odr_index(data)];

830
		if (steps < 0 || steps > 0xff)
831 832
			return -EINVAL;

833
		return mma8452_change_config(data, data->chip_info->ev_count,
834
					     steps);
835

836 837 838 839 840 841 842 843 844 845 846 847 848 849
	case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
		reg = i2c_smbus_read_byte_data(data->client,
					       MMA8452_TRANSIENT_CFG);
		if (reg < 0)
			return reg;

		if (val == 0 && val2 == 0) {
			reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
		} else {
			reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
			ret = mma8452_set_hp_filter_frequency(data, val, val2);
			if (ret < 0)
				return ret;
		}
850

851 852
		return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);

853 854 855
	default:
		return -EINVAL;
	}
856 857 858 859 860 861 862 863
}

static int mma8452_read_event_config(struct iio_dev *indio_dev,
				     const struct iio_chan_spec *chan,
				     enum iio_event_type type,
				     enum iio_event_direction dir)
{
	struct mma8452_data *data = iio_priv(indio_dev);
864
	const struct mma_chip_info *chip = data->chip_info;
865 866
	int ret;

867 868 869 870 871 872 873 874 875 876 877
	switch (dir) {
	case IIO_EV_DIR_FALLING:
		return mma8452_freefall_mode_enabled(data);
	case IIO_EV_DIR_RISING:
		if (mma8452_freefall_mode_enabled(data))
			return 0;

		ret = i2c_smbus_read_byte_data(data->client,
					       data->chip_info->ev_cfg);
		if (ret < 0)
			return ret;
878

879 880
		return !!(ret & BIT(chan->scan_index +
				    chip->ev_cfg_chan_shift));
881 882 883
	default:
		return -EINVAL;
	}
884 885 886 887 888 889 890 891 892
}

static int mma8452_write_event_config(struct iio_dev *indio_dev,
				      const struct iio_chan_spec *chan,
				      enum iio_event_type type,
				      enum iio_event_direction dir,
				      int state)
{
	struct mma8452_data *data = iio_priv(indio_dev);
893
	const struct mma_chip_info *chip = data->chip_info;
894 895 896 897 898
	int val, ret;

	ret = mma8452_set_runtime_pm_state(data->client, state);
	if (ret)
		return ret;
899

900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918
	switch (dir) {
	case IIO_EV_DIR_FALLING:
		return mma8452_set_freefall_mode(data, state);
	case IIO_EV_DIR_RISING:
		val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
		if (val < 0)
			return val;

		if (state) {
			if (mma8452_freefall_mode_enabled(data)) {
				val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
				val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
				val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
				val |= MMA8452_FF_MT_CFG_OAE;
			}
			val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
		} else {
			if (mma8452_freefall_mode_enabled(data))
				return 0;
919

920 921
			val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
		}
922

923
		val |= chip->ev_cfg_ele;
924

925 926 927 928
		return mma8452_change_config(data, chip->ev_cfg, val);
	default:
		return -EINVAL;
	}
929 930 931 932 933
}

static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
{
	struct mma8452_data *data = iio_priv(indio_dev);
934
	s64 ts = iio_get_time_ns(indio_dev);
935 936
	int src;

937
	src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
938 939 940
	if (src < 0)
		return;

941 942 943 944 945 946 947 948 949 950
	if (mma8452_freefall_mode_enabled(data)) {
		iio_push_event(indio_dev,
			       IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
						  IIO_MOD_X_AND_Y_AND_Z,
						  IIO_EV_TYPE_MAG,
						  IIO_EV_DIR_FALLING),
			       ts);
		return;
	}

951
	if (src & data->chip_info->ev_src_xe)
952 953
		iio_push_event(indio_dev,
			       IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
954
						  IIO_EV_TYPE_MAG,
955 956 957
						  IIO_EV_DIR_RISING),
			       ts);

958
	if (src & data->chip_info->ev_src_ye)
959 960
		iio_push_event(indio_dev,
			       IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
961
						  IIO_EV_TYPE_MAG,
962 963 964
						  IIO_EV_DIR_RISING),
			       ts);

965
	if (src & data->chip_info->ev_src_ze)
966 967
		iio_push_event(indio_dev,
			       IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
968
						  IIO_EV_TYPE_MAG,
969 970 971 972 973 974 975 976
						  IIO_EV_DIR_RISING),
			       ts);
}

static irqreturn_t mma8452_interrupt(int irq, void *p)
{
	struct iio_dev *indio_dev = p;
	struct mma8452_data *data = iio_priv(indio_dev);
977
	const struct mma_chip_info *chip = data->chip_info;
978
	int ret = IRQ_NONE;
979 980 981 982 983 984
	int src;

	src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
	if (src < 0)
		return IRQ_NONE;

985 986 987 988 989
	if (src & MMA8452_INT_DRDY) {
		iio_trigger_poll_chained(indio_dev->trig);
		ret = IRQ_HANDLED;
	}

990 991 992 993
	if ((src & MMA8452_INT_TRANS &&
	     chip->ev_src == MMA8452_TRANSIENT_SRC) ||
	    (src & MMA8452_INT_FF_MT &&
	     chip->ev_src == MMA8452_FF_MT_SRC)) {
994
		mma8452_transient_interrupt(indio_dev);
995
		ret = IRQ_HANDLED;
996 997
	}

998
	return ret;
999 1000
}

1001 1002 1003 1004 1005 1006 1007 1008
static irqreturn_t mma8452_trigger_handler(int irq, void *p)
{
	struct iio_poll_func *pf = p;
	struct iio_dev *indio_dev = pf->indio_dev;
	struct mma8452_data *data = iio_priv(indio_dev);
	u8 buffer[16]; /* 3 16-bit channels + padding + ts */
	int ret;

1009
	ret = mma8452_read(data, (__be16 *)buffer);
1010 1011 1012 1013
	if (ret < 0)
		goto done;

	iio_push_to_buffers_with_timestamp(indio_dev, buffer,
1014
					   iio_get_time_ns(indio_dev));
1015 1016 1017

done:
	iio_trigger_notify_done(indio_dev->trig);
1018

1019 1020 1021
	return IRQ_HANDLED;
}

1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043
static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
				  unsigned reg, unsigned writeval,
				  unsigned *readval)
{
	int ret;
	struct mma8452_data *data = iio_priv(indio_dev);

	if (reg > MMA8452_MAX_REG)
		return -EINVAL;

	if (!readval)
		return mma8452_change_config(data, reg, writeval);

	ret = i2c_smbus_read_byte_data(data->client, reg);
	if (ret < 0)
		return ret;

	*readval = ret;

	return 0;
}

1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064
static const struct iio_event_spec mma8452_freefall_event[] = {
	{
		.type = IIO_EV_TYPE_MAG,
		.dir = IIO_EV_DIR_FALLING,
		.mask_separate = BIT(IIO_EV_INFO_ENABLE),
		.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
					BIT(IIO_EV_INFO_PERIOD) |
					BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
	},
};

static const struct iio_event_spec mma8652_freefall_event[] = {
	{
		.type = IIO_EV_TYPE_MAG,
		.dir = IIO_EV_DIR_FALLING,
		.mask_separate = BIT(IIO_EV_INFO_ENABLE),
		.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
					BIT(IIO_EV_INFO_PERIOD)
	},
};

1065 1066
static const struct iio_event_spec mma8452_transient_event[] = {
	{
1067
		.type = IIO_EV_TYPE_MAG,
1068 1069
		.dir = IIO_EV_DIR_RISING,
		.mask_separate = BIT(IIO_EV_INFO_ENABLE),
1070
		.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1071 1072
					BIT(IIO_EV_INFO_PERIOD) |
					BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1073 1074 1075
	},
};

1076 1077 1078 1079 1080 1081 1082 1083 1084 1085
static const struct iio_event_spec mma8452_motion_event[] = {
	{
		.type = IIO_EV_TYPE_MAG,
		.dir = IIO_EV_DIR_RISING,
		.mask_separate = BIT(IIO_EV_INFO_ENABLE),
		.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
					BIT(IIO_EV_INFO_PERIOD)
	},
};

1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100
/*
 * Threshold is configured in fixed 8G/127 steps regardless of
 * currently selected scale for measurement.
 */
static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");

static struct attribute *mma8452_event_attributes[] = {
	&iio_const_attr_accel_transient_scale.dev_attr.attr,
	NULL,
};

static struct attribute_group mma8452_event_attribute_group = {
	.attrs = mma8452_event_attributes,
};

1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118
#define MMA8452_FREEFALL_CHANNEL(modifier) { \
	.type = IIO_ACCEL, \
	.modified = 1, \
	.channel2 = modifier, \
	.scan_index = -1, \
	.event_spec = mma8452_freefall_event, \
	.num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
}

#define MMA8652_FREEFALL_CHANNEL(modifier) { \
	.type = IIO_ACCEL, \
	.modified = 1, \
	.channel2 = modifier, \
	.scan_index = -1, \
	.event_spec = mma8652_freefall_event, \
	.num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
}

1119
#define MMA8452_CHANNEL(axis, idx, bits) { \
1120 1121 1122 1123
	.type = IIO_ACCEL, \
	.modified = 1, \
	.channel2 = IIO_MOD_##axis, \
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1124
			      BIT(IIO_CHAN_INFO_CALIBBIAS), \
1125
	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1126
			BIT(IIO_CHAN_INFO_SCALE) | \
1127 1128
			BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
			BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1129 1130 1131
	.scan_index = idx, \
	.scan_type = { \
		.sign = 's', \
1132
		.realbits = (bits), \
1133
		.storagebits = 16, \
1134
		.shift = 16 - (bits), \
1135 1136
		.endianness = IIO_BE, \
	}, \
1137 1138
	.event_spec = mma8452_transient_event, \
	.num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1139 1140
}

1141 1142 1143 1144 1145 1146 1147
#define MMA8652_CHANNEL(axis, idx, bits) { \
	.type = IIO_ACCEL, \
	.modified = 1, \
	.channel2 = IIO_MOD_##axis, \
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
		BIT(IIO_CHAN_INFO_CALIBBIAS), \
	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1148 1149
		BIT(IIO_CHAN_INFO_SCALE) | \
		BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161
	.scan_index = idx, \
	.scan_type = { \
		.sign = 's', \
		.realbits = (bits), \
		.storagebits = 16, \
		.shift = 16 - (bits), \
		.endianness = IIO_BE, \
	}, \
	.event_spec = mma8452_motion_event, \
	.num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
}

1162 1163 1164 1165 1166 1167 1168 1169
static const struct iio_chan_spec mma8451_channels[] = {
	MMA8452_CHANNEL(X, idx_x, 14),
	MMA8452_CHANNEL(Y, idx_y, 14),
	MMA8452_CHANNEL(Z, idx_z, 14),
	IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
	MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
};

1170
static const struct iio_chan_spec mma8452_channels[] = {
1171 1172 1173 1174
	MMA8452_CHANNEL(X, idx_x, 12),
	MMA8452_CHANNEL(Y, idx_y, 12),
	MMA8452_CHANNEL(Z, idx_z, 12),
	IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1175
	MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1176 1177
};

1178
static const struct iio_chan_spec mma8453_channels[] = {
1179 1180 1181 1182
	MMA8452_CHANNEL(X, idx_x, 10),
	MMA8452_CHANNEL(Y, idx_y, 10),
	MMA8452_CHANNEL(Z, idx_z, 10),
	IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1183
	MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1184 1185
};

1186
static const struct iio_chan_spec mma8652_channels[] = {
1187 1188 1189 1190
	MMA8652_CHANNEL(X, idx_x, 12),
	MMA8652_CHANNEL(Y, idx_y, 12),
	MMA8652_CHANNEL(Z, idx_z, 12),
	IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1191
	MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1192 1193 1194
};

static const struct iio_chan_spec mma8653_channels[] = {
1195 1196 1197 1198
	MMA8652_CHANNEL(X, idx_x, 10),
	MMA8652_CHANNEL(Y, idx_y, 10),
	MMA8652_CHANNEL(Z, idx_z, 10),
	IIO_CHAN_SOFT_TIMESTAMP(idx_ts),