Commit 8ebd6558 authored by Daniel Drake's avatar Daniel Drake Committed by Greg Kroah-Hartman

PCI: Reprogram bridge prefetch registers on resume

commit 08387454 upstream.

On 38+ Intel-based ASUS products, the NVIDIA GPU becomes unusable after S3
suspend/resume.  The affected products include multiple generations of
NVIDIA GPUs and Intel SoCs.  After resume, nouveau logs many errors such

  fifo: fault 00 [READ] at 0000005555555000 engine 00 [GR] client 04
        [HUB/FE] reason 4a [] on channel -1 [007fa91000 unknown]
  DRM: failed to idle channel 0 [DRM]

Similarly, the NVIDIA proprietary driver also fails after resume (black
screen, 100% CPU usage in Xorg process).  We shipped a sample to NVIDIA for
diagnosis, and their response indicated that it's a problem with the parent
PCI bridge (on the Intel SoC), not the GPU.

Runtime suspend/resume works fine, only S3 suspend is affected.

We found a workaround: on resume, rewrite the Intel PCI bridge
'Prefetchable Base Upper 32 Bits' register (PCI_PREF_BASE_UPPER32).  In the
cases that I checked, this register has value 0 and we just have to rewrite
that value.

Linux already saves and restores PCI config space during suspend/resume,
but this register was being skipped because upon resume, it already has
value 0 (the correct, pre-suspend value).

Intel appear to have previously acknowledged this behaviour and the
requirement to rewrite this register:

Based on that, rewrite the prefetch register values even when that appears

We have confirmed this solution on all the affected models we have in-hands
(X542UQ, UX533FD, X530UN, V272UN).

Additionally, this solves an issue where r8169 MSI-X interrupts were broken
after S3 suspend/resume on ASUS X441UAR.  This issue was recently worked
around in commit 7bb05b85 ("r8169: don't use MSI-X on RTL8106e").  It
also fixes the same issue on RTL6186evl/8111evl on an Aimfor-tech laptop
that we had not yet patched.  I suspect it will also fix the issue that was
worked around in commit 7c53a722 ("r8169: don't use MSI-X on

Thomas Martitz reports that this change also solves an issue where the AMD
Radeon Polaris 10 GPU on the HP Zbook 14u G5 is unresponsive after S3

Link: default avatarDaniel Drake <>
Signed-off-by: default avatarBjorn Helgaas <>
Reviewed-by: default avatarRafael J. Wysocki <>
Reviewed-By: default avatarPeter Wu <>
Signed-off-by: default avatarGreg Kroah-Hartman <>
parent 25bc6e80
......@@ -1112,12 +1112,12 @@ int pci_save_state(struct pci_dev *dev)
static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
u32 saved_val, int retry)
u32 saved_val, int retry, bool force)
u32 val;
pci_read_config_dword(pdev, offset, &val);
if (val == saved_val)
if (!force && val == saved_val)
for (;;) {
......@@ -1136,25 +1136,36 @@ static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
static void pci_restore_config_space_range(struct pci_dev *pdev,
int start, int end, int retry)
int start, int end, int retry,
bool force)
int index;
for (index = end; index >= start; index--)
pci_restore_config_dword(pdev, 4 * index,
retry, force);
static void pci_restore_config_space(struct pci_dev *pdev)
if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
pci_restore_config_space_range(pdev, 10, 15, 0);
pci_restore_config_space_range(pdev, 10, 15, 0, false);
/* Restore BARs before the command register. */
pci_restore_config_space_range(pdev, 4, 9, 10);
pci_restore_config_space_range(pdev, 0, 3, 0);
pci_restore_config_space_range(pdev, 4, 9, 10, false);
pci_restore_config_space_range(pdev, 0, 3, 0, false);
} else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
pci_restore_config_space_range(pdev, 12, 15, 0, false);
* Force rewriting of prefetch registers to avoid S3 resume
* issues on Intel PCI bridges that occur when these
* registers are not explicitly written.
pci_restore_config_space_range(pdev, 9, 11, 0, true);
pci_restore_config_space_range(pdev, 0, 8, 0, false);
} else {
pci_restore_config_space_range(pdev, 0, 15, 0);
pci_restore_config_space_range(pdev, 0, 15, 0, false);
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