Commit 8c609698 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform updates from Arnd Bergmann:
 "Most of the commits are for defconfig changes, to enable newly added
  drivers or features that people have started using. For the changed
  lines lines, we have mostly cleanups, the affected platforms are OMAP,
  Versatile, EP93xx, Samsung, Broadcom, i.MX, and Actions.

  The largest single change is the introduction of the TI "sysc" bus
  driver, with the intention of cleaning up more legacy code.

  Two new SoC platforms get added this time:

   - Allwinner R40 is a modernized version of the A20 chip, now with a
     Quad-Core ARM Cortex-A7. According to the manufacturer, it is
     intended for "Smart Hardware"

   - Broadcom Hurricane 2 (Aka Strataconnect BCM5334X) is a family of
     chips meant for managed gigabit ethernet switches, based around a
     Cortex-A9 CPU.

  Finally, we gain SMP support for two platforms: Renesas R-Car E2 and
  Amlogic Meson8/8b, which were previously added but only supported
  uniprocessor operation"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits)
  ARM: multi_v7_defconfig: Select RPMSG_VIRTIO as module
  ARM: multi_v7_defconfig: enable CONFIG_GPIO_UNIPHIER
  arm64: defconfig: enable CONFIG_GPIO_UNIPHIER
  ARM: meson: enable MESON_IRQ_GPIO in Kconfig for meson8b
  ARM: meson: Add SMP bringup code for Meson8 and Meson8b
  ARM: smp_scu: allow the platform code to read the SCU CPU status
  ARM: smp_scu: add a helper for powering on a specific CPU
  dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation
  ARM: OMAP3: Delete an unnecessary variable initialisation in omap3xxx_hwmod_init()
  ARM: OMAP3: Use common error handling code in omap3xxx_hwmod_init()
  ARM: defconfig: select the right SX150X driver
  arm64: defconfig: Enable QCOM_IOMMU
  arm64: Add ThunderX drivers to defconfig
  arm64: defconfig: Enable Tegra PCI controller
  cpufreq: imx6q: Move speed grading check to cpufreq driver
  arm64: defconfig: re-enable Qualcomm DB410c USB
  ARM: configs: stm32: Add MDMA support in STM32 defconfig
  ARM: imx: Enable cpuidle for i.MX6DL starting at 1.1
  bus: ti-sysc: Fix unbalanced pm_runtime_enable by adding remove
  bus: ti-sysc: mark PM functions as __maybe_unused
  ...
parents 18c83d2c fa32475a
......@@ -33,6 +33,11 @@ SunXi family
- Next Thing Co GR8 (sun5i)
* Single ARM Cortex-A7 based SoCs
- Allwinner V3s (sun8i)
+ Datasheet
http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
* Dual ARM Cortex-A7 based SoCs
- Allwinner A20 (sun7i)
+ User Manual
......@@ -71,9 +76,11 @@ SunXi family
+ Datasheet
http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
- Allwinner V3s (sun8i)
- Allwinner R40 (sun8i)
+ Datasheet
http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
https://github.com/tinalinux/docs/raw/r40-v1.y/R40_Datasheet_V1.0.pdf
+ User Manual
https://github.com/tinalinux/docs/raw/r40-v1.y/Allwinner_R40_User_Manual_V1.0.pdf
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
- Allwinner A80
......
Amlogic Meson8 and Meson8b power-management-unit:
-------------------------------------------------
The pmu is used to turn off and on different power domains of the SoCs
This includes the power to the CPU cores.
Required node properties:
- compatible value : depending on the SoC this should be one of:
"amlogic,meson8-pmu"
"amlogic,meson8b-pmu"
- reg : physical base address and the size of the registers window
Example:
pmu@c81000e4 {
compatible = "amlogic,meson8b-pmu", "syscon";
reg = <0xc81000e0 0x18>;
};
Amlogic Meson8 and Meson8b SRAM for smp bringup:
------------------------------------------------
Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
Once the core gets powered up it executes the code that is residing at a
specific location.
Therefore a reserved section sub-node has to be added to the mmio-sram
declaration.
Required sub-node properties:
- compatible : depending on the SoC this should be one of:
"amlogic,meson8-smp-sram"
"amlogic,meson8b-smp-sram"
The rest of the properties should follow the generic mmio-sram discription
found in ../../misc/sram.txt
Example:
sram: sram@d9000000 {
compatible = "mmio-sram";
reg = <0xd9000000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xd9000000 0x20000>;
smp-sram@1ff80 {
compatible = "amlogic,meson8b-smp-sram";
reg = <0x1ff80 0x8>;
};
};
......@@ -197,6 +197,8 @@ described below.
"actions,s500-smp"
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"amlogic,meson8-smp"
"amlogic,meson8b-smp"
"arm,realview-smp"
"brcm,bcm11351-cpu-method"
"brcm,bcm23550"
......
......@@ -21,6 +21,8 @@ Required properties:
"ti,omap3-scm"
"ti,omap4-scm-core"
"ti,omap4-scm-padconf-core"
"ti,omap4-scm-wkup"
"ti,omap4-scm-padconf-wkup"
"ti,omap5-scm-core"
"ti,omap5-scm-padconf-core"
"ti,dra7-scm-core"
......
......@@ -14,6 +14,8 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h2-plus
allwinner,sun8i-h3
allwinner-sun8i-r40
allwinner,sun8i-v3s
allwinner,sun9i-a80
allwinner,sun50i-a64
nextthing,gr8
Texas Instruments sysc interconnect target module wrapper binding
Texas Instruments SoCs can have a generic interconnect target module
hardware for devices connected to various interconnects such as L3
interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
is mostly used for interaction between module and PRCM. It participates
in the OCP Disconnect Protocol but other than that is mostly independent
of the interconnect.
Each interconnect target module can have one or more devices connected to
it. There is a set of control registers for managing interconnect target
module clocks, idle modes and interconnect level resets for the module.
These control registers are sprinkled into the unused register address
space of the first child device IP block managed by the interconnect
target module and typically are named REVISION, SYSCONFIG and SYSSTATUS.
Required standard properties:
- compatible shall be one of the following generic types:
"ti,sysc-omap2"
"ti,sysc-omap4"
"ti,sysc-omap4-simple"
or one of the following derivative types for hardware
needing special workarounds:
"ti,sysc-omap3430-sr"
"ti,sysc-omap3630-sr"
"ti,sysc-omap4-sr"
"ti,sysc-omap3-sham"
"ti,sysc-omap-aes"
"ti,sysc-mcasp"
"ti,sysc-usb-host-fs"
- reg shall have register areas implemented for the interconnect
target module in question such as revision, sysc and syss
- reg-names shall contain the register names implemented for the
interconnect target module in question such as
"rev, "sysc", and "syss"
- ranges shall contain the interconnect target module IO range
available for one or more child device IP blocks managed
by the interconnect target module, the ranges may include
multiple ranges such as device L4 range for control and
parent L3 range for DMA access
Optional properties:
- clocks clock specifier for each name in the clock-names as
specified in the binding documentation for ti-clkctrl,
typically available for all interconnect targets on TI SoCs
based on omap4 except if it's read-only register in hwauto
mode as for example omap4 L4_CFG_CLKCTRL
- clock-names should contain at least "fck", and optionally also "ick"
depending on the SoC and the interconnect target module
- ti,hwmods optional TI interconnect module name to use legacy
hwmod platform data
Example: Single instance of MUSB controller on omap4 using interconnect ranges
using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
compatible = "ti,sysc-omap2";
ti,hwmods = "usb_otg_hs";
reg = <0x2b400 0x4>,
<0x2b404 0x4>,
<0x2b408 0x4>;
reg-names = "rev", "sysc", "syss";
clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2b000 0x1000>;
usb_otg_hs: otg@0 {
compatible = "ti,omap4-musb";
reg = <0x0 0x7ff>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb2_phy>;
...
};
};
Note that other SoCs, such as am335x can have multipe child devices. On am335x
there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA
instance as children of a single interconnet target module.
......@@ -7,8 +7,10 @@ of the EMIF IP and memory parts attached to it.
Required properties:
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
is the IP revision of the specific EMIF instance.
For am437x should be ti,emif-am4372.
is the IP revision of the specific EMIF instance. For newer controllers,
compatible should be one of the following:
"ti,emif-am3352"
"ti,emif-am4372"
- phy-type : <u32> indicating the DDR phy type. Following are the
allowed values
......
Texas Instruments SmartReflex binding
SmartReflex is used to set and adjust the SoC operating points.
Required properties:
compatible: Shall be one of the following:
"ti,omap3-smartreflex-core"
"ti,omap3-smartreflex-iva"
"ti,omap4-smartreflex-core"
"ti,omap4-smartreflex-mpu"
"ti,omap4-smartreflex-iva"
reg: Shall contain the device instance IO range
interrupts: Shall contain the device instance interrupt
Optional properties:
ti,hwmods: Shall contain the TI interconnect module name if needed
by the SoC
Example:
smartreflex_iva: smartreflex@4a0db000 {
compatible = "ti,omap4-smartreflex-iva";
reg = <0x4a0db000 0x80>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "smartreflex_iva";
};
smartreflex_core: smartreflex@4a0dd000 {
compatible = "ti,omap4-smartreflex-core";
reg = <0x4a0dd000 0x80>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "smartreflex_core";
};
smartreflex_mpu: smartreflex@4a0d9000 {
compatible = "ti,omap4-smartreflex-mpu";
reg = <0x4a0d9000 0x80>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "smartreflex_mpu";
};
......@@ -2162,7 +2162,6 @@ F: sound/soc/zte/
ARM/ZYNQ ARCHITECTURE
M: Michal Simek <michal.simek@xilinx.com>
R: Sören Brinkmann <soren.brinkmann@xilinx.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://wiki.xilinx.com
T: git https://github.com/Xilinx/linux-xlnx.git
......@@ -2937,6 +2936,7 @@ N: bcm583*
N: bcm585*
N: bcm586*
N: bcm88312
N: hr2
F: arch/arm64/boot/dts/broadcom/ns2*
F: drivers/clk/bcm/clk-ns*
F: drivers/pinctrl/bcm/pinctrl-ns*
......
......@@ -371,7 +371,7 @@ config ARCH_EBSA110
config ARCH_EP93XX
bool "EP93xx-based"
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SPARSEMEM_ENABLE
select ARM_AMBA
imply ARM_PATCH_PHYS_VIRT
select ARM_VIC
......
......@@ -170,6 +170,11 @@ choice
depends on ARCH_BCM_5301X || ARCH_BCM_NSP
select DEBUG_UART_8250
config DEBUG_BCM_HR2
bool "Kernel low-level debugging on Hurricane 2 UART2"
depends on ARCH_BCM_HR2
select DEBUG_UART_8250
config DEBUG_BCM_KONA_UART
bool "Kernel low-level debugging messages via BCM KONA UART"
depends on ARCH_BCM_MOBILE
......@@ -912,6 +917,13 @@ choice
Say Y here if you want kernel low-level debugging support
via SCIF2 on Renesas R-Car E2 (R8A7794).
config DEBUG_RCAR_GEN2_SCIF4
bool "Kernel low-level debugging messages via SCIF4 on R8A7745"
depends on ARCH_R8A7745
help
Say Y here if you want kernel low-level debugging support
via SCIF4 on Renesas RZ/G1E (R8A7745).
config DEBUG_RMOBILE_SCIFA0
bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4"
depends on ARCH_R8A73A4
......@@ -1452,6 +1464,7 @@ config DEBUG_LL_INCLUDE
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF0
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF2
default "debug/renesas-scif.S" if DEBUG_RCAR_GEN2_SCIF4
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1
default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
......@@ -1509,6 +1522,7 @@ config DEBUG_UART_PHYS
default 0x11009000 if DEBUG_MT8135_UART3
default 0x16000000 if DEBUG_INTEGRATOR
default 0x18000300 if DEBUG_BCM_5301X
default 0x18000400 if DEBUG_BCM_HR2
default 0x18010000 if DEBUG_SIRFATLAS7_UART0
default 0x18020000 if DEBUG_SIRFATLAS7_UART1
default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
......@@ -1571,6 +1585,7 @@ config DEBUG_UART_PHYS
default 0xe6c80000 if DEBUG_RMOBILE_SCIFA4
default 0xe6e58000 if DEBUG_RCAR_GEN2_SCIF2
default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4
default 0xe8008000 if DEBUG_R7S72100_SCIF2
default 0xf0000be0 if ARCH_EBSA110
default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE
......@@ -1605,6 +1620,7 @@ config DEBUG_UART_PHYS
DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \
DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \
DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \
DEBUG_RCAR_GEN2_SCIF4 || \
DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \
DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
DEBUG_S3C64XX_UART || \
......@@ -1624,6 +1640,7 @@ config DEBUG_UART_VIRT
default 0xf01fb000 if DEBUG_NOMADIK_UART
default 0xf0201000 if DEBUG_BCM2835 || DEBUG_BCM2836
default 0xf1000300 if DEBUG_BCM_5301X
default 0xf1000400 if DEBUG_BCM_HR2
default 0xf1002000 if DEBUG_MT8127_UART0
default 0xf1006000 if DEBUG_MT6589_UART0
default 0xf1009000 if DEBUG_MT8135_UART3
......@@ -1729,7 +1746,8 @@ config DEBUG_UART_8250_SHIFT
int "Register offset shift for the 8250 debug UART"
depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
default 0 if DEBUG_FOOTBRIDGE_COM1 || ARCH_IOP32X || DEBUG_BCM_5301X || \
DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || DEBUG_OMAP7XXUART3
DEBUG_BCM_HR2 || DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || \
DEBUG_OMAP7XXUART3
default 2
config DEBUG_UART_8250_WORD
......
......@@ -149,6 +149,7 @@ textofs-$(CONFIG_SA1111) := 0x00208000
endif
textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
textofs-$(CONFIG_ARCH_MESON) := 0x00208000
textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
# Machine directory name. This list is sorted alphanumerically
......
......@@ -130,9 +130,11 @@
};
};
pmu {
pmu@4b000000 {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
reg = <0x4b000000 0x1000000>;
ti,hwmods = "debugss";
};
/*
......@@ -929,6 +931,12 @@
};
};
emif: emif@4c000000 {
compatible = "ti,emif-am3352";
reg = <0x4c000000 0x1000000>;
ti,hwmods = "emif";
};
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
......
......@@ -457,6 +457,7 @@
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <127>;
ti,hwmods = "dma_system";
};
edma: edma@43300000 {
......@@ -1069,6 +1070,13 @@
max-frequency = <192000000>;
};
hdqw1w: 1w@480b2000 {
compatible = "ti,omap3-1w";
reg = <0x480b2000 0x1000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "hdq1w";
};
mmc2: mmc@480b4000 {
compatible = "ti,omap4-hsmmc";
reg = <0x480b4000 0x400>;
......@@ -1489,6 +1497,32 @@
};
};
target-module@4a0dd000 {
compatible = "ti,sysc-omap4-sr";
ti,hwmods = "smartreflex_core";
reg = <0x4a0dd000 0x4>,
<0x4a0dd008 0x4>;
reg-names = "rev", "sysc";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a0dd000 0x001000>;
/* SmartReflex child device marked reserved in TRM */
};
target-module@4a0d9000 {
compatible = "ti,sysc-omap4-sr";
ti,hwmods = "smartreflex_mpu";
reg = <0x4a0d9000 0x4>,
<0x4a0d9008 0x4>;
reg-names = "rev", "sysc";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a0d9000 0x001000>;
/* SmartReflex child device marked reserved in TRM */
};
omap_dwc3_1: omap_dwc3_1@48880000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss1";
......
......@@ -215,6 +215,7 @@
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <96>;
ti,hwmods = "dma";
};
gpio1: gpio@48310000 {
......
......@@ -51,6 +51,17 @@
};
};
/*
* Note that 4430 needs cross trigger interface (CTI) supported
* before we can configure the interrupts. This means sampling
* events are not supported for pmu. Note that 4460 does not use
* CTI, see also 4460.dtsi.
*/
pmu {
compatible = "arm,cortex-a9-pmu";
ti,hwmods = "debugss";
};
gic: interrupt-controller@48241000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
......@@ -163,6 +174,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x1000>;
ti,hwmods = "ctrl_module_core";
scm_conf: scm_conf@0 {
compatible = "syscon";
......@@ -175,9 +187,11 @@
omap4_padconf_core: scm@100000 {
compatible = "ti,omap4-scm-padconf-core",
"simple-bus";
reg = <0x100000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x100000 0x1000>;
ti,hwmods = "ctrl_module_pad_core";
omap4_pmx_core: pinmux@40 {
compatible = "ti,omap4-padconf",
......@@ -252,17 +266,33 @@
};
};
omap4_pmx_wkup: pinmux@1e040 {
compatible = "ti,omap4-padconf",
"pinctrl-single";
reg = <0x1e040 0x0038>;
omap4_scm_wkup: scm@c000 {
compatible = "ti,omap4-scm-wkup";
reg = <0xc000 0x1000>;
ti,hwmods = "ctrl_module_wkup";
};
omap4_padconf_wkup: padconf@1e000 {
compatible = "ti,omap4-scm-padconf-wkup",
"simple-bus";
reg = <0x1e000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
#size-cells = <1>;
ranges = <0 0x1e000 0x1000>;
ti,hwmods = "ctrl_module_pad_wkup";
omap4_pmx_wkup: pinmux@40 {
compatible = "ti,omap4-padconf",
"pinctrl-single";
reg = <0x40 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
};
};
};
......@@ -282,6 +312,7 @@
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <127>;
ti,hwmods = "dma_system";
};
gpio1: gpio@4a310000 {
......@@ -351,6 +382,19 @@
#interrupt-cells = <2>;
};
target-module@48076000 {
compatible = "ti,sysc-omap4";
ti,hwmods = "slimbus2";
reg = <0x48076000 0x4>,
<0x48076010 0x4>;
reg-names = "rev", "sysc";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48076000 0x001000>;
/* No child device binding or driver in mainline */
};
elm: elm@48078000 {
compatible = "ti,am3352-elm";
reg = <0x48078000 0x2000>;
......@@ -411,6 +455,57 @@
clock-frequency = <48000000>;
};
target-module@4a0db000 {
compatible = "ti,sysc-sr";
ti,hwmods = "smartreflex_iva";
reg = <0x4a0db000 0x4>,
<0x4a0db008 0x4>;
reg-names = "rev", "sysc";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a0db000 0x001000>;
smartreflex_iva: smartreflex@0 {
compatible = "ti,omap4-smartreflex-iva";
reg = <0 0x80>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@4a0dd000 {
compatible = "ti,sysc-sr";
ti,hwmods = "smartreflex_core";
reg = <0x4a0dd000 0x4>,
<0x4a0dd008 0x4>;
reg-names = "rev", "sysc";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a0dd000 0x001000>;
smartreflex_core: smartreflex@0 {
compatible = "ti,omap4-smartreflex-core";
reg = <0 0x80>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@4a0d9000 {
compatible = "ti,sysc-sr";
ti,hwmods = "smartreflex_mpu";
reg = <0x4a0d9000 0x4>,
<0x4a0d9008 0x4>;
reg-names = "rev", "sysc";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a0d9000 0x001000>;
smartreflex_mpu: smartreflex@0 {
compatible = "ti,omap4-smartreflex-mpu";
reg = <0 0x80>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;