Commit 915db32d authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (21 commits)
  MIPS: Alchemy: PB1200: use SMC91X platform data.
  MIPS: Alchemy: MIPS hazard workarounds are not required.
  MIPS: Alchemy: provide cpu feature overrides.
  MIPS: Alchemy: unify CPU model constants.
  MIPS: Make a needlessly global symbol static in arch/mips/kernel/smp.c
  MIPS: Fix global namespace pollution in arch/mips/kernel/smp-up.c
  MIPS: Malta: make a needlessly global integer variable static
  MIPS: Use BUG_ON() where possible.
  MIPS: Convert obsolete irq_desc_t to struct irq_desc
  MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms
  MIPS: EMMA2RH: Set UART mapbase
  MIPS: EMMA2RH: Use set_irq_chip_and_handler_name
  MIPS: EMMA2RH: Use handle_edge_irq() handler for GPIO interrupts
  MIPS: Mark Eins: Fix cascading interrupt dispatcher
  MIPS: Au1000: convert to using gpiolib
  MIPS: Stop using <asm-generic/int-l64.h>.
  MIPS: Cavium: Add -Werror
  MIPS: Makefile: Add simple make install target.
  MIPS: Compat: Zero upper 32-bit of offset_high and offset_low.
  MIPS: __raw_spin_lock() may spin forever on ticket wrap.
  ...
parents ebc8eca1 91e8a30e
......@@ -77,7 +77,6 @@ config MIPS_COBALT
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
config MACH_DECSTATION
bool "DECstations"
......@@ -132,7 +131,6 @@ config MACH_JAZZ
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_100HZ
select GENERIC_HARDIRQS_NO__DO_IRQ
help
This a family of machines based on the MIPS R4030 chipset which was
used by several vendors to build RISC/os and Windows NT workstations.
......@@ -154,7 +152,6 @@ config LASAT
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
select SYS_SUPPORTS_LITTLE_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
config LEMOTE_FULONG
bool "Lemote Fulong mini-PC"
......@@ -175,7 +172,6 @@ config LEMOTE_FULONG
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_ISA_DMA_SUPPORT_BROKEN
select CPU_HAS_WB
help
......@@ -250,7 +246,6 @@ config MACH_VR41XX
select CEVT_R4K
select CSRC_R4K
select SYS_HAS_CPU_VR41XX
select GENERIC_HARDIRQS_NO__DO_IRQ
config NXP_STB220
bool "NXP STB220 board"
......@@ -364,7 +359,6 @@ config SGI_IP27
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_NUMA
select SYS_SUPPORTS_SMP
select GENERIC_HARDIRQS_NO__DO_IRQ
help
This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
workstations. To compile a Linux kernel that runs on these, say Y
......@@ -563,7 +557,6 @@ config MIKROTIK_RB532
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select GENERIC_HARDIRQS_NO__DO_IRQ
select HW_HAS_PCI
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
......@@ -700,8 +693,7 @@ config SCHED_OMIT_FRAME_POINTER
default y
config GENERIC_HARDIRQS_NO__DO_IRQ
bool
default n
def_bool y
#
# Select some configuration options automatically based on user selections.
......@@ -920,7 +912,6 @@ config SOC_PNX833X
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_BIG_ENDIAN
select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_GPIO
select CPU_MIPSR2_IRQ_VI
......@@ -939,7 +930,6 @@ config SOC_PNX8550
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select GENERIC_HARDIRQS_NO__DO_IRQ
select GENERIC_GPIO
config SWAP_IO_SPACE
......
......@@ -720,11 +720,17 @@ ifdef CONFIG_MIPS32_O32
$(Q)$(MAKE) $(build)=. missing-syscalls EXTRA_CFLAGS="-mabi=32"
endif
install:
$(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
$(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
$(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
archclean:
@$(MAKE) $(clean)=arch/mips/boot
@$(MAKE) $(clean)=arch/mips/lasat
define archhelp
echo ' install - install kernel into $(INSTALL_PATH)'
echo ' vmlinux.ecoff - ECOFF boot image'
echo ' vmlinux.bin - Raw binary boot image'
echo ' vmlinux.srec - SREC boot image'
......
......@@ -134,4 +134,4 @@ config SOC_AU1X00
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_APM_EMULATION
select GENERIC_HARDIRQS_NO__DO_IRQ
select ARCH_REQUIRE_GPIOLIB
/*
* Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
* Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
* Architecture specific GPIO support
*
* This program is free software; you can redistribute it and/or modify it
......@@ -27,122 +27,175 @@
* others have a second one : GPIO2
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/gpio.h>
#define gpio1 sys
#if !defined(CONFIG_SOC_AU1000)
static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE;
#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
struct au1000_gpio_chip {
struct gpio_chip chip;
void __iomem *regbase;
};
static int au1xxx_gpio2_read(unsigned gpio)
#if !defined(CONFIG_SOC_AU1000)
static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
{
gpio -= AU1XXX_GPIO_BASE;
return ((gpio2->pinstate >> gpio) & 0x01);
u32 mask = 1 << offset;
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
}
static void au1xxx_gpio2_write(unsigned gpio, int value)
static void au1000_gpio2_set(struct gpio_chip *chip,
unsigned offset, int value)
{
gpio -= AU1XXX_GPIO_BASE;
u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
local_irq_save(flags);
writel(mask, gpch->regbase + AU1000_GPIO2_OUT);
local_irq_restore(flags);
}
static int au1xxx_gpio2_direction_input(unsigned gpio)
static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
{
gpio -= AU1XXX_GPIO_BASE;
gpio2->dir &= ~(0x01 << gpio);
u32 mask = 1 << offset;
u32 tmp;
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
local_irq_save(flags);
tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
tmp &= ~mask;
writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
local_irq_restore(flags);
return 0;
}
static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
static int au1000_gpio2_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
gpio -= AU1XXX_GPIO_BASE;
gpio2->dir |= 0x01 << gpio;
gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
u32 mask = 1 << offset;
u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
u32 tmp;
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
local_irq_save(flags);
tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
tmp |= mask;
writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT);
local_irq_restore(flags);
return 0;
}
#endif /* !defined(CONFIG_SOC_AU1000) */
static int au1xxx_gpio1_read(unsigned gpio)
static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
{
return (gpio1->pinstaterd >> gpio) & 0x01;
u32 mask = 1 << offset;
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
return readl(gpch->regbase + AU1000_GPIO1_ST) & mask;
}
static void au1xxx_gpio1_write(unsigned gpio, int value)
static void au1000_gpio1_set(struct gpio_chip *chip,
unsigned offset, int value)
{
u32 mask = 1 << offset;
u32 reg_offset;
struct au1000_gpio_chip *gpch;
unsigned long flags;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
if (value)
gpio1->outputset = (0x01 << gpio);
reg_offset = AU1000_GPIO1_OUT;
else
/* Output a zero */
gpio1->outputclr = (0x01 << gpio);
}
reg_offset = AU1000_GPIO1_CLR;
static int au1xxx_gpio1_direction_input(unsigned gpio)
{
gpio1->pininputen = (0x01 << gpio);
return 0;
local_irq_save(flags);
writel(mask, gpch->regbase + reg_offset);
local_irq_restore(flags);
}
static int au1xxx_gpio1_direction_output(unsigned gpio, int value)
static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
{
gpio1->trioutclr = (0x01 & gpio);
au1xxx_gpio1_write(gpio, value);
u32 mask = 1 << offset;
struct au1000_gpio_chip *gpch;
gpch = container_of(chip, struct au1000_gpio_chip, chip);
writel(mask, gpch->regbase + AU1000_GPIO1_ST);
return 0;
}
int au1xxx_gpio_get_value(unsigned gpio)
static int au1000_gpio1_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
if (gpio >= AU1XXX_GPIO_BASE)
#if defined(CONFIG_SOC_AU1000)
return 0;
#else
return au1xxx_gpio2_read(gpio);
#endif
else
return au1xxx_gpio1_read(gpio);
}
EXPORT_SYMBOL(au1xxx_gpio_get_value);
u32 mask = 1 << offset;
struct au1000_gpio_chip *gpch;
void au1xxx_gpio_set_value(unsigned gpio, int value)
{
if (gpio >= AU1XXX_GPIO_BASE)
#if defined(CONFIG_SOC_AU1000)
;
#else
au1xxx_gpio2_write(gpio, value);
#endif
else
au1xxx_gpio1_write(gpio, value);
}
EXPORT_SYMBOL(au1xxx_gpio_set_value);
gpch = container_of(chip, struct au1000_gpio_chip, chip);
int au1xxx_gpio_direction_input(unsigned gpio)
{
if (gpio >= AU1XXX_GPIO_BASE)
#if defined(CONFIG_SOC_AU1000)
return -ENODEV;
#else
return au1xxx_gpio2_direction_input(gpio);
#endif
writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT);
au1000_gpio1_set(chip, offset, value);
return au1xxx_gpio1_direction_input(gpio);
return 0;
}
EXPORT_SYMBOL(au1xxx_gpio_direction_input);
int au1xxx_gpio_direction_output(unsigned gpio, int value)
struct au1000_gpio_chip au1000_gpio_chip[] = {
[0] = {
.regbase = (void __iomem *)SYS_BASE,
.chip = {
.label = "au1000-gpio1",
.direction_input = au1000_gpio1_direction_input,
.direction_output = au1000_gpio1_direction_output,
.get = au1000_gpio1_get,
.set = au1000_gpio1_set,
.base = 0,
.ngpio = 32,
},
},
#if !defined(CONFIG_SOC_AU1000)
[1] = {
.regbase = (void __iomem *)GPIO2_BASE,
.chip = {
.label = "au1000-gpio2",
.direction_input = au1000_gpio2_direction_input,
.direction_output = au1000_gpio2_direction_output,
.get = au1000_gpio2_get,
.set = au1000_gpio2_set,
.base = AU1XXX_GPIO_BASE,
.ngpio = 32,
},
},
#endif
};
static int __init au1000_gpio_init(void)
{
if (gpio >= AU1XXX_GPIO_BASE)
#if defined(CONFIG_SOC_AU1000)
return -ENODEV;
#else
return au1xxx_gpio2_direction_output(gpio, value);
gpiochip_add(&au1000_gpio_chip[0].chip);
#if !defined(CONFIG_SOC_AU1000)
gpiochip_add(&au1000_gpio_chip[1].chip);
#endif
return au1xxx_gpio1_direction_output(gpio, value);
return 0;
}
EXPORT_SYMBOL(au1xxx_gpio_direction_output);
arch_initcall(au1000_gpio_init);
......@@ -22,6 +22,7 @@
#include <linux/init.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/smc91x.h>
#include <asm/mach-au1x00/au1xxx.h>
#include <asm/mach-au1x00/au1100_mmc.h>
......@@ -131,6 +132,12 @@ static struct platform_device ide_device = {
.resource = ide_resources
};
static struct smc91x_platdata smc_data = {
.flags = SMC91X_NOWAIT | SMC91X_USE_16BIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource smc91c111_resources[] = {
[0] = {
.name = "smc91x-regs",
......@@ -146,6 +153,9 @@ static struct resource smc91c111_resources[] = {
};
static struct platform_device smc91c111_device = {
.dev = {
.platform_data = &smc_data,
},
.name = "smc91x",
.id = -1,
.num_resources = ARRAY_SIZE(smc91c111_resources),
......
......@@ -14,3 +14,5 @@ obj-y += dma-octeon.o flash_setup.o
obj-y += octeon-memcpy.o
obj-$(CONFIG_SMP) += smp.o
EXTRA_CFLAGS += -Werror
......@@ -57,7 +57,7 @@ static int __init flash_init(void)
flash_map.bankwidth = 1;
flash_map.virt = ioremap(flash_map.phys, flash_map.size);
pr_notice("Bootbus flash: Setting flash for %luMB flash at "
"0x%08lx\n", flash_map.size >> 20, flash_map.phys);
"0x%08llx\n", flash_map.size >> 20, flash_map.phys);
simple_map_init(&flash_map);
mymtd = do_map_probe("cfi_probe", &flash_map);
if (mymtd) {
......
......@@ -31,7 +31,7 @@ static void octeon_irq_core_ack(unsigned int irq)
static void octeon_irq_core_eoi(unsigned int irq)
{
irq_desc_t *desc = irq_desc + irq;
struct irq_desc *desc = irq_desc + irq;
unsigned int bit = irq - OCTEON_IRQ_SW0;
/*
* If an IRQ is being processed while we are disabling it the
......
......@@ -80,9 +80,9 @@ void emma2rh_irq_init(void)
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i,
&emma2rh_irq_controller,
handle_level_irq);
set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
&emma2rh_irq_controller,
handle_level_irq, "level");
}
static void emma2rh_sw_irq_enable(unsigned int irq)
......@@ -120,9 +120,9 @@ void emma2rh_sw_irq_init(void)
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i,
&emma2rh_sw_irq_controller,
handle_level_irq);
set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
&emma2rh_sw_irq_controller,
handle_level_irq, "level");
}
static void emma2rh_gpio_irq_enable(unsigned int irq)
......@@ -149,37 +149,28 @@ static void emma2rh_gpio_irq_disable(unsigned int irq)
static void emma2rh_gpio_irq_ack(unsigned int irq)
{
u32 reg;
irq -= EMMA2RH_GPIO_IRQ_BASE;
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg &= ~(1 << irq);
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
static void emma2rh_gpio_irq_end(unsigned int irq)
static void emma2rh_gpio_irq_mask_ack(unsigned int irq)
{
u32 reg;
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
irq -= EMMA2RH_GPIO_IRQ_BASE;
irq -= EMMA2RH_GPIO_IRQ_BASE;
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg |= 1 << irq;
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
reg &= ~(1 << irq);
emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
}
struct irq_chip emma2rh_gpio_irq_controller = {
.name = "emma2rh_gpio_irq",
.ack = emma2rh_gpio_irq_ack,
.mask = emma2rh_gpio_irq_disable,
.mask_ack = emma2rh_gpio_irq_ack,
.mask_ack = emma2rh_gpio_irq_mask_ack,
.unmask = emma2rh_gpio_irq_enable,
.end = emma2rh_gpio_irq_end,
};
void emma2rh_gpio_irq_init(void)
......@@ -187,8 +178,9 @@ void emma2rh_gpio_irq_init(void)
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
&emma2rh_gpio_irq_controller);
set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
&emma2rh_gpio_irq_controller,
handle_edge_irq, "edge");
}
static struct irqaction irq_cascade = {
......@@ -213,8 +205,7 @@ void emma2rh_irq_dispatch(void)
emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
#ifdef EMMA2RH_SW_CASCADE
if (intStatus &
(1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
if (intStatus & (1UL << EMMA2RH_SW_CASCADE)) {
u32 swIntStatus;
swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
& emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
......@@ -225,6 +216,8 @@ void emma2rh_irq_dispatch(void)
}
}
}
/* Skip S/W interrupt */
intStatus &= ~(1UL << EMMA2RH_SW_CASCADE);
#endif
for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
......@@ -238,8 +231,7 @@ void emma2rh_irq_dispatch(void)
emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
#ifdef EMMA2RH_GPIO_CASCADE
if (intStatus &
(1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
if (intStatus & (1UL << (EMMA2RH_GPIO_CASCADE % 32))) {
u32 gpioIntStatus;
gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
& emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
......@@ -250,6 +242,8 @@ void emma2rh_irq_dispatch(void)
}
}
}
/* Skip GPIO interrupt */
intStatus &= ~(1UL << (EMMA2RH_GPIO_CASCADE % 32));
#endif
for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
......
......@@ -110,6 +110,7 @@ struct platform_device i2c_emma_devices[] = {
static struct plat_serial8250_port platform_serial_ports[] = {
[0] = {
.membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
.mapbase = EMMA2RH_PFUR0_BASE + 3,
.irq = EMMA2RH_IRQ_PFUR0,
.uartclk = EMMA2RH_SERIAL_CLOCK,
.regshift = 4,
......@@ -117,6 +118,7 @@ static struct plat_serial8250_port platform_serial_ports[] = {
.flags = EMMA2RH_SERIAL_FLAGS,
}, [1] = {
.membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
.mapbase = EMMA2RH_PFUR1_BASE + 3,
.irq = EMMA2RH_IRQ_PFUR1,
.uartclk = EMMA2RH_SERIAL_CLOCK,
.regshift = 4,
......@@ -124,6 +126,7 @@ static struct plat_serial8250_port platform_serial_ports[] = {
.flags = EMMA2RH_SERIAL_FLAGS,
}, [2] = {
.membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
.mapbase = EMMA2RH_PFUR2_BASE + 3,
.irq = EMMA2RH_IRQ_PFUR2,
.uartclk = EMMA2RH_SERIAL_CLOCK,
.regshift = 4,
......
......@@ -209,8 +209,7 @@ enum cpu_type_enum {
* MIPS32 class processors
*/
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
/*
* MIPS64 class processors
......
......@@ -87,7 +87,7 @@ do { \
: "=r" (tmp)); \
} while (0)
#elif defined(CONFIG_CPU_MIPSR1)
#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
/*
* These are slightly complicated by the fact that we guarantee R1 kernels to
......@@ -139,7 +139,7 @@ do { \
} while (0)
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
defined(CONFIG_CPU_R5500)
defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
......
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_tx39_cache 0
#define cpu_has_fpu 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_mcheck 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_mips16 0
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 1
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_vint 0
#define cpu_has_veic 0
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32