speedstep-lib.c 11.6 KB
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/*
 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
 *
 *  Licensed under the terms of the GNU GPL License version 2.
 *
 *  Library for common functions for Intel SpeedStep v.1 and v.2 support
 *
 *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
 */

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/cpufreq.h>

#include <asm/msr.h>
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#include <asm/tsc.h>
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#include "speedstep-lib.h"

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#define PFX "speedstep-lib: "
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#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
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static int relaxed_check;
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#else
#define relaxed_check 0
#endif

/*********************************************************************
 *                   GET PROCESSOR CORE SPEED IN KHZ                 *
 *********************************************************************/

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static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
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{
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	/* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
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	static const struct {
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		unsigned int ratio;	/* Frequency Multiplier (x10) */
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		u8 bitmap;		/* power on configuration bits
					[27, 25:22] (in MSR 0x2a) */
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	} msr_decode_mult[] = {
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		{ 30, 0x01 },
		{ 35, 0x05 },
		{ 40, 0x02 },
		{ 45, 0x06 },
		{ 50, 0x00 },
		{ 55, 0x04 },
		{ 60, 0x0b },
		{ 65, 0x0f },
		{ 70, 0x09 },
		{ 75, 0x0d },
		{ 80, 0x0a },
		{ 85, 0x26 },
		{ 90, 0x20 },
		{ 100, 0x2b },
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		{ 0, 0xff }	/* error or unknown value */
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	};

	/* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
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	static const struct {
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		unsigned int value;	/* Front Side Bus speed in MHz */
		u8 bitmap;		/* power on configuration bits [18: 19]
					(in MSR 0x2a) */
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	} msr_decode_fsb[] = {
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		{  66, 0x0 },
		{ 100, 0x2 },
		{ 133, 0x1 },
		{   0, 0xff}
	};

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	u32 msr_lo, msr_tmp;
	int i = 0, j = 0;
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	/* read MSR 0x2a - we only need the low 32 bits */
	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
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	pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
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	msr_tmp = msr_lo;

	/* decode the FSB */
	msr_tmp &= 0x00c0000;
	msr_tmp >>= 18;
	while (msr_tmp != msr_decode_fsb[i].bitmap) {
		if (msr_decode_fsb[i].bitmap == 0xff)
			return 0;
		i++;
	}

	/* decode the multiplier */
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	if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
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		pr_debug("workaround for early PIIIs\n");
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		msr_lo &= 0x03c00000;
	} else
		msr_lo &= 0x0bc00000;
	msr_lo >>= 22;
	while (msr_lo != msr_decode_mult[j].bitmap) {
		if (msr_decode_mult[j].bitmap == 0xff)
			return 0;
		j++;
	}

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	pr_debug("speed is %u\n",
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		(msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
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	return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
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}


static unsigned int pentiumM_get_frequency(void)
{
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	u32 msr_lo, msr_tmp;
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	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
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	pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
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	/* see table B-2 of 24547212.pdf */
	if (msr_lo & 0x00040000) {
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		printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
				msr_lo, msr_tmp);
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		return 0;
	}

	msr_tmp = (msr_lo >> 22) & 0x1f;
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	pr_debug("bits 22-26 are 0x%x, speed is %u\n",
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			msr_tmp, (msr_tmp * 100 * 1000));
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	return msr_tmp * 100 * 1000;
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}

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static unsigned int pentium_core_get_frequency(void)
{
	u32 fsb = 0;
	u32 msr_lo, msr_tmp;
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	int ret;
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	rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
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	/* see table B-2 of 25366920.pdf */
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	switch (msr_lo & 0x07) {
	case 5:
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		fsb = 100000;
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		break;
	case 1:
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		fsb = 133333;
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		break;
	case 3:
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		fsb = 166667;
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		break;
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	case 2:
		fsb = 200000;
		break;
	case 0:
		fsb = 266667;
		break;
	case 4:
		fsb = 333333;
		break;
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	default:
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		pr_err("PCORE - MSR_FSB_FREQ undefined value\n");
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	}

	rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
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	pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
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			msr_lo, msr_tmp);
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	msr_tmp = (msr_lo >> 22) & 0x1f;
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	pr_debug("bits 22-26 are 0x%x, speed is %u\n",
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			msr_tmp, (msr_tmp * fsb));
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	ret = (msr_tmp * fsb);
	return ret;
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}
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static unsigned int pentium4_get_frequency(void)
{
	struct cpuinfo_x86 *c = &boot_cpu_data;
	u32 msr_lo, msr_hi, mult;
	unsigned int fsb = 0;
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	unsigned int ret;
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	u8 fsb_code;

	/* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency
	 * to System Bus Frequency Ratio Field in the Processor Frequency
	 * Configuration Register of the MSR. Therefore the current
	 * frequency cannot be calculated and has to be measured.
	 */
	if (c->x86_model < 2)
		return cpu_khz;
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	rdmsr(0x2c, msr_lo, msr_hi);

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	pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
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	/* decode the FSB: see IA-32 Intel (C) Architecture Software
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	 * Developer's Manual, Volume 3: System Prgramming Guide,
	 * revision #12 in Table B-1: MSRs in the Pentium 4 and
	 * Intel Xeon Processors, on page B-4 and B-5.
	 */
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	fsb_code = (msr_lo >> 16) & 0x7;
	switch (fsb_code) {
	case 0:
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		fsb = 100 * 1000;
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		break;
	case 1:
		fsb = 13333 * 10;
		break;
	case 2:
		fsb = 200 * 1000;
		break;
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	}

	if (!fsb)
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		printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
				"Please send an e-mail to <linux@brodo.de>\n");
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	/* Multiplier. */
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	mult = msr_lo >> 24;
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	pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
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			fsb, mult, (fsb * mult));
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	ret = (fsb * mult);
	return ret;
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}

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/* Warning: may get called from smp_call_function_single. */
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unsigned int speedstep_get_frequency(enum speedstep_processor processor)
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{
	switch (processor) {
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	case SPEEDSTEP_CPU_PCORE:
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		return pentium_core_get_frequency();
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	case SPEEDSTEP_CPU_PM:
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		return pentiumM_get_frequency();
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	case SPEEDSTEP_CPU_P4D:
	case SPEEDSTEP_CPU_P4M:
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		return pentium4_get_frequency();
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	case SPEEDSTEP_CPU_PIII_T:
	case SPEEDSTEP_CPU_PIII_C:
	case SPEEDSTEP_CPU_PIII_C_EARLY:
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		return pentium3_get_frequency(processor);
	default:
		return 0;
	};
	return 0;
}
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EXPORT_SYMBOL_GPL(speedstep_get_frequency);
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/*********************************************************************
 *                 DETECT SPEEDSTEP-CAPABLE PROCESSOR                *
 *********************************************************************/

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/* Keep in sync with the x86_cpu_id tables in the different modules */
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unsigned int speedstep_detect_processor(void)
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{
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	struct cpuinfo_x86 *c = &cpu_data(0);
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	u32 ebx, msr_lo, msr_hi;
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	pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model);
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	if ((c->x86_vendor != X86_VENDOR_INTEL) ||
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	    ((c->x86 != 6) && (c->x86 != 0xF)))
		return 0;

	if (c->x86 == 0xF) {
		/* Intel Mobile Pentium 4-M
		 * or Intel Mobile Pentium 4 with 533 MHz FSB */
		if (c->x86_model != 2)
			return 0;

		ebx = cpuid_ebx(0x00000001);
		ebx &= 0x000000FF;

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		pr_debug("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
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		switch (c->x86_mask) {
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		case 4:
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			/*
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			 * B-stepping [M-P4-M]
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			 * sample has ebx = 0x0f, production has 0x0e.
			 */
			if ((ebx == 0x0e) || (ebx == 0x0f))
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				return SPEEDSTEP_CPU_P4M;
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			break;
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		case 7:
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			/*
			 * C-stepping [M-P4-M]
			 * needs to have ebx=0x0e, else it's a celeron:
			 * cf. 25130917.pdf / page 7, footnote 5 even
			 * though 25072120.pdf / page 7 doesn't say
			 * samples are only of B-stepping...
			 */
			if (ebx == 0x0e)
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				return SPEEDSTEP_CPU_P4M;
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			break;
		case 9:
			/*
			 * D-stepping [M-P4-M or M-P4/533]
			 *
			 * this is totally strange: CPUID 0x0F29 is
			 * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
			 * The latter need to be sorted out as they don't
			 * support speedstep.
			 * Celerons with CPUID 0x0F29 may have either
			 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
			 * specific.
			 * M-P4-Ms may have either ebx=0xe or 0xf [see above]
			 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
			 * also, M-P4M HTs have ebx=0x8, too
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			 * For now, they are distinguished by the model_id
			 * string
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			 */
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			if ((ebx == 0x0e) ||
				(strstr(c->x86_model_id,
				    "Mobile Intel(R) Pentium(R) 4") != NULL))
				return SPEEDSTEP_CPU_P4M;
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			break;
		default:
			break;
		}
		return 0;
	}

	switch (c->x86_model) {
	case 0x0B: /* Intel PIII [Tualatin] */
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		/* cpuid_ebx(1) is 0x04 for desktop PIII,
		 * 0x06 for mobile PIII-M */
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		ebx = cpuid_ebx(0x00000001);
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		pr_debug("ebx is %x\n", ebx);
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		ebx &= 0x000000FF;

		if (ebx != 0x06)
			return 0;

		/* So far all PIII-M processors support SpeedStep. See
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		 * Intel's 24540640.pdf of June 2003
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		 */
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		return SPEEDSTEP_CPU_PIII_T;
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	case 0x08: /* Intel PIII [Coppermine] */

		/* all mobile PIII Coppermines have FSB 100 MHz
		 * ==> sort out a few desktop PIIIs. */
		rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
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		pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
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				msr_lo, msr_hi);
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		msr_lo &= 0x00c0000;
		if (msr_lo != 0x0080000)
			return 0;

		/*
		 * If the processor is a mobile version,
		 * platform ID has bit 50 set
		 * it has SpeedStep technology if either
		 * bit 56 or 57 is set
		 */
		rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
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		pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
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				msr_lo, msr_hi);
		if ((msr_hi & (1<<18)) &&
		    (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
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			if (c->x86_mask == 0x01) {
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				pr_debug("early PIII version\n");
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				return SPEEDSTEP_CPU_PIII_C_EARLY;
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			} else
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				return SPEEDSTEP_CPU_PIII_C;
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		}
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		/* fall through */
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	default:
		return 0;
	}
}
EXPORT_SYMBOL_GPL(speedstep_detect_processor);


/*********************************************************************
 *                     DETECT SPEEDSTEP SPEEDS                       *
 *********************************************************************/

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unsigned int speedstep_get_freqs(enum speedstep_processor processor,
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				  unsigned int *low_speed,
				  unsigned int *high_speed,
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				  unsigned int *transition_latency,
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				  void (*set_state) (unsigned int state))
{
	unsigned int prev_speed;
	unsigned int ret = 0;
	unsigned long flags;
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	ktime_t tv1, tv2;
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	if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
		return -EINVAL;

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	pr_debug("trying to determine both speeds\n");
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	/* get current speed */
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	prev_speed = speedstep_get_frequency(processor);
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	if (!prev_speed)
		return -EIO;

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	pr_debug("previous speed is %u\n", prev_speed);
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	preempt_disable();
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	local_irq_save(flags);

	/* switch to low state */
	set_state(SPEEDSTEP_LOW);
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	*low_speed = speedstep_get_frequency(processor);
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	if (!*low_speed) {
		ret = -EIO;
		goto out;
	}

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	pr_debug("low speed is %u\n", *low_speed);
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	/* start latency measurement */
	if (transition_latency)
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		tv1 = ktime_get();
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	/* switch to high state */
	set_state(SPEEDSTEP_HIGH);
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	/* end latency measurement */
	if (transition_latency)
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		tv2 = ktime_get();
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	*high_speed = speedstep_get_frequency(processor);
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	if (!*high_speed) {
		ret = -EIO;
		goto out;
	}

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	pr_debug("high speed is %u\n", *high_speed);
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	if (*low_speed == *high_speed) {
		ret = -ENODEV;
		goto out;
	}

	/* switch to previous state, if necessary */
	if (*high_speed != prev_speed)
		set_state(SPEEDSTEP_LOW);

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	if (transition_latency) {
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		*transition_latency = ktime_to_us(ktime_sub(tv2, tv1));
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		pr_debug("transition latency is %u uSec\n", *transition_latency);
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		/* convert uSec to nSec and add 20% for safety reasons */
		*transition_latency *= 1200;

		/* check if the latency measurement is too high or too low
		 * and set it to a safe value (500uSec) in that case
		 */
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		if (*transition_latency > 10000000 ||
		    *transition_latency < 50000) {
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			pr_warn("frequency transition measured seems out of range (%u nSec), falling back to a safe one of %u nSec\n",
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				*transition_latency, 500000);
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			*transition_latency = 500000;
		}
	}

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out:
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	local_irq_restore(flags);
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	preempt_enable();

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	return ret;
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}
EXPORT_SYMBOL_GPL(speedstep_get_freqs);

#ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
module_param(relaxed_check, int, 0444);
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MODULE_PARM_DESC(relaxed_check,
		"Don't do all checks for speedstep capability.");
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#endif

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MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
MODULE_LICENSE("GPL");