Commit e7309c26 authored by Suman Anna's avatar Suman Anna Committed by Tony Lindgren

bus: omap_l3_noc: Fix master id address decoding for OMAP5

The L3 Error handling on OMAP5 for the most part is very similar
to that of OMAP4, and had leveraged common data structures and
register layout definitions so far. Upon closer inspection, there
are a few minor differences causing an incorrect decoding and
reporting of the master NIU upon an error:

  1. The L3_TARG_STDERRLOG_MSTADDR.STDERRLOG_MSTADDR occupies
     11 bits on OMAP5 as against 8 bits on OMAP4, with the master
     NIU connID encoded in the 6 MSBs of the STDERRLOG_MSTADDR
     field.
  2. The CLK3 FlagMux component has 1 input source on OMAP4 and 3
     input sources on OMAP5. The common DEBUGSS source is at a
     different input on each SoC.

Fix the above issues by using a OMAP5-specific compatible property
and using SoC-specific data where there are differences.
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Acked-by: default avatarNishanth Menon <nm@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 4adf82c3
......@@ -6,6 +6,7 @@ provided by Arteris.
Required properties:
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
Should be "ti,omap4-l3-noc" for OMAP4 family
Should be "ti,omap5-l3-noc" for OMAP5 family
Should be "ti,dra7-l3-noc" for DRA7 family
Should be "ti,am4372-l3-noc" for AM43 family
- reg: Contains L3 register address range for each noc domain.
......
......@@ -128,7 +128,7 @@
* hierarchy.
*/
ocp {
compatible = "ti,omap4-l3-noc", "simple-bus";
compatible = "ti,omap5-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
......
/*
* OMAP L3 Interconnect error handling driver
*
* Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Sricharan <r.sricharan@ti.com>
*
......@@ -233,7 +233,8 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
}
static const struct of_device_id l3_noc_match[] = {
{.compatible = "ti,omap4-l3-noc", .data = &omap_l3_data},
{.compatible = "ti,omap4-l3-noc", .data = &omap4_l3_data},
{.compatible = "ti,omap5-l3-noc", .data = &omap5_l3_data},
{.compatible = "ti,dra7-l3-noc", .data = &dra_l3_data},
{.compatible = "ti,am4372-l3-noc", .data = &am4372_l3_data},
{},
......
/*
* OMAP L3 Interconnect error handling driver header
*
* Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* sricharan <r.sricharan@ti.com>
*
......@@ -175,16 +175,14 @@ static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
};
static struct l3_target_data omap_l3_target_data_clk3[] = {
{0x0100, "EMUSS",},
{0x0300, "DEBUG SOURCE",},
{0x0, "HOST CLK3",},
static struct l3_target_data omap4_l3_target_data_clk3[] = {
{0x0100, "DEBUGSS",},
};
static struct l3_flagmux_data omap_l3_flagmux_clk3 = {
static struct l3_flagmux_data omap4_l3_flagmux_clk3 = {
.offset = 0x0200,
.l3_targ = omap_l3_target_data_clk3,
.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3),
.l3_targ = omap4_l3_target_data_clk3,
.num_targ_data = ARRAY_SIZE(omap4_l3_target_data_clk3),
};
static struct l3_masters_data omap_l3_masters[] = {
......@@ -215,21 +213,49 @@ static struct l3_masters_data omap_l3_masters[] = {
{ 0x32, "USBHOSTFS"}
};
static struct l3_flagmux_data *omap_l3_flagmux[] = {
static struct l3_flagmux_data *omap4_l3_flagmux[] = {
&omap_l3_flagmux_clk1,
&omap_l3_flagmux_clk2,
&omap_l3_flagmux_clk3,
&omap4_l3_flagmux_clk3,
};
static const struct omap_l3 omap_l3_data = {
.l3_flagmux = omap_l3_flagmux,
.num_modules = ARRAY_SIZE(omap_l3_flagmux),
static const struct omap_l3 omap4_l3_data = {
.l3_flagmux = omap4_l3_flagmux,
.num_modules = ARRAY_SIZE(omap4_l3_flagmux),
.l3_masters = omap_l3_masters,
.num_masters = ARRAY_SIZE(omap_l3_masters),
/* The 6 MSBs of register field used to distinguish initiator */
.mst_addr_mask = 0xFC,
};
/* OMAP5 data */
static struct l3_target_data omap5_l3_target_data_clk3[] = {
{0x0100, "L3INSTR",},
{0x0300, "DEBUGSS",},
{0x0, "HOSTCLK3",},
};
static struct l3_flagmux_data omap5_l3_flagmux_clk3 = {
.offset = 0x0200,
.l3_targ = omap5_l3_target_data_clk3,
.num_targ_data = ARRAY_SIZE(omap5_l3_target_data_clk3),
};
static struct l3_flagmux_data *omap5_l3_flagmux[] = {
&omap_l3_flagmux_clk1,
&omap_l3_flagmux_clk2,
&omap5_l3_flagmux_clk3,
};
static const struct omap_l3 omap5_l3_data = {
.l3_flagmux = omap5_l3_flagmux,
.num_modules = ARRAY_SIZE(omap5_l3_flagmux),
.l3_masters = omap_l3_masters,
.num_masters = ARRAY_SIZE(omap_l3_masters),
/* The 6 MSBs of register field used to distinguish initiator */
.mst_addr_mask = 0x7E0,
};
/* DRA7 data */
static struct l3_target_data dra_l3_target_data_clk1[] = {
{0x2a00, "AES1",},
......
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