amplc_pci230.c 81.3 KB
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/*
 * comedi/drivers/amplc_pci230.c
 * Driver for Amplicon PCI230 and PCI260 Multifunction I/O boards.
 *
 * Copyright (C) 2001 Allan Willcox <allanwillcox@ozemail.com.au>
 *
 * COMEDI - Linux Control and Measurement Device Interface
 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
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/*
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 * Driver: amplc_pci230
 * Description: Amplicon PCI230, PCI260 Multifunction I/O boards
 * Author: Allan Willcox <allanwillcox@ozemail.com.au>,
 *   Steve D Sharples <steve.sharples@nottingham.ac.uk>,
 *   Ian Abbott <abbotti@mev.co.uk>
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 * Updated: Mon, 01 Sep 2014 10:09:16 +0000
 * Devices: [Amplicon] PCI230 (amplc_pci230), PCI230+, PCI260, PCI260+
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 * Status: works
 *
 * Configuration options:
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 *   none
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 *
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 * Manual configuration of PCI cards is not supported; they are configured
 * automatically.
 *
 * The PCI230+ and PCI260+ have the same PCI device IDs as the PCI230 and
 * PCI260, but can be distinguished by the the size of the PCI regions.  A
 * card will be configured as a "+" model if detected as such.
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 *
 * Subdevices:
 *
 *                 PCI230(+)    PCI260(+)
 *                 ---------    ---------
 *   Subdevices       3            1
 *         0          AI           AI
 *         1          AO
 *         2          DIO
 *
 * AI Subdevice:
 *
 *   The AI subdevice has 16 single-ended channels or 8 differential
 *   channels.
 *
 *   The PCI230 and PCI260 cards have 12-bit resolution.  The PCI230+ and
 *   PCI260+ cards have 16-bit resolution.
 *
 *   For differential mode, use inputs 2N and 2N+1 for channel N (e.g. use
 *   inputs 14 and 15 for channel 7).  If the card is physically a PCI230
 *   or PCI260 then it actually uses a "pseudo-differential" mode where the
 *   inputs are sampled a few microseconds apart.  The PCI230+ and PCI260+
 *   use true differential sampling.  Another difference is that if the
 *   card is physically a PCI230 or PCI260, the inverting input is 2N,
 *   whereas for a PCI230+ or PCI260+ the inverting input is 2N+1.  So if a
 *   PCI230 is physically replaced by a PCI230+ (or a PCI260 with a
 *   PCI260+) and differential mode is used, the differential inputs need
 *   to be physically swapped on the connector.
 *
 *   The following input ranges are supported:
 *
 *     0 => [-10, +10] V
 *     1 => [-5, +5] V
 *     2 => [-2.5, +2.5] V
 *     3 => [-1.25, +1.25] V
 *     4 => [0, 10] V
 *     5 => [0, 5] V
 *     6 => [0, 2.5] V
 *
 * AI Commands:
 *
 *   +=========+==============+===========+============+==========+
 *   |start_src|scan_begin_src|convert_src|scan_end_src| stop_src |
 *   +=========+==============+===========+============+==========+
 *   |TRIG_NOW | TRIG_FOLLOW  |TRIG_TIMER | TRIG_COUNT |TRIG_NONE |
 *   |TRIG_INT |              |TRIG_EXT(3)|            |TRIG_COUNT|
 *   |         |              |TRIG_INT   |            |          |
 *   |         |--------------|-----------|            |          |
 *   |         | TRIG_TIMER(1)|TRIG_TIMER |            |          |
 *   |         | TRIG_EXT(2)  |           |            |          |
 *   |         | TRIG_INT     |           |            |          |
 *   +---------+--------------+-----------+------------+----------+
 *
 *   Note 1: If AI command and AO command are used simultaneously, only
 *           one may have scan_begin_src == TRIG_TIMER.
 *
 *   Note 2: For PCI230 and PCI230+, scan_begin_src == TRIG_EXT uses
 *           DIO channel 16 (pin 49) which will need to be configured as
 *           a digital input.  For PCI260+, the EXTTRIG/EXTCONVCLK input
 *           (pin 17) is used instead.  For PCI230, scan_begin_src ==
 *           TRIG_EXT is not supported.  The trigger is a rising edge
 *           on the input.
 *
 *   Note 3: For convert_src == TRIG_EXT, the EXTTRIG/EXTCONVCLK input
 *           (pin 25 on PCI230(+), pin 17 on PCI260(+)) is used.  The
 *           convert_arg value is interpreted as follows:
 *
 *             convert_arg == (CR_EDGE | 0) => rising edge
 *             convert_arg == (CR_EDGE | CR_INVERT | 0) => falling edge
 *             convert_arg == 0 => falling edge (backwards compatibility)
 *             convert_arg == 1 => rising edge (backwards compatibility)
 *
 *   All entries in the channel list must use the same analogue reference.
 *   If the analogue reference is not AREF_DIFF (not differential) each
 *   pair of channel numbers (0 and 1, 2 and 3, etc.) must use the same
 *   input range.  The input ranges used in the sequence must be all
 *   bipolar (ranges 0 to 3) or all unipolar (ranges 4 to 6).  The channel
 *   sequence must consist of 1 or more identical subsequences.  Within the
 *   subsequence, channels must be in ascending order with no repeated
 *   channels.  For example, the following sequences are valid: 0 1 2 3
 *   (single valid subsequence), 0 2 3 5 0 2 3 5 (repeated valid
 *   subsequence), 1 1 1 1 (repeated valid subsequence).  The following
 *   sequences are invalid: 0 3 2 1 (invalid subsequence), 0 2 3 5 0 2 3
 *   (incompletely repeated subsequence).  Some versions of the PCI230+ and
 *   PCI260+ have a bug that requires a subsequence longer than one entry
 *   long to include channel 0.
 *
 * AO Subdevice:
 *
 *   The AO subdevice has 2 channels with 12-bit resolution.
 *   The following output ranges are supported:
 *     0 => [0, 10] V
 *     1 => [-10, +10] V
 *
 * AO Commands:
 *
 *   +=========+==============+===========+============+==========+
 *   |start_src|scan_begin_src|convert_src|scan_end_src| stop_src |
 *   +=========+==============+===========+============+==========+
 *   |TRIG_INT | TRIG_TIMER(1)| TRIG_NOW  | TRIG_COUNT |TRIG_NONE |
 *   |         | TRIG_EXT(2)  |           |            |TRIG_COUNT|
 *   |         | TRIG_INT     |           |            |          |
 *   +---------+--------------+-----------+------------+----------+
 *
 *   Note 1: If AI command and AO command are used simultaneously, only
 *           one may have scan_begin_src == TRIG_TIMER.
 *
 *   Note 2: scan_begin_src == TRIG_EXT is only supported if the card is
 *           configured as a PCI230+ and is only supported on later
 *           versions of the card.  As a card configured as a PCI230+ is
 *           not guaranteed to support external triggering, please consider
 *           this support to be a bonus.  It uses the EXTTRIG/ EXTCONVCLK
 *           input (PCI230+ pin 25).  Triggering will be on the rising edge
 *           unless the CR_INVERT flag is set in scan_begin_arg.
 *
 *   The channels in the channel sequence must be in ascending order with
 *   no repeats.  All entries in the channel sequence must use the same
 *   output range.
 *
 * DIO Subdevice:
 *
 *   The DIO subdevice is a 8255 chip providing 24 DIO channels.  The DIO
 *   channels are configurable as inputs or outputs in four groups:
 *
 *     Port A  - channels  0 to  7
 *     Port B  - channels  8 to 15
 *     Port CL - channels 16 to 19
 *     Port CH - channels 20 to 23
 *
 *   Only mode 0 of the 8255 chip is supported.
 *
 *   Bit 0 of port C (DIO channel 16) is also used as an external scan
 *   trigger input for AI commands on PCI230 and PCI230+, so would need to
 *   be configured as an input to use it for that purpose.
 */

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/*
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 * Extra triggered scan functionality, interrupt bug-fix added by Steve
 * Sharples.  Support for PCI230+/260+, more triggered scan functionality,
 * and workarounds for (or detection of) various hardware problems added
 * by Ian Abbott.
 */
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include "../comedidev.h"

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#include "comedi_fc.h"
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#include "8253.h"
#include "8255.h"

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/*
 * PCI230 PCI configuration register information
 */
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#define PCI_DEVICE_ID_PCI230 0x0000
#define PCI_DEVICE_ID_PCI260 0x0006

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/*
 * PCI230 i/o space 1 registers.
 */
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#define PCI230_PPI_X_BASE	0x00	/* User PPI (82C55) base */
#define PCI230_PPI_X_A		0x00	/* User PPI (82C55) port A */
#define PCI230_PPI_X_B		0x01	/* User PPI (82C55) port B */
#define PCI230_PPI_X_C		0x02	/* User PPI (82C55) port C */
#define PCI230_PPI_X_CMD	0x03	/* User PPI (82C55) control word */
#define PCI230_Z2_CT_BASE	0x14	/* 82C54 counter/timer base */
#define PCI230_Z2_CT0		0x14	/* 82C54 counter/timer 0 */
#define PCI230_Z2_CT1		0x15	/* 82C54 counter/timer 1 */
#define PCI230_Z2_CT2		0x16	/* 82C54 counter/timer 2 */
#define PCI230_Z2_CTC		0x17	/* 82C54 counter/timer control word */
#define PCI230_ZCLK_SCE		0x1A	/* Group Z Clock Configuration */
#define PCI230_ZGAT_SCE		0x1D	/* Group Z Gate Configuration */
#define PCI230_INT_SCE		0x1E	/* Interrupt source mask (w) */
#define PCI230_INT_STAT		0x1E	/* Interrupt status (r) */

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/*
 * PCI230 i/o space 2 registers.
 */
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#define PCI230_DACCON		0x00	/* DAC control */
#define PCI230_DACOUT1		0x02	/* DAC channel 0 (w) */
#define PCI230_DACOUT2		0x04	/* DAC channel 1 (w) (not FIFO mode) */
#define PCI230_ADCDATA		0x08	/* ADC data (r) */
#define PCI230_ADCSWTRIG	0x08	/* ADC software trigger (w) */
#define PCI230_ADCCON		0x0A	/* ADC control */
#define PCI230_ADCEN		0x0C	/* ADC channel enable bits */
#define PCI230_ADCG		0x0E	/* ADC gain control bits */
/* PCI230+ i/o space 2 additional registers. */
#define PCI230P_ADCTRIG		0x10	/* ADC start acquisition trigger */
#define PCI230P_ADCTH		0x12	/* ADC analog trigger threshold */
#define PCI230P_ADCFFTH		0x14	/* ADC FIFO interrupt threshold */
#define PCI230P_ADCFFLEV	0x16	/* ADC FIFO level (r) */
#define PCI230P_ADCPTSC		0x18	/* ADC pre-trigger sample count (r) */
#define PCI230P_ADCHYST		0x1A	/* ADC analog trigger hysteresys */
#define PCI230P_EXTFUNC		0x1C	/* Extended functions */
#define PCI230P_HWVER		0x1E	/* Hardware version (r) */
/* PCI230+ hardware version 2 onwards. */
#define PCI230P2_DACDATA	0x02	/* DAC data (FIFO mode) (w) */
#define PCI230P2_DACSWTRIG	0x02	/* DAC soft trigger (FIFO mode) (r) */
#define PCI230P2_DACEN		0x06	/* DAC channel enable (FIFO mode) */

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/*
 * DACCON read-write values.
 */
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#define PCI230_DAC_OR_UNI		(0 << 0) /* Output range unipolar */
#define PCI230_DAC_OR_BIP		(1 << 0) /* Output range bipolar */
#define PCI230_DAC_OR_MASK		(1 << 0)
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/*
 * The following applies only if DAC FIFO support is enabled in the EXTFUNC
 * register (and only for PCI230+ hardware version 2 onwards).
 */
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#define PCI230P2_DAC_FIFO_EN		(1 << 8) /* FIFO enable */
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/*
 * The following apply only if the DAC FIFO is enabled (and only for PCI230+
 * hardware version 2 onwards).
 */
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#define PCI230P2_DAC_TRIG_NONE		(0 << 2) /* No trigger */
#define PCI230P2_DAC_TRIG_SW		(1 << 2) /* Software trigger trigger */
#define PCI230P2_DAC_TRIG_EXTP		(2 << 2) /* EXTTRIG +ve edge trigger */
#define PCI230P2_DAC_TRIG_EXTN		(3 << 2) /* EXTTRIG -ve edge trigger */
#define PCI230P2_DAC_TRIG_Z2CT0		(4 << 2) /* CT0-OUT +ve edge trigger */
#define PCI230P2_DAC_TRIG_Z2CT1		(5 << 2) /* CT1-OUT +ve edge trigger */
#define PCI230P2_DAC_TRIG_Z2CT2		(6 << 2) /* CT2-OUT +ve edge trigger */
#define PCI230P2_DAC_TRIG_MASK		(7 << 2)
#define PCI230P2_DAC_FIFO_WRAP		(1 << 7) /* FIFO wraparound mode */
#define PCI230P2_DAC_INT_FIFO_EMPTY	(0 << 9) /* FIFO interrupt empty */
#define PCI230P2_DAC_INT_FIFO_NEMPTY	(1 << 9)
#define PCI230P2_DAC_INT_FIFO_NHALF	(2 << 9) /* FIFO intr not half full */
#define PCI230P2_DAC_INT_FIFO_HALF	(3 << 9)
#define PCI230P2_DAC_INT_FIFO_NFULL	(4 << 9) /* FIFO interrupt not full */
#define PCI230P2_DAC_INT_FIFO_FULL	(5 << 9)
#define PCI230P2_DAC_INT_FIFO_MASK	(7 << 9)
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/*
 * DACCON read-only values.
 */
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#define PCI230_DAC_BUSY			(1 << 1) /* DAC busy. */
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/*
 * The following apply only if the DAC FIFO is enabled (and only for PCI230+
 * hardware version 2 onwards).
 */
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#define PCI230P2_DAC_FIFO_UNDERRUN_LATCHED	(1 << 5) /* Underrun error */
#define PCI230P2_DAC_FIFO_EMPTY		(1 << 13) /* FIFO empty */
#define PCI230P2_DAC_FIFO_FULL		(1 << 14) /* FIFO full */
#define PCI230P2_DAC_FIFO_HALF		(1 << 15) /* FIFO half full */
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/*
 * DACCON write-only, transient values.
 */
/*
 * The following apply only if the DAC FIFO is enabled (and only for PCI230+
 * hardware version 2 onwards).
 */
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#define PCI230P2_DAC_FIFO_UNDERRUN_CLEAR	(1 << 5) /* Clear underrun */
#define PCI230P2_DAC_FIFO_RESET		(1 << 12) /* FIFO reset */
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/*
 * PCI230+ hardware version 2 DAC FIFO levels.
 */
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#define PCI230P2_DAC_FIFOLEVEL_HALF	512
#define PCI230P2_DAC_FIFOLEVEL_FULL	1024
/* Free space in DAC FIFO. */
#define PCI230P2_DAC_FIFOROOM_EMPTY		PCI230P2_DAC_FIFOLEVEL_FULL
#define PCI230P2_DAC_FIFOROOM_ONETOHALF		\
	(PCI230P2_DAC_FIFOLEVEL_FULL - PCI230P2_DAC_FIFOLEVEL_HALF)
#define PCI230P2_DAC_FIFOROOM_HALFTOFULL	1
#define PCI230P2_DAC_FIFOROOM_FULL		0

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/*
 * ADCCON read/write values.
 */
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#define PCI230_ADC_TRIG_NONE		(0 << 0) /* No trigger */
#define PCI230_ADC_TRIG_SW		(1 << 0) /* Software trigger trigger */
#define PCI230_ADC_TRIG_EXTP		(2 << 0) /* EXTTRIG +ve edge trigger */
#define PCI230_ADC_TRIG_EXTN		(3 << 0) /* EXTTRIG -ve edge trigger */
#define PCI230_ADC_TRIG_Z2CT0		(4 << 0) /* CT0-OUT +ve edge trigger */
#define PCI230_ADC_TRIG_Z2CT1		(5 << 0) /* CT1-OUT +ve edge trigger */
#define PCI230_ADC_TRIG_Z2CT2		(6 << 0) /* CT2-OUT +ve edge trigger */
#define PCI230_ADC_TRIG_MASK		(7 << 0)
#define PCI230_ADC_IR_UNI		(0 << 3) /* Input range unipolar */
#define PCI230_ADC_IR_BIP		(1 << 3) /* Input range bipolar */
#define PCI230_ADC_IR_MASK		(1 << 3)
#define PCI230_ADC_IM_SE		(0 << 4) /* Input mode single ended */
#define PCI230_ADC_IM_DIF		(1 << 4) /* Input mode differential */
#define PCI230_ADC_IM_MASK		(1 << 4)
#define PCI230_ADC_FIFO_EN		(1 << 8) /* FIFO enable */
#define PCI230_ADC_INT_FIFO_EMPTY	(0 << 9)
#define PCI230_ADC_INT_FIFO_NEMPTY	(1 << 9) /* FIFO interrupt not empty */
#define PCI230_ADC_INT_FIFO_NHALF	(2 << 9)
#define PCI230_ADC_INT_FIFO_HALF	(3 << 9) /* FIFO interrupt half full */
#define PCI230_ADC_INT_FIFO_NFULL	(4 << 9)
#define PCI230_ADC_INT_FIFO_FULL	(5 << 9) /* FIFO interrupt full */
#define PCI230P_ADC_INT_FIFO_THRESH	(7 << 9) /* FIFO interrupt threshold */
#define PCI230_ADC_INT_FIFO_MASK	(7 << 9)
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/*
 * ADCCON write-only, transient values.
 */
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#define PCI230_ADC_FIFO_RESET		(1 << 12) /* FIFO reset */
#define PCI230_ADC_GLOB_RESET		(1 << 13) /* Global reset */
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/*
 * ADCCON read-only values.
 */
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#define PCI230_ADC_BUSY			(1 << 15) /* ADC busy */
#define PCI230_ADC_FIFO_EMPTY		(1 << 12) /* FIFO empty */
#define PCI230_ADC_FIFO_FULL		(1 << 13) /* FIFO full */
#define PCI230_ADC_FIFO_HALF		(1 << 14) /* FIFO half full */
#define PCI230_ADC_FIFO_FULL_LATCHED	(1 << 5)  /* FIFO overrun occurred */
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/*
 * PCI230 ADC FIFO levels.
 */
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#define PCI230_ADC_FIFOLEVEL_HALFFULL	2049	/* Value for FIFO half full */
#define PCI230_ADC_FIFOLEVEL_FULL	4096	/* FIFO size */

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/*
 * PCI230+ EXTFUNC values.
 */
/* Route EXTTRIG pin to external gate inputs. */
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#define PCI230P_EXTFUNC_GAT_EXTTRIG	(1 << 0)
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/* PCI230+ hardware version 2 values. */
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/* Allow DAC FIFO to be enabled. */
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#define PCI230P2_EXTFUNC_DACFIFO	(1 << 1)
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/*
 * Counter/timer clock input configuration sources.
 */
#define CLK_CLK		0	/* reserved (channel-specific clock) */
#define CLK_10MHZ	1	/* internal 10 MHz clock */
#define CLK_1MHZ	2	/* internal 1 MHz clock */
#define CLK_100KHZ	3	/* internal 100 kHz clock */
#define CLK_10KHZ	4	/* internal 10 kHz clock */
#define CLK_1KHZ	5	/* internal 1 kHz clock */
#define CLK_OUTNM1	6	/* output of channel-1 modulo total */
#define CLK_EXT		7	/* external clock */
/* Macro to construct clock input configuration register value. */
#define CLK_CONFIG(chan, src)	((((chan) & 3) << 3) | ((src) & 7))
/* Timebases in ns. */
#define TIMEBASE_10MHZ		100
#define TIMEBASE_1MHZ		1000
#define TIMEBASE_100KHZ		10000
#define TIMEBASE_10KHZ		100000
#define TIMEBASE_1KHZ		1000000

/*
 * Counter/timer gate input configuration sources.
 */
#define GAT_VCC		0	/* VCC (i.e. enabled) */
#define GAT_GND		1	/* GND (i.e. disabled) */
#define GAT_EXT		2	/* external gate input (PPCn on PCI230) */
#define GAT_NOUTNM2	3	/* inverted output of channel-2 modulo total */
/* Macro to construct gate input configuration register value. */
#define GAT_CONFIG(chan, src)	((((chan) & 3) << 3) | ((src) & 7))

/*
 * Summary of CLK_OUTNM1 and GAT_NOUTNM2 connections for PCI230 and PCI260:
 *
 *              Channel's       Channel's
 *              clock input     gate input
 * Channel      CLK_OUTNM1      GAT_NOUTNM2
 * -------      ----------      -----------
 * Z2-CT0       Z2-CT2-OUT      /Z2-CT1-OUT
 * Z2-CT1       Z2-CT0-OUT      /Z2-CT2-OUT
 * Z2-CT2       Z2-CT1-OUT      /Z2-CT0-OUT
 */

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/*
 * Interrupt enables/status register values.
 */
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#define PCI230_INT_DISABLE		0
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#define PCI230_INT_PPI_C0		(1 << 0)
#define PCI230_INT_PPI_C3		(1 << 1)
#define PCI230_INT_ADC			(1 << 2)
#define PCI230_INT_ZCLK_CT1		(1 << 5)
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/* For PCI230+ hardware version 2 when DAC FIFO enabled. */
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#define PCI230P2_INT_DAC		(1 << 4)
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/*
 * (Potentially) shared resources and their owners
 */
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enum {
	RES_Z2CT0,		/* Z2-CT0 */
	RES_Z2CT1,		/* Z2-CT1 */
	RES_Z2CT2,		/* Z2-CT2 */
	NUM_RESOURCES		/* Number of (potentially) shared resources. */
};

enum {
	OWNER_NONE,		/* Not owned */
	OWNER_AICMD,		/* Owned by AI command */
	OWNER_AOCMD		/* Owned by AO command */
};

/*
 * Handy macros.
 */

/* Combine old and new bits. */
#define COMBINE(old, new, mask)	(((old) & ~(mask)) | ((new) & (mask)))

/* Current CPU.  XXX should this be hard_smp_processor_id()? */
#define THISCPU		smp_processor_id()

/* State flags for atomic bit operations */
#define AI_CMD_STARTED	0
#define AO_CMD_STARTED	1

/*
 * Board descriptions for the two boards supported.
 */

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struct pci230_board {
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	const char *name;
	unsigned short id;
	int ai_bits;
	int ao_bits;
	int have_dio;
	unsigned int min_hwver;	/* Minimum hardware version supported. */
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};
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static const struct pci230_board pci230_boards[] = {
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	{
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		.name		= "pci230+",
		.id		= PCI_DEVICE_ID_PCI230,
		.ai_bits	= 16,
		.ao_bits	= 12,
		.have_dio	= 1,
		.min_hwver	= 1,
	},
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	{
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		.name		= "pci260+",
		.id		= PCI_DEVICE_ID_PCI260,
		.ai_bits	= 16,
		.min_hwver	= 1,
	},
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	{
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		.name		= "pci230",
		.id		= PCI_DEVICE_ID_PCI230,
		.ai_bits	= 12,
		.ao_bits	= 12,
		.have_dio	= 1,
	},
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	{
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		.name		= "pci260",
		.id		= PCI_DEVICE_ID_PCI260,
		.ai_bits	= 12,
	},
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};

struct pci230_private {
	spinlock_t isr_spinlock;	/* Interrupt spin lock */
	spinlock_t res_spinlock;	/* Shared resources spin lock */
	spinlock_t ai_stop_spinlock;	/* Spin lock for stopping AI command */
	spinlock_t ao_stop_spinlock;	/* Spin lock for stopping AO command */
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	unsigned long daqio;		/* PCI230's DAQ I/O space */
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	unsigned long state;		/* State flags */
	unsigned int ai_scan_count;	/* Number of AI scans remaining */
	unsigned int ai_scan_pos;	/* Current position within AI scan */
	unsigned int ao_scan_count;	/* Number of AO scans remaining.  */
	int intr_cpuid;			/* ID of CPU running ISR */
	unsigned short hwver;		/* Hardware version (for '+' models) */
	unsigned short adccon;		/* ADCCON register value */
	unsigned short daccon;		/* DACCON register value */
	unsigned short adcfifothresh;	/* ADC FIFO threshold (PCI230+/260+) */
	unsigned short adcg;		/* ADCG register value */
	unsigned char int_en;		/* Interrupt enable bits */
	unsigned char ai_bipolar;	/* Flag AI range is bipolar */
	unsigned char ao_bipolar;	/* Flag AO range is bipolar */
	unsigned char ier;		/* Copy of interrupt enable register */
	unsigned char intr_running;	/* Flag set in interrupt routine */
	unsigned char res_owner[NUM_RESOURCES]; /* Shared resource owners */
514 515 516 517 518 519 520 521 522 523 524 525
};

/* PCI230 clock source periods in ns */
static const unsigned int pci230_timebase[8] = {
	[CLK_10MHZ] = TIMEBASE_10MHZ,
	[CLK_1MHZ] = TIMEBASE_1MHZ,
	[CLK_100KHZ] = TIMEBASE_100KHZ,
	[CLK_10KHZ] = TIMEBASE_10KHZ,
	[CLK_1KHZ] = TIMEBASE_1KHZ,
};

/* PCI230 analogue input range table */
526 527 528 529 530 531 532 533 534 535
static const struct comedi_lrange pci230_ai_range = {
	7, {
		BIP_RANGE(10),
		BIP_RANGE(5),
		BIP_RANGE(2.5),
		BIP_RANGE(1.25),
		UNI_RANGE(10),
		UNI_RANGE(5),
		UNI_RANGE(2.5)
	}
536 537 538 539 540 541 542 543 544
};

/* PCI230 analogue gain bits for each input range. */
static const unsigned char pci230_ai_gain[7] = { 0, 1, 2, 3, 1, 2, 3 };

/* PCI230 adccon bipolar flag for each analogue input range. */
static const unsigned char pci230_ai_bipolar[7] = { 1, 1, 1, 1, 0, 0, 0 };

/* PCI230 analogue output range table */
545 546 547 548 549
static const struct comedi_lrange pci230_ao_range = {
	2, {
		UNI_RANGE(10),
		BIP_RANGE(10)
	}
550 551 552 553 554
};

/* PCI230 daccon bipolar flag for each analogue output range. */
static const unsigned char pci230_ao_bipolar[2] = { 0, 1 };

555
static unsigned short pci230_ai_read(struct comedi_device *dev)
556
{
557 558
	const struct pci230_board *thisboard = comedi_board(dev);
	struct pci230_private *devpriv = dev->private;
559
	unsigned short data;
560

561
	/* Read sample. */
562
	data = inw(devpriv->daqio + PCI230_ADCDATA);
563 564 565 566
	/*
	 * PCI230 is 12 bit - stored in upper bits of 16 bit register
	 * (lower four bits reserved for expansion).  PCI230+ is 16 bit AI.
	 */
567 568
	data = data >> (16 - thisboard->ai_bits);

569 570 571 572
	/*
	 * If a bipolar range was specified, mangle it
	 * (twos complement->straight binary).
	 */
573
	if (devpriv->ai_bipolar)
574
		data ^= 1 << (thisboard->ai_bits - 1);
575

576 577 578
	return data;
}

579
static inline unsigned short pci230_ao_mangle_datum(struct comedi_device *dev,
580
						    unsigned short datum)
581
{
582 583 584
	const struct pci230_board *thisboard = comedi_board(dev);
	struct pci230_private *devpriv = dev->private;

585 586 587 588
	/*
	 * If a bipolar range was specified, mangle it
	 * (straight binary->twos complement).
	 */
589
	if (devpriv->ao_bipolar)
590
		datum ^= 1 << (thisboard->ao_bits - 1);
591

592 593 594 595
	/*
	 * PCI230 is 12 bit - stored in upper bits of 16 bit register (lower
	 * four bits reserved for expansion).  PCI230+ is also 12 bit AO.
	 */
596
	datum <<= (16 - thisboard->ao_bits);
597
	return datum;
598 599
}

600
static inline void pci230_ao_write_nofifo(struct comedi_device *dev,
601 602
					  unsigned short datum,
					  unsigned int chan)
603
{
604 605
	struct pci230_private *devpriv = dev->private;

606
	/* Write mangled datum to appropriate DACOUT register. */
607
	outw(pci230_ao_mangle_datum(dev, datum),
608
	     devpriv->daqio + ((chan == 0) ? PCI230_DACOUT1 : PCI230_DACOUT2));
609 610
}

611 612
static inline void pci230_ao_write_fifo(struct comedi_device *dev,
					unsigned short datum, unsigned int chan)
613
{
614 615
	struct pci230_private *devpriv = dev->private;

616 617
	/* Write mangled datum to appropriate DACDATA register. */
	outw(pci230_ao_mangle_datum(dev, datum),
618
	     devpriv->daqio + PCI230P2_DACDATA);
619 620
}

621
static int get_resources(struct comedi_device *dev, unsigned int res_mask,
622
			 unsigned char owner)
623
{
624
	struct pci230_private *devpriv = dev->private;
625 626 627 628 629 630 631 632
	int ok;
	unsigned int i;
	unsigned int b;
	unsigned int claimed;
	unsigned long irqflags;

	ok = 1;
	claimed = 0;
633
	spin_lock_irqsave(&devpriv->res_spinlock, irqflags);
634
	for (b = 1, i = 0; i < NUM_RESOURCES && res_mask; b <<= 1, i++) {
635
		if (res_mask & b) {
636 637 638 639 640
			res_mask &= ~b;
			if (devpriv->res_owner[i] == OWNER_NONE) {
				devpriv->res_owner[i] = owner;
				claimed |= b;
			} else if (devpriv->res_owner[i] != owner) {
641 642
				for (b = 1, i = 0; claimed; b <<= 1, i++) {
					if (claimed & b) {
643 644
						devpriv->res_owner[i] =
						    OWNER_NONE;
645 646 647 648 649 650 651 652
						claimed &= ~b;
					}
				}
				ok = 0;
				break;
			}
		}
	}
653
	spin_unlock_irqrestore(&devpriv->res_spinlock, irqflags);
654 655 656
	return ok;
}

657 658
static inline int get_one_resource(struct comedi_device *dev,
				   unsigned int resource, unsigned char owner)
659
{
660
	return get_resources(dev, 1U << resource, owner);
661 662
}

663
static void put_resources(struct comedi_device *dev, unsigned int res_mask,
664
			  unsigned char owner)
665
{
666
	struct pci230_private *devpriv = dev->private;
667 668 669 670
	unsigned int i;
	unsigned int b;
	unsigned long irqflags;

671
	spin_lock_irqsave(&devpriv->res_spinlock, irqflags);
672
	for (b = 1, i = 0; i < NUM_RESOURCES && res_mask; b <<= 1, i++) {
673
		if (res_mask & b) {
674
			res_mask &= ~b;
675
			if (devpriv->res_owner[i] == owner)
676 677 678
				devpriv->res_owner[i] = OWNER_NONE;
		}
	}
679
	spin_unlock_irqrestore(&devpriv->res_spinlock, irqflags);
680 681
}

682 683
static inline void put_one_resource(struct comedi_device *dev,
				    unsigned int resource, unsigned char owner)
684
{
685
	put_resources(dev, 1U << resource, owner);
686 687
}

688 689
static inline void put_all_resources(struct comedi_device *dev,
				     unsigned char owner)
690 691 692 693
{
	put_resources(dev, (1U << NUM_RESOURCES) - 1, owner);
}

694
static unsigned int divide_ns(uint64_t ns, unsigned int timebase,
695
			      unsigned int flags)
696 697 698 699 700 701
{
	uint64_t div;
	unsigned int rem;

	div = ns;
	rem = do_div(div, timebase);
702
	switch (flags & TRIG_ROUND_MASK) {
703 704 705 706 707 708 709 710 711 712 713 714 715
	default:
	case TRIG_ROUND_NEAREST:
		div += (rem + (timebase / 2)) / timebase;
		break;
	case TRIG_ROUND_DOWN:
		break;
	case TRIG_ROUND_UP:
		div += (rem + timebase - 1) / timebase;
		break;
	}
	return div > UINT_MAX ? UINT_MAX : (unsigned int)div;
}

716 717 718 719
/*
 * Given desired period in ns, returns the required internal clock source
 * and gets the initial count.
 */
720
static unsigned int pci230_choose_clk_count(uint64_t ns, unsigned int *count,
721
					    unsigned int flags)
722 723 724 725
{
	unsigned int clk_src, cnt;

	for (clk_src = CLK_10MHZ;; clk_src++) {
726
		cnt = divide_ns(ns, pci230_timebase[clk_src], flags);
727
		if (cnt <= 65536 || clk_src == CLK_1KHZ)
728 729 730 731 732 733
			break;
	}
	*count = cnt;
	return clk_src;
}

734
static void pci230_ns_to_single_timer(unsigned int *ns, unsigned int flags)
735 736 737 738
{
	unsigned int count;
	unsigned int clk_src;

739
	clk_src = pci230_choose_clk_count(*ns, &count, flags);
740 741 742 743 744
	*ns = count * pci230_timebase[clk_src];
}

static void pci230_ct_setup_ns_mode(struct comedi_device *dev, unsigned int ct,
				    unsigned int mode, uint64_t ns,
745
				    unsigned int flags)
746 747 748 749 750
{
	unsigned int clk_src;
	unsigned int count;

	/* Set mode. */
751
	i8254_set_mode(dev->iobase + PCI230_Z2_CT_BASE, 0, ct, mode);
752
	/* Determine clock source and count. */
753
	clk_src = pci230_choose_clk_count(ns, &count, flags);
754
	/* Program clock source. */
755
	outb(CLK_CONFIG(ct, clk_src), dev->iobase + PCI230_ZCLK_SCE);
756 757 758 759
	/* Set initial count. */
	if (count >= 65536)
		count = 0;

760
	i8254_write(dev->iobase + PCI230_Z2_CT_BASE, 0, ct, count);
761 762 763 764
}

static void pci230_cancel_ct(struct comedi_device *dev, unsigned int ct)
{
765
	i8254_set_mode(dev->iobase + PCI230_Z2_CT_BASE, 0, ct, I8254_MODE1);
766 767 768
	/* Counter ct, 8254 mode 1, initial count not written. */
}

769 770 771 772 773
static int pci230_ai_eoc(struct comedi_device *dev,
			 struct comedi_subdevice *s,
			 struct comedi_insn *insn,
			 unsigned long context)
{
774
	struct pci230_private *devpriv = dev->private;
775 776
	unsigned int status;

777
	status = inw(devpriv->daqio + PCI230_ADCCON);
778 779 780 781 782
	if ((status & PCI230_ADC_FIFO_EMPTY) == 0)
		return 0;
	return -EBUSY;
}

783 784 785
static int pci230_ai_rinsn(struct comedi_device *dev,
			   struct comedi_subdevice *s, struct comedi_insn *insn,
			   unsigned int *data)
786
{
787
	struct pci230_private *devpriv = dev->private;
788
	unsigned int n;
789 790 791
	unsigned int chan, range, aref;
	unsigned int gainshift;
	unsigned short adccon, adcen;
792
	int ret;
793 794 795 796 797 798 799 800

	/* Unpack channel and range. */
	chan = CR_CHAN(insn->chanspec);
	range = CR_RANGE(insn->chanspec);
	aref = CR_AREF(insn->chanspec);
	if (aref == AREF_DIFF) {
		/* Differential. */
		if (chan >= s->n_chan / 2) {
801 802 803
			dev_dbg(dev->class_dev,
				"%s: differential channel number out of range 0 to %u\n",
				__func__, (s->n_chan / 2) - 1);
804 805 806 807
			return -EINVAL;
		}
	}

808 809
	/*
	 * Use Z2-CT2 as a conversion trigger instead of the built-in
810 811 812 813 814 815
	 * software trigger, as otherwise triggering of differential channels
	 * doesn't work properly for some versions of PCI230/260.  Also set
	 * FIFO mode because the ADC busy bit only works for software triggers.
	 */
	adccon = PCI230_ADC_TRIG_Z2CT2 | PCI230_ADC_FIFO_EN;
	/* Set Z2-CT2 output low to avoid any false triggers. */
816
	i8254_set_mode(dev->iobase + PCI230_Z2_CT_BASE, 0, 2, I8254_MODE0);
817 818 819 820 821
	devpriv->ai_bipolar = pci230_ai_bipolar[range];
	if (aref == AREF_DIFF) {
		/* Differential. */
		gainshift = chan * 2;
		if (devpriv->hwver == 0) {
822 823 824 825
			/*
			 * Original PCI230/260 expects both inputs of the
			 * differential channel to be enabled.
			 */
826 827
			adcen = 3 << gainshift;
		} else {
828 829 830 831
			/*
			 * PCI230+/260+ expects only one input of the
			 * differential channel to be enabled.
			 */
832 833 834 835 836 837 838 839 840
			adcen = 1 << gainshift;
		}
		adccon |= PCI230_ADC_IM_DIF;
	} else {
		/* Single ended. */
		adcen = 1 << chan;
		gainshift = chan & ~1;
		adccon |= PCI230_ADC_IM_SE;
	}
841 842
	devpriv->adcg = (devpriv->adcg & ~(3 << gainshift)) |
			(pci230_ai_gain[range] << gainshift);
843
	if (devpriv->ai_bipolar)
844
		adccon |= PCI230_ADC_IR_BIP;
845
	else
846
		adccon |= PCI230_ADC_IR_UNI;
847

848 849 850 851
	/*
	 * Enable only this channel in the scan list - otherwise by default
	 * we'll get one sample from each channel.
	 */
852
	outw(adcen, devpriv->daqio + PCI230_ADCEN);
853 854

	/* Set gain for channel. */
855
	outw(devpriv->adcg, devpriv->daqio + PCI230_ADCG);
856 857 858

	/* Specify uni/bip, se/diff, conversion source, and reset FIFO. */
	devpriv->adccon = adccon;
859
	outw(adccon | PCI230_ADC_FIFO_RESET, devpriv->daqio + PCI230_ADCCON);
860 861 862

	/* Convert n samples */
	for (n = 0; n < insn->n; n++) {
863 864 865 866
		/*
		 * Trigger conversion by toggling Z2-CT2 output
		 * (finish with output high).
		 */
867 868 869 870
		i8254_set_mode(dev->iobase + PCI230_Z2_CT_BASE, 0,
			       2, I8254_MODE0);
		i8254_set_mode(dev->iobase + PCI230_Z2_CT_BASE, 0,
			       2, I8254_MODE1);
871 872

		/* wait for conversion to end */
873
		ret = comedi_timeout(dev, s, insn, pci230_ai_eoc, 0);
874
		if (ret)
875
			return ret;
876 877 878 879 880 881 882 883 884

		/* read data */
		data[n] = pci230_ai_read(dev);
	}

	/* return the number of samples read/written */
	return n;
}

885 886 887 888
static int pci230_ao_insn_write(struct comedi_device *dev,
				struct comedi_subdevice *s,
				struct comedi_insn *insn,
				unsigned int *data)
889
{
890
	struct pci230_private *devpriv = dev->private;
891 892 893
	unsigned int chan = CR_CHAN(insn->chanspec);
	unsigned int range = CR_RANGE(insn->chanspec);
	unsigned int val = s->readback[chan];
894 895
	int i;

896 897 898 899
	/*
	 * Set range - see analogue output range table; 0 => unipolar 10V,
	 * 1 => bipolar +/-10V range scale
	 */
900
	devpriv->ao_bipolar = pci230_ao_bipolar[range];
901
	outw(range, devpriv->daqio + PCI230_DACCON);
902 903

	for (i = 0; i < insn->n; i++) {
904 905
		val = data[i];
		pci230_ao_write_nofifo(dev, val, chan);
906
	}
907
	s->readback[chan] = val;
908

909
	return insn->n;
910 911
}

912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943
static int pci230_ao_check_chanlist(struct comedi_device *dev,
				    struct comedi_subdevice *s,
				    struct comedi_cmd *cmd)
{
	unsigned int prev_chan = CR_CHAN(cmd->chanlist[0]);
	unsigned int range0 = CR_RANGE(cmd->chanlist[0]);
	int i;

	for (i = 1; i < cmd->chanlist_len; i++) {
		unsigned int chan = CR_CHAN(cmd->chanlist[i]);
		unsigned int range = CR_RANGE(cmd->chanlist[i]);

		if (chan < prev_chan) {
			dev_dbg(dev->class_dev,
				"%s: channel numbers must increase\n",
				__func__);
			return -EINVAL;
		}

		if (range != range0) {
			dev_dbg(dev->class_dev,
				"%s: channels must have the same range\n",
				__func__);
			return -EINVAL;
		}

		prev_chan = chan;
	}

	return 0;
}

944 945
static int pci230_ao_cmdtest(struct comedi_device *dev,
			     struct comedi_subdevice *s, struct comedi_cmd *cmd)
946
{
947 948
	const struct pci230_board *thisboard = comedi_board(dev);
	struct pci230_private *devpriv = dev->private;
949 950 951
	int err = 0;
	unsigned int tmp;

952
	/* Step 1 : check if triggers are trivially valid */
953

954
	err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
955

956
	tmp = TRIG_TIMER | TRIG_INT;
957
	if (thisboard->min_hwver > 0 && devpriv->hwver >= 2) {
958 959 960 961 962 963 964 965 966 967 968 969 970 971
		/*
		 * For PCI230+ hardware version 2 onwards, allow external
		 * trigger from EXTTRIG/EXTCONVCLK input (PCI230+ pin 25).
		 *
		 * FIXME: The permitted scan_begin_src values shouldn't depend
		 * on devpriv->hwver (the detected card's actual hardware
		 * version).  They should only depend on thisboard->min_hwver
		 * (the static capabilities of the configured card).  To fix
		 * it, a new card model, e.g. "pci230+2" would have to be
		 * defined with min_hwver set to 2.  It doesn't seem worth it
		 * for this alone.  At the moment, please consider
		 * scan_begin_src==TRIG_EXT support to be a bonus rather than a
		 * guarantee!
		 */
972
		tmp |= TRIG_EXT;
973
	}
974
	err |= cfc_check_trigger_src(&cmd->scan_begin_src, tmp);
975

976 977 978
	err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
	err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
979 980 981 982

	if (err)
		return 1;

983
	/* Step 2a : make sure trigger sources are unique */
984

985 986 987 988
	err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
	err |= cfc_check_trigger_is_unique(cmd->stop_src);

	/* Step 2b : and mutually compatible */
989 990 991 992

	if (err)
		return 2;

993 994 995
	/* Step 3: check if arguments are trivially valid */

	err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
996 997

#define MAX_SPEED_AO	8000	/* 8000 ns => 125 kHz */
998 999 1000 1001
/*
 * Comedi limit due to unsigned int cmd.  Driver limit =
 * 2^16 (16bit * counter) * 1000000ns (1kHz onboard clock) = 65.536s
 */
1002 1003 1004 1005
#define MIN_SPEED_AO	4294967295u	/* 4294967295ns = 4.29s */

	switch (cmd->scan_begin_src) {
	case TRIG_TIMER:
1006 1007 1008 1009
		err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
						 MAX_SPEED_AO);
		err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
						 MIN_SPEED_AO);
1010 1011
		break;
	case TRIG_EXT:
1012 1013 1014
		/*
		 * External trigger - for PCI230+ hardware version 2 onwards.
		 */
1015
		/* Trigger number must be 0. */
1016
		if (cmd->scan_begin_arg & ~CR_FLAGS_MASK) {
1017
			cmd->scan_begin_arg = COMBINE(cmd->scan_begin_arg, 0,
1018
						      ~CR_FLAGS_MASK);
1019
			err |= -EINVAL;
1020
		}
1021 1022 1023 1024
		/*
		 * The only flags allowed are CR_EDGE and CR_INVERT.
		 * The CR_EDGE flag is ignored.
		 */
1025 1026 1027 1028 1029
		if (cmd->scan_begin_arg & CR_FLAGS_MASK &
		    ~(CR_EDGE | CR_INVERT)) {
			cmd->scan_begin_arg =
			    COMBINE(cmd->scan_begin_arg, 0,
				    CR_FLAGS_MASK & ~(CR_EDGE | CR_INVERT));
1030
			err |= -EINVAL;
1031 1032 1033
		}
		break;
	default:
1034
		err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
1035 1036 1037
		break;
	}

1038 1039 1040 1041
	err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);

	if (cmd->stop_src == TRIG_NONE)
		err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
1042 1043 1044 1045

	if (err)
		return 3;

1046
	/* Step 4: fix up any arguments */
1047 1048 1049

	if (cmd->scan_begin_src == TRIG_TIMER) {
		tmp = cmd->scan_begin_arg;
1050
		pci230_ns_to_single_timer(&cmd->scan_begin_arg, cmd->flags);
1051 1052 1053 1054 1055 1056 1057
		if (tmp != cmd->scan_begin_arg)
			err++;
	}

	if (err)
		return 4;

1058 1059 1060
	/* Step 5: check channel list if it exists */
	if (cmd->chanlist && cmd->chanlist_len > 0)
		err |= pci230_ao_check_chanlist(dev, s, cmd);
1061 1062 1063 1064 1065 1066 1067

	if (err)
		return 5;

	return 0;
}

1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094
static void pci230_ao_stop(struct comedi_device *dev,
			   struct comedi_subdevice *s)
{
	struct pci230_private *devpriv = dev->private;
	unsigned long irqflags;
	unsigned char intsrc;
	int started;
	struct comedi_cmd *cmd;

	spin_lock_irqsave(&devpriv->ao_stop_spinlock, irqflags);
	started = test_and_clear_bit(AO_CMD_STARTED, &devpriv->state);
	spin_unlock_irqrestore(&devpriv->ao_stop_spinlock, irqflags);
	if (!started)
		return;
	cmd = &s->async->cmd;
	if (cmd->scan_begin_src == TRIG_TIMER) {
		/* Stop scan rate generator. */
		pci230_cancel_ct(dev, 1);
	}
	/* Determine interrupt source. */
	if (devpriv->hwver < 2) {
		/* Not using DAC FIFO.  Using CT1 interrupt. */
		intsrc = PCI230_INT_ZCLK_CT1;
	} else {
		/* Using DAC FIFO interrupt. */
		intsrc = PCI230P2_INT_DAC;
	}
1095 1096 1097 1098
	/*
	 * Disable interrupt and wait for interrupt routine to finish running
	 * unless we are called from the interrupt routine.
	 */
1099 1100 1101 1102 1103 1104 1105 1106
	spin_lock_irqsave(&devpriv->isr_spinlock, irqflags);
	devpriv->int_en &= ~intsrc;
	while (devpriv->intr_running && devpriv->intr_cpuid != THISCPU) {
		spin_unlock_irqrestore(&devpriv->isr_spinlock, irqflags);
		spin_lock_irqsave(&devpriv->isr_spinlock, irqflags);
	}
	if (devpriv->ier != devpriv->int_en) {
		devpriv->ier = devpriv->int_en;
1107
		outb(devpriv->ier, dev->iobase + PCI230_INT_SCE);
1108 1109 1110
	}
	spin_unlock_irqrestore(&devpriv->isr_spinlock, irqflags);
	if (devpriv->hwver >= 2) {
1111 1112 1113 1114
		/*
		 * Using DAC FIFO.  Reset FIFO, clear underrun error,
		 * disable FIFO.
		 */
1115
		devpriv->daccon &= PCI230_DAC_OR_MASK;
1116 1117
		outw(devpriv->daccon | PCI230P2_DAC_FIFO_RESET |
		     PCI230P2_DAC_FIFO_UNDERRUN_CLEAR,
1118
		     devpriv->daqio + PCI230_DACCON);
1119 1120 1121 1122 1123 1124 1125 1126 1127
	}
	/* Release resources. */
	put_all_resources(dev, OWNER_AOCMD);
}

static void pci230_handle_ao_nofifo(struct comedi_device *dev,
				    struct comedi_subdevice *s)
{
	struct pci230_private *devpriv = dev->private;
1128
	unsigned short data;
1129 1130 1131 1132
	int i, ret;
	struct comedi_async *async = s->async;
	struct comedi_cmd *cmd = &async->cmd;

1133
	if (cmd->stop_src == TRIG_COUNT && devpriv->ao_scan_count == 0)
1134 1135
		return;
	for (i = 0; i < cmd->chanlist_len; i++) {
1136 1137
		unsigned int chan = CR_CHAN(cmd->chanlist[i]);

1138
		/* Read sample from Comedi's circular buffer. */
1139
		ret = comedi_buf_get(s, &data);
1140 1141 1142
		if (ret == 0) {
			s->async->events |= COMEDI_CB_OVERFLOW;
			pci230_ao_stop(dev, s);
1143
			dev_err(dev->class_dev, "AO buffer underrun\n");
1144 1145
			return;
		}
1146 1147
		pci230_ao_write_nofifo(dev, data, chan);
		s->readback[chan] = data;
1148 1149
	}
	async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOS;
1150
	if (cmd->stop_src == TRIG_COUNT) {
1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175
		devpriv->ao_scan_count--;
		if (devpriv->ao_scan_count == 0) {
			/* End of acquisition. */
			async->events |= COMEDI_CB_EOA;
			pci230_ao_stop(dev, s);
		}
	}
}

/* Loads DAC FIFO (if using it) from buffer. */
/* Returns 0 if AO finished due to completion or error, 1 if still going. */
static int pci230_handle_ao_fifo(struct comedi_device *dev,
				 struct comedi_subdevice *s)
{
	struct pci230_private *devpriv = dev->private;
	struct comedi_async *async = s->async;
	struct comedi_cmd *cmd = &async->cmd;
	unsigned int num_scans;
	unsigned int room;
	unsigned short dacstat;
	unsigned int i, n;
	unsigned int events = 0;
	int running;

	/* Get DAC FIFO status. */
1176
	dacstat = inw(devpriv->daqio + PCI230_DACCON);
1177
	/* Determine number of scans available in buffer. */
1178
	num_scans = comedi_buf_read_n_available(s) / cfc_bytes_per_scan(s);
1179
	if (cmd->stop_src == TRIG_COUNT) {
1180 1181 1182 1183 1184 1185 1186 1187 1188 1189
		/* Fixed number of scans. */
		if (num_scans > devpriv->ao_scan_count)
			num_scans = devpriv->ao_scan_count;
		if (devpriv->ao_scan_count == 0) {
			/* End of acquisition. */
			events |= COMEDI_CB_EOA;
		}
	}
	if (events == 0) {
		/* Check for FIFO underrun. */
1190
		if (dacstat & PCI230P2_DAC_FIFO_UNDERRUN_LATCHED) {
1191
			dev_err(dev->class_dev, "AO FIFO underrun\n");
1192 1193
			events |= COMEDI_CB_OVERFLOW | COMEDI_CB_ERROR;
		}
1194 1195
		/*
		 * Check for buffer underrun if FIFO less than half full
1196
		 * (otherwise there will be loads of "DAC FIFO not half full"
1197 1198
		 * interrupts).
		 */
1199 1200
		if (num_scans == 0 &&
		    (dacstat & PCI230P2_DAC_FIFO_HALF) == 0) {
1201
			dev_err(dev->class_dev, "AO buffer underrun\n");
1202 1203 1204 1205 1206
			events |= COMEDI_CB_OVERFLOW | COMEDI_CB_ERROR;
		}
	}
	if (events == 0) {
		/* Determine how much room is in the FIFO (in samples). */
1207
		if (dacstat & PCI230P2_DAC_FIFO_FULL)
1208
			room = PCI230P2_DAC_FIFOROOM_FULL;
1209
		else if (dacstat & PCI230P2_DAC_FIFO_HALF)
1210
			room = PCI230P2_DAC_FIFOROOM_HALFTOFULL;
1211
		else if (dacstat & PCI230P2_DAC_FIFO_EMPTY)
1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222
			room = PCI230P2_DAC_FIFOROOM_EMPTY;
		else
			room = PCI230P2_DAC_FIFOROOM_ONETOHALF;
		/* Convert room to number of scans that can be added. */
		room /= cmd->chanlist_len;
		/* Determine number of scans to process. */
		if (num_scans > room)
			num_scans = room;
		/* Process scans. */
		for (n = 0; n < num_scans; n++) {
			for (i = 0; i < cmd->chanlist_len; i++) {
1223