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  • Soren Brinkmann's avatar
    clk/zynq/clkc: Add 'fclk-enable' feature · ba52f8a9
    Soren Brinkmann authored
    
    
    In some use cases Zynq's FPGA clocks are used as static clock
    generators for IP in the FPGA part of the SOC for which no Linux driver
    exists and would control those clocks. To avoid automatic
    gating of these clocks in such cases a new property - fclk-enable - is
    added to the clock controller's DT description to accomodate such use
    cases. It's value is a bitmask, where a set bit results in enabling
    the corresponding FCLK through the clkc.
    
    FPGA clocks are handled following the rules below:
    
    If an FCLK is not enabled by bootloaders, that FCLK will be disabled in
    Linux. Drivers can enable and control it through the CCF as usual.
    
    If an FCLK is enabled by bootloaders AND the corresponding bit in the
    'fclk-enable' DT property is set, that FCLK will be enabled by the clkc,
    resulting in an off by one reference count for that clock. Ensuring it
    will always be running.
    
    Signed-off-by: default avatarSoren Brinkmann <soren.brinkmann@xilinx.com>
    Acked-by: default avatarMichal Simek <michal.simek@xilinx.com>
    Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
    ba52f8a9