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    [POWERPC] Provide a way to protect 4k subpages when using 64k pages · fa28237c
    Paul Mackerras authored
    
    
    Using 64k pages on 64-bit PowerPC systems makes life difficult for
    emulators that are trying to emulate an ISA, such as x86, which use a
    smaller page size, since the emulator can no longer use the MMU and
    the normal system calls for controlling page protections.  Of course,
    the emulator can emulate the MMU by checking and possibly remapping
    the address for each memory access in software, but that is pretty
    slow.
    
    This provides a facility for such programs to control the access
    permissions on individual 4k sub-pages of 64k pages.  The idea is
    that the emulator supplies an array of protection masks to apply to a
    specified range of virtual addresses.  These masks are applied at the
    level where hardware PTEs are inserted into the hardware page table
    based on the Linux PTEs, so the Linux PTEs are not affected.  Note
    that this new mechanism does not allow any access that would otherwise
    be prohibited; it can only prohibit accesses that would otherwise be
    allowed.  This new facility is only available on 64-bit PowerPC and
    only when the kernel is configured for 64k pages.
    
    The masks are supplied using a new subpage_prot system call, which
    takes a starting virtual address and length, and a pointer to an array
    of protection masks in memory.  The array has a 32-bit word per 64k
    page to be protected; each 32-bit word consists of 16 2-bit fields,
    for which 0 allows any access (that is otherwise allowed), 1 prevents
    write accesses, and 2 or 3 prevent any access.
    
    Implicit in this is that the regions of the address space that are
    protected are switched to use 4k hardware pages rather than 64k
    hardware pages (on machines with hardware 64k page support).  In fact
    the whole process is switched to use 4k hardware pages when the
    subpage_prot system call is used, but this could be improved in future
    to switch only the affected segments.
    
    The subpage protection bits are stored in a 3 level tree akin to the
    page table tree.  The top level of this tree is stored in a structure
    that is appended to the top level of the page table tree, i.e., the
    pgd array.  Since it will often only be 32-bit addresses (below 4GB)
    that are protected, the pointers to the first four bottom level pages
    are also stored in this structure (each bottom level page contains the
    protection bits for 1GB of address space), so the protection bits for
    addresses below 4GB can be accessed with one fewer loads than those
    for higher addresses.
    
    Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
    fa28237c