Commit 1cd4027c authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq updates from Thomas Gleixner:
 "This update provides:

   - Yet another two irq controller chip drivers

   - A few updates and fixes for GICV3

   - A resource managed function for interrupt allocation

   - Fixes, updates and enhancements all over the place"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/qcom: Fix error handling
  genirq: Clarify logic calculating bogus irqreturn_t values
  genirq/msi: Add stubs for get_cached_msi_msg/pci_write_msi_msg
  genirq/devres: Use dev_name(dev) as default for devname
  genirq: Fix /proc/interrupts output alignment
  irqdesc: Add a resource managed version of irq_alloc_descs()
  irqchip/gic-v3-its: Zero command on allocation
  irqchip/gic-v3-its: Fix command buffer allocation
  irqchip/mips-gic: Fix local interrupts
  irqchip: Add a driver for Cortina Gemini
  irqchip: DT bindings for Cortina Gemini irqchip
  irqchip/gic-v3: Remove duplicate definition of GICD_TYPER_LPIS
  irqchip/gic-v3-its: Rename MAPVI to MAPTI
  irqchip/gic-v3-its: Drop deprecated GITS_BASER_TYPE_CPU
  irqchip/gic-v3-its: Refactor command encoding
  irqchip/gic-v3-its: Enable cacheable attribute Read-allocate hints
  irqchip/qcom: Add IRQ combiner driver
  ACPI: Add support for ResourceSource/IRQ domain mapping
  ACPI: Generic GSI: Do not attempt to map non-GSI IRQs during bus scan
  irq/platform-msi: Fix comment about maximal MSIs
parents 20dcfe1b 3900dea4
* Cortina Systems Gemini interrupt controller
This interrupt controller is found on the Gemini SoCs.
Required properties:
- compatible: must be "cortina,gemini-interrupt-controller"
- reg: The register bank for the interrupt controller.
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: The number of cells to define the interrupts.
Must be 2 as the controller can specify level or rising edge
IRQs. The bindings follows the standard binding for controllers
with two cells specified in
interrupt-controller/interrupts.txt
Example:
interrupt-controller@48000000 {
compatible = "cortina,gemini-interrupt-controller";
reg = <0x48000000 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
};
......@@ -306,6 +306,11 @@ IRQ
devm_request_any_context_irq()
devm_request_irq()
devm_request_threaded_irq()
devm_irq_alloc_descs()
devm_irq_alloc_desc()
devm_irq_alloc_desc_at()
devm_irq_alloc_desc_from()
devm_irq_alloc_descs_from()
LED
devm_led_classdev_register()
......
......@@ -55,7 +55,7 @@ acpi-$(CONFIG_DEBUG_FS) += debugfs.o
acpi-$(CONFIG_ACPI_NUMA) += numa.o
acpi-$(CONFIG_ACPI_PROCFS_POWER) += cm_sbs.o
acpi-y += acpi_lpat.o
acpi-$(CONFIG_ACPI_GENERIC_GSI) += gsi.o
acpi-$(CONFIG_ACPI_GENERIC_GSI) += irq.o
acpi-$(CONFIG_ACPI_WATCHDOG) += acpi_watchdog.o
# These are (potentially) separate modules
......
......@@ -84,6 +84,205 @@ void acpi_unregister_gsi(u32 gsi)
}
EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
/**
* acpi_get_irq_source_fwhandle() - Retrieve fwhandle from IRQ resource source.
* @source: acpi_resource_source to use for the lookup.
*
* Description:
* Retrieve the fwhandle of the device referenced by the given IRQ resource
* source.
*
* Return:
* The referenced device fwhandle or NULL on failure
*/
static struct fwnode_handle *
acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source)
{
struct fwnode_handle *result;
struct acpi_device *device;
acpi_handle handle;
acpi_status status;
if (!source->string_length)
return acpi_gsi_domain_id;
status = acpi_get_handle(NULL, source->string_ptr, &handle);
if (WARN_ON(ACPI_FAILURE(status)))
return NULL;
device = acpi_bus_get_acpi_device(handle);
if (WARN_ON(!device))
return NULL;
result = &device->fwnode;
acpi_bus_put_acpi_device(device);
return result;
}
/*
* Context for the resource walk used to lookup IRQ resources.
* Contains a return code, the lookup index, and references to the flags
* and fwspec where the result is returned.
*/
struct acpi_irq_parse_one_ctx {
int rc;
unsigned int index;
unsigned long *res_flags;
struct irq_fwspec *fwspec;
};
/**
* acpi_irq_parse_one_match - Handle a matching IRQ resource.
* @fwnode: matching fwnode
* @hwirq: hardware IRQ number
* @triggering: triggering attributes of hwirq
* @polarity: polarity attributes of hwirq
* @polarity: polarity attributes of hwirq
* @shareable: shareable attributes of hwirq
* @ctx: acpi_irq_parse_one_ctx updated by this function
*
* Description:
* Handle a matching IRQ resource by populating the given ctx with
* the information passed.
*/
static inline void acpi_irq_parse_one_match(struct fwnode_handle *fwnode,
u32 hwirq, u8 triggering,
u8 polarity, u8 shareable,
struct acpi_irq_parse_one_ctx *ctx)
{
if (!fwnode)
return;
ctx->rc = 0;
*ctx->res_flags = acpi_dev_irq_flags(triggering, polarity, shareable);
ctx->fwspec->fwnode = fwnode;
ctx->fwspec->param[0] = hwirq;
ctx->fwspec->param[1] = acpi_dev_get_irq_type(triggering, polarity);
ctx->fwspec->param_count = 2;
}
/**
* acpi_irq_parse_one_cb - Handle the given resource.
* @ares: resource to handle
* @context: context for the walk
*
* Description:
* This is called by acpi_walk_resources passing each resource returned by
* the _CRS method. We only inspect IRQ resources. Since IRQ resources
* might contain multiple interrupts we check if the index is within this
* one's interrupt array, otherwise we subtract the current resource IRQ
* count from the lookup index to prepare for the next resource.
* Once a match is found we call acpi_irq_parse_one_match to populate
* the result and end the walk by returning AE_CTRL_TERMINATE.
*
* Return:
* AE_OK if the walk should continue, AE_CTRL_TERMINATE if a matching
* IRQ resource was found.
*/
static acpi_status acpi_irq_parse_one_cb(struct acpi_resource *ares,
void *context)
{
struct acpi_irq_parse_one_ctx *ctx = context;
struct acpi_resource_irq *irq;
struct acpi_resource_extended_irq *eirq;
struct fwnode_handle *fwnode;
switch (ares->type) {
case ACPI_RESOURCE_TYPE_IRQ:
irq = &ares->data.irq;
if (ctx->index >= irq->interrupt_count) {
ctx->index -= irq->interrupt_count;
return AE_OK;
}
fwnode = acpi_gsi_domain_id;
acpi_irq_parse_one_match(fwnode, irq->interrupts[ctx->index],
irq->triggering, irq->polarity,
irq->sharable, ctx);
return AE_CTRL_TERMINATE;
case ACPI_RESOURCE_TYPE_EXTENDED_IRQ:
eirq = &ares->data.extended_irq;
if (eirq->producer_consumer == ACPI_PRODUCER)
return AE_OK;
if (ctx->index >= eirq->interrupt_count) {
ctx->index -= eirq->interrupt_count;
return AE_OK;
}
fwnode = acpi_get_irq_source_fwhandle(&eirq->resource_source);
acpi_irq_parse_one_match(fwnode, eirq->interrupts[ctx->index],
eirq->triggering, eirq->polarity,
eirq->sharable, ctx);
return AE_CTRL_TERMINATE;
}
return AE_OK;
}
/**
* acpi_irq_parse_one - Resolve an interrupt for a device
* @handle: the device whose interrupt is to be resolved
* @index: index of the interrupt to resolve
* @fwspec: structure irq_fwspec filled by this function
* @flags: resource flags filled by this function
*
* Description:
* Resolves an interrupt for a device by walking its CRS resources to find
* the appropriate ACPI IRQ resource and populating the given struct irq_fwspec
* and flags.
*
* Return:
* The result stored in ctx.rc by the callback, or the default -EINVAL value
* if an error occurs.
*/
static int acpi_irq_parse_one(acpi_handle handle, unsigned int index,
struct irq_fwspec *fwspec, unsigned long *flags)
{
struct acpi_irq_parse_one_ctx ctx = { -EINVAL, index, flags, fwspec };
acpi_walk_resources(handle, METHOD_NAME__CRS, acpi_irq_parse_one_cb, &ctx);
return ctx.rc;
}
/**
* acpi_irq_get - Lookup an ACPI IRQ resource and use it to initialize resource.
* @handle: ACPI device handle
* @index: ACPI IRQ resource index to lookup
* @res: Linux IRQ resource to initialize
*
* Description:
* Look for the ACPI IRQ resource with the given index and use it to initialize
* the given Linux IRQ resource.
*
* Return:
* 0 on success
* -EINVAL if an error occurs
* -EPROBE_DEFER if the IRQ lookup/conversion failed
*/
int acpi_irq_get(acpi_handle handle, unsigned int index, struct resource *res)
{
struct irq_fwspec fwspec;
struct irq_domain *domain;
unsigned long flags;
int rc;
rc = acpi_irq_parse_one(handle, index, &fwspec, &flags);
if (rc)
return rc;
domain = irq_find_matching_fwnode(fwspec.fwnode, DOMAIN_BUS_ANY);
if (!domain)
return -EPROBE_DEFER;
rc = irq_create_fwspec_mapping(&fwspec);
if (rc <= 0)
return -EINVAL;
res->start = rc;
res->end = rc;
res->flags = flags;
return 0;
}
EXPORT_SYMBOL_GPL(acpi_irq_get);
/**
* acpi_set_irq_model - Setup the GSI irqdomain information
* @model: the value assigned to acpi_irq_model
......
......@@ -43,6 +43,19 @@ static inline bool
acpi_iospace_resource_valid(struct resource *res) { return true; }
#endif
#if IS_ENABLED(CONFIG_ACPI_GENERIC_GSI)
static inline bool is_gsi(struct acpi_resource_extended_irq *ext_irq)
{
return ext_irq->resource_source.string_length == 0 &&
ext_irq->producer_consumer == ACPI_CONSUMER;
}
#else
static inline bool is_gsi(struct acpi_resource_extended_irq *ext_irq)
{
return true;
}
#endif
static bool acpi_dev_resource_len_valid(u64 start, u64 end, u64 len, bool io)
{
u64 reslen = end - start + 1;
......@@ -470,9 +483,12 @@ bool acpi_dev_resource_interrupt(struct acpi_resource *ares, int index,
acpi_dev_irqresource_disabled(res, 0);
return false;
}
acpi_dev_get_irqresource(res, ext_irq->interrupts[index],
if (is_gsi(ext_irq))
acpi_dev_get_irqresource(res, ext_irq->interrupts[index],
ext_irq->triggering, ext_irq->polarity,
ext_irq->sharable, false);
else
acpi_dev_irqresource_disabled(res, 0);
break;
default:
res->flags = 0;
......
......@@ -206,7 +206,7 @@ platform_msi_alloc_priv_data(struct device *dev, unsigned int nvec,
{
struct platform_msi_priv_data *datap;
/*
* Limit the number of interrupts to 256 per device. Should we
* Limit the number of interrupts to 2048 per device. Should we
* need to bump this up, DEV_ID_SHIFT should be adjusted
* accordingly (which would impact the max number of MSI
* capable devices).
......
......@@ -102,6 +102,16 @@ int platform_get_irq(struct platform_device *dev, unsigned int num)
}
r = platform_get_resource(dev, IORESOURCE_IRQ, num);
if (has_acpi_companion(&dev->dev)) {
if (r && r->flags & IORESOURCE_DISABLED) {
int ret;
ret = acpi_irq_get(ACPI_HANDLE(&dev->dev), num, r);
if (ret)
return ret;
}
}
/*
* The resources may pass trigger flags to the irqs that need
* to be set up. It so happens that the trigger flags for
......
......@@ -283,3 +283,12 @@ config EZNPS_GIC
config STM32_EXTI
bool
select IRQ_DOMAIN
config QCOM_IRQ_COMBINER
bool "QCOM IRQ combiner support"
depends on ARCH_QCOM && ACPI
select IRQ_DOMAIN
select IRQ_DOMAIN_HIERARCHY
help
Say yes here to add support for the IRQ combiner devices embedded
in Qualcomm Technologies chips.
......@@ -6,6 +6,7 @@ obj-$(CONFIG_ATH79) += irq-ath79-misc.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
obj-$(CONFIG_ARCH_GEMINI) += irq-gemini.o
obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o
obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
......@@ -75,3 +76,4 @@ obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
/*
* irqchip for the Cortina Systems Gemini Copyright (C) 2017 Linus
* Walleij <linus.walleij@linaro.org>
*
* Based on arch/arm/mach-gemini/irq.c
* Copyright (C) 2001-2006 Storlink, Corp.
* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
*/
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irqchip/versatile-fpga.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/cpu.h>
#include <asm/exception.h>
#include <asm/mach/irq.h>
#define GEMINI_NUM_IRQS 32
#define GEMINI_IRQ_SOURCE(base_addr) (base_addr + 0x00)
#define GEMINI_IRQ_MASK(base_addr) (base_addr + 0x04)
#define GEMINI_IRQ_CLEAR(base_addr) (base_addr + 0x08)
#define GEMINI_IRQ_MODE(base_addr) (base_addr + 0x0C)
#define GEMINI_IRQ_POLARITY(base_addr) (base_addr + 0x10)
#define GEMINI_IRQ_STATUS(base_addr) (base_addr + 0x14)
#define GEMINI_FIQ_SOURCE(base_addr) (base_addr + 0x20)
#define GEMINI_FIQ_MASK(base_addr) (base_addr + 0x24)
#define GEMINI_FIQ_CLEAR(base_addr) (base_addr + 0x28)
#define GEMINI_FIQ_MODE(base_addr) (base_addr + 0x2C)
#define GEMINI_FIQ_POLARITY(base_addr) (base_addr + 0x30)
#define GEMINI_FIQ_STATUS(base_addr) (base_addr + 0x34)
/**
* struct gemini_irq_data - irq data container for the Gemini IRQ controller
* @base: memory offset in virtual memory
* @chip: chip container for this instance
* @domain: IRQ domain for this instance
*/
struct gemini_irq_data {
void __iomem *base;
struct irq_chip chip;
struct irq_domain *domain;
};
static void gemini_irq_mask(struct irq_data *d)
{
struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
unsigned int mask;
mask = readl(GEMINI_IRQ_MASK(g->base));
mask &= ~BIT(irqd_to_hwirq(d));
writel(mask, GEMINI_IRQ_MASK(g->base));
}
static void gemini_irq_unmask(struct irq_data *d)
{
struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
unsigned int mask;
mask = readl(GEMINI_IRQ_MASK(g->base));
mask |= BIT(irqd_to_hwirq(d));
writel(mask, GEMINI_IRQ_MASK(g->base));
}
static void gemini_irq_ack(struct irq_data *d)
{
struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
writel(BIT(irqd_to_hwirq(d)), GEMINI_IRQ_CLEAR(g->base));
}
static int gemini_irq_set_type(struct irq_data *d, unsigned int trigger)
{
struct gemini_irq_data *g = irq_data_get_irq_chip_data(d);
int offset = irqd_to_hwirq(d);
u32 mode, polarity;
mode = readl(GEMINI_IRQ_MODE(g->base));
polarity = readl(GEMINI_IRQ_POLARITY(g->base));
if (trigger & (IRQ_TYPE_LEVEL_HIGH)) {
irq_set_handler_locked(d, handle_level_irq);
/* Disable edge detection */
mode &= ~BIT(offset);
polarity &= ~BIT(offset);
} else if (trigger & IRQ_TYPE_EDGE_RISING) {
irq_set_handler_locked(d, handle_edge_irq);
mode |= BIT(offset);
polarity |= BIT(offset);
} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
irq_set_handler_locked(d, handle_edge_irq);
mode |= BIT(offset);
polarity &= ~BIT(offset);
} else {
irq_set_handler_locked(d, handle_bad_irq);
pr_warn("GEMINI IRQ: no supported trigger selected for line %d\n",
offset);
}
writel(mode, GEMINI_IRQ_MODE(g->base));
writel(polarity, GEMINI_IRQ_POLARITY(g->base));
return 0;
}
static struct irq_chip gemini_irq_chip = {
.name = "GEMINI",
.irq_ack = gemini_irq_ack,
.irq_mask = gemini_irq_mask,
.irq_unmask = gemini_irq_unmask,
.irq_set_type = gemini_irq_set_type,
};
/* Local static for the IRQ entry call */
static struct gemini_irq_data girq;
asmlinkage void __exception_irq_entry gemini_irqchip_handle_irq(struct pt_regs *regs)
{
struct gemini_irq_data *g = &girq;
int irq;
u32 status;
while ((status = readl(GEMINI_IRQ_STATUS(g->base)))) {
irq = ffs(status) - 1;
handle_domain_irq(g->domain, irq, regs);
}
}
static int gemini_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
struct gemini_irq_data *g = d->host_data;
irq_set_chip_data(irq, g);
/* All IRQs should set up their type, flags as bad by default */
irq_set_chip_and_handler(irq, &gemini_irq_chip, handle_bad_irq);
irq_set_probe(irq);
return 0;
}
static void gemini_irqdomain_unmap(struct irq_domain *d, unsigned int irq)
{
irq_set_chip_and_handler(irq, NULL, NULL);
irq_set_chip_data(irq, NULL);
}
static const struct irq_domain_ops gemini_irqdomain_ops = {
.map = gemini_irqdomain_map,
.unmap = gemini_irqdomain_unmap,
.xlate = irq_domain_xlate_onetwocell,
};
int __init gemini_of_init_irq(struct device_node *node,
struct device_node *parent)
{
struct gemini_irq_data *g = &girq;
/*
* Disable the idle handler by default since it is buggy
* For more info see arch/arm/mach-gemini/idle.c
*/
cpu_idle_poll_ctrl(true);
g->base = of_iomap(node, 0);
WARN(!g->base, "unable to map gemini irq registers\n");
/* Disable all interrupts */
writel(0, GEMINI_IRQ_MASK(g->base));
writel(0, GEMINI_FIQ_MASK(g->base));
g->domain = irq_domain_add_simple(node, GEMINI_NUM_IRQS, 0,
&gemini_irqdomain_ops, g);
set_handle_irq(gemini_irqchip_handle_irq);
return 0;
}
IRQCHIP_DECLARE(gemini, "cortina,gemini-interrupt-controller",
gemini_of_init_irq);
......@@ -161,7 +161,7 @@ struct its_cmd_desc {
struct its_device *dev;
u32 phys_id;
u32 event_id;
} its_mapvi_cmd;
} its_mapti_cmd;
struct {
struct its_device *dev;
......@@ -193,58 +193,56 @@ struct its_cmd_block {
typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
struct its_cmd_desc *);
static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
{
u64 mask = GENMASK_ULL(h, l);
*raw_cmd &= ~mask;
*raw_cmd |= (val << l) & mask;
}
static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
{
cmd->raw_cmd[0] &= ~0xffULL;
cmd->raw_cmd[0] |= cmd_nr;
its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
}
static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
{
cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
cmd->raw_cmd[0] |= ((u64)devid) << 32;
its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
}
static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
{
cmd->raw_cmd[1] &= ~0xffffffffULL;
cmd->raw_cmd[1] |= id;
its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
}
static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
{
cmd->raw_cmd[1] &= 0xffffffffULL;
cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
}
static void its_encode_size(struct its_cmd_block *cmd, u8 size)
{
cmd->raw_cmd[1] &= ~0x1fULL;
cmd->raw_cmd[1] |= size & 0x1f;
its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
}
static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
{
cmd->raw_cmd[2] &= ~0xffffffffffffULL;
cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00ULL;
its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 50, 8);
}
static void its_encode_valid(struct its_cmd_block *cmd, int valid)
{
cmd->raw_cmd[2] &= ~(1ULL << 63);
cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
}
static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
{
cmd->raw_cmd[2] &= ~(0xffffffffULL << 16);
cmd->raw_cmd[2] |= (target_addr & (0xffffffffULL << 16));
its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 50, 16);
}
static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
{
cmd->raw_cmd[2] &= ~0xffffULL;
cmd->raw_cmd[2] |= col;
its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
}
static inline void its_fixup_cmd(struct its_cmd_block *cmd)
......@@ -289,18 +287,18 @@ static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
return desc->its_mapc_cmd.col;
}
static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd,
static struct its_collection *its_build_mapti_cmd(struct its_cmd_block *cmd,
struct its_cmd_desc *desc)
{
struct its_collection *col;
col = dev_event_to_col(desc->its_mapvi_cmd.dev,
desc->its_mapvi_cmd.event_id);
col = dev_event_to_col(desc->its_mapti_cmd.dev,
desc->its_mapti_cmd.event_id);
its_encode_cmd(cmd, GITS_CMD_MAPVI);
its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id);
its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id);
its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id);
its_encode_cmd(cmd, GITS_CMD_MAPTI);
its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
its_encode_collection(cmd, col->col_id);
its_fixup_cmd(cmd);
......@@ -413,6 +411,12 @@ static struct its_cmd_block *its_allocate_entry(struct its_node *its)
if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
its->cmd_write = its->cmd_base;
/* Clear command */
cmd->raw_cmd[0] = 0;
cmd->raw_cmd[1] = 0;
cmd->raw_cmd[2] = 0;
cmd->raw_cmd[3] = 0;