Commit 61792e40 authored by Joseph Lo's avatar Joseph Lo Committed by Peter De Schrijver

clk: tegra124: add suspend/resume function for tegra_cpu_car_ops

Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Acked-by: Stephen Warren's avatarStephen Warren <swarren@nvidia.com>
parent 9e036d3e
......@@ -28,6 +28,7 @@
#include "clk.h"
#include "clk-id.h"
#define CLK_SOURCE_CSITE 0x1d4
#define CLK_SOURCE_EMC 0x19c
#define CLK_SOURCE_XUSB_SS_SRC 0x610
......@@ -115,6 +116,12 @@
/* Tegra CPU clock and reset control regs */
#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
#ifdef CONFIG_PM_SLEEP
static struct cpu_clk_suspend_context {
u32 clk_csite_src;
} tegra124_cpu_clk_sctx;
#endif
static void __iomem *clk_base;
static void __iomem *pmc_base;
......@@ -1302,9 +1309,29 @@ static void tegra124_disable_cpu_clock(u32 cpu)
/* flow controller would take care in the power sequence. */
}
#ifdef CONFIG_PM_SLEEP
static void tegra124_cpu_clock_suspend(void)
{
/* switch coresite to clk_m, save off original source */
tegra124_cpu_clk_sctx.clk_csite_src =
readl(clk_base + CLK_SOURCE_CSITE);
writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
}
static void tegra124_cpu_clock_resume(void)
{
writel(tegra124_cpu_clk_sctx.clk_csite_src,
clk_base + CLK_SOURCE_CSITE);
}
#endif
static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
.wait_for_reset = tegra124_wait_cpu_in_reset,
.disable_clock = tegra124_disable_cpu_clock,
#ifdef CONFIG_PM_SLEEP
.suspend = tegra124_cpu_clock_suspend,
.resume = tegra124_cpu_clock_resume,
#endif
};
static const struct of_device_id pmc_match[] __initconst = {
......
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