Commit 831223b2 authored by Shubhrajyoti Datta's avatar Shubhrajyoti Datta Committed by Greg Kroah-Hartman

i2c: xiic: Make the start and the byte count write atomic

commit ae7304c3 upstream.

Disable interrupts while configuring the transfer and enable them back.

We have below as the programming sequence
1. start and slave address
2. byte count and stop

In some customer platform there was a lot of interrupts between 1 and 2
and after slave address (around 7 clock cyles) if 2 is not executed
then the transaction is nacked.

To fix this case make the 2 writes atomic.
Signed-off-by: default avatarShubhrajyoti Datta <>
Signed-off-by: default avatarMichal Simek <>
[wsa: added a newline for better readability]
Signed-off-by: default avatarWolfram Sang <>
Signed-off-by: default avatarGreg Kroah-Hartman <>
parent 5dfe87ac
......@@ -538,6 +538,7 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
u8 rx_watermark;
struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
unsigned long flags;
/* Clear and enable Rx full interrupt. */
......@@ -553,6 +554,7 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
rx_watermark = IIC_RX_FIFO_DEPTH;
xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
if (!(msg->flags & I2C_M_NOSTART))
/* write the address */
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
......@@ -563,6 +565,8 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
if (i2c->nmsgs == 1)
/* very last, enable bus not busy as well */
xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
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