Commit a6359d1e authored by Thomas Gleixner's avatar Thomas Gleixner

init_task: Replace CONFIG_HAVE_GENERIC_INIT_TASK

Now that all archs except ia64 are converted, replace the config and
let the ia64 select CONFIG_ARCH_INIT_TASK
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20120503085035.867948914@linutronix.de
parent e4d59621
......@@ -148,7 +148,8 @@ config USE_GENERIC_SMP_HELPERS
config GENERIC_SMP_IDLE_THREAD
bool
config HAVE_GENERIC_INIT_TASK
# Select if arch init_task initializer is different to init/init_task.c
config ARCH_INIT_TASK
bool
config HAVE_REGS_AND_STACK_ACCESS_API
......
......@@ -16,7 +16,6 @@ config ALPHA
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select GENERIC_SMP_IDLE_THREAD
select HAVE_GENERIC_INIT_TASK
help
The Alpha is a 64-bit general-purpose processor designed and
marketed by the Digital Equipment Corporation of blessed memory,
......
......@@ -35,7 +35,6 @@ config ARM
select GENERIC_PCI_IOMAP
select HAVE_BPF_JIT if NET
select GENERIC_SMP_IDLE_THREAD
select HAVE_GENERIC_INIT_TASK
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
......
......@@ -12,7 +12,6 @@ config AVR32
select HARDIRQS_SW_RESEND
select GENERIC_IRQ_SHOW
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select HAVE_GENERIC_INIT_TASK
help
AVR32 is a high-performance 32-bit RISC microprocessor core,
designed for cost-sensitive embedded applications, with particular
......
......@@ -38,7 +38,6 @@ config BLACKFIN
select IRQ_PER_CPU if SMP
select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
select GENERIC_SMP_IDLE_THREAD
select HAVE_GENERIC_INIT_TASK
config GENERIC_CSUM
def_bool y
......
......@@ -10,7 +10,6 @@ config TMS320C6X
select HAVE_ARCH_TRACEHOOK
select HAVE_DMA_API_DEBUG
select HAVE_GENERIC_HARDIRQS
select HAVE_GENERIC_INIT_TASK
select HAVE_MEMBLOCK
select SPARSE_IRQ
select IRQ_DOMAIN
......
......@@ -50,7 +50,6 @@ config CRIS
select GENERIC_IRQ_SHOW
select GENERIC_IOMAP
select GENERIC_SMP_IDLE_THREAD if ETRAX_ARCH_V32
select HAVE_GENERIC_INIT_TASK
config HZ
int
......
......@@ -9,7 +9,6 @@ config FRV
select GENERIC_IRQ_SHOW
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select GENERIC_CPU_DEVICES
select HAVE_GENERIC_INIT_TASK
config ZONE_DMA
bool
......
......@@ -5,7 +5,6 @@ config H8300
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_SHOW
select GENERIC_CPU_DEVICES
select HAVE_GENERIC_INIT_TASK
config SYMBOL_PREFIX
string
......
......@@ -28,7 +28,6 @@ config HEXAGON
select NO_IOPORT
select GENERIC_IOMAP
select GENERIC_SMP_IDLE_THREAD
select HAVE_GENERIC_INIT_TASK
# mostly generic routines, with some accelerated ones
---help---
Qualcomm Hexagon is a processor architecture designed for high
......
......@@ -34,6 +34,7 @@ config IA64
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select GENERIC_IOMAP
select GENERIC_SMP_IDLE_THREAD
select ARCH_INIT_TASK
default y
help
The Itanium Processor Family is Intel's 64-bit successor to
......
......@@ -11,7 +11,6 @@ config M32R
select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
select GENERIC_ATOMIC64
select HAVE_GENERIC_INIT_TASK
config SBUS
bool
......
......@@ -8,7 +8,6 @@ config M68K
select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS
select GENERIC_CPU_DEVICES
select FPU if MMU
select HAVE_GENERIC_INIT_TASK
config RWSEM_GENERIC_SPINLOCK
bool
......
......@@ -22,7 +22,6 @@ config MICROBLAZE
select GENERIC_PCI_IOMAP
select GENERIC_CPU_DEVICES
select GENERIC_ATOMIC64
select HAVE_GENERIC_INIT_TASK
config SWAP
def_bool n
......
......@@ -30,7 +30,6 @@ config MIPS
select HAVE_MEMBLOCK_NODE_MAP
select ARCH_DISCARD_MEMBLOCK
select GENERIC_SMP_IDLE_THREAD
select HAVE_GENERIC_INIT_TASK
menu "Machine selection"
......
......@@ -6,7 +6,6 @@ config MN10300
select HAVE_ARCH_TRACEHOOK
select HAVE_ARCH_KGDB
select HAVE_NMI_WATCHDOG if MN10300_WD_TIMER
select HAVE_GENERIC_INIT_TASK
config AM33_2
def_bool n
......
......@@ -17,7 +17,6 @@ config OPENRISC
select GENERIC_IOMAP
select GENERIC_CPU_DEVICES
select GENERIC_ATOMIC64
select HAVE_GENERIC_INIT_TASK
config MMU
def_bool y
......
......@@ -18,7 +18,6 @@ config PARISC
select IRQ_PER_CPU
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select GENERIC_SMP_IDLE_THREAD
select HAVE_GENERIC_INIT_TASK
help
The PA-RISC microprocessor is designed by Hewlett-Packard and used
......
......@@ -145,7 +145,6 @@ config PPC
select HAVE_ARCH_JUMP_LABEL
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select GENERIC_SMP_IDLE_THREAD
select HAVE_GENERIC_INIT_TASK
config EARLY_PRINTK
bool
......
......@@ -123,7 +123,6 @@ config S390
select ARCH_INLINE_WRITE_UNLOCK_IRQ
select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE
select GENERIC_SMP_IDLE_THREAD
select HAVE_GENERIC_INIT_TASK
config SCHED_OMIT_FRAME_POINTER
def_bool y
......
......@@ -9,7 +9,6 @@ config SCORE
select HAVE_MEMBLOCK_NODE_MAP
select ARCH_DISCARD_MEMBLOCK
select GENERIC_CPU_DEVICES
select HAVE_GENERIC_INIT_TASK
choice
prompt "System type"
......
......@@ -29,7 +29,6 @@ config SUPERH
select GENERIC_ATOMIC64
select GENERIC_IRQ_SHOW
select GENERIC_SMP_IDLE_THREAD
select HAVE_GENERIC_INIT_TASK
help
The SuperH is a RISC processor targeted for use in embedded systems
and consumer electronics; it was also used in the Sega Dreamcast
......
......@@ -31,7 +31,6 @@ config SPARC
select GENERIC_PCI_IOMAP
select HAVE_NMI_WATCHDOG if SPARC64
select GENERIC_SMP_IDLE_THREAD
select HAVE_GENERIC_INIT_TASK
config SPARC32
def_bool !64BIT
......
......@@ -13,7 +13,6 @@ config TILE
select GENERIC_IRQ_SHOW
select SYS_HYPERVISOR
select ARCH_HAVE_NMI_SAFE_CMPXCHG
select HAVE_GENERIC_INIT_TASK
# FIXME: investigate whether we need/want these options.
# select HAVE_IOREMAP_PROT
......
......@@ -10,7 +10,6 @@ config UML
select GENERIC_IRQ_SHOW
select GENERIC_CPU_DEVICES
select GENERIC_IO
select HAVE_GENERIC_INIT_TASK
config MMU
bool
......
......@@ -13,7 +13,6 @@ config UNICORE32
select GENERIC_IRQ_SHOW
select ARCH_WANT_FRAME_POINTERS
select GENERIC_IOMAP
select HAVE_GENERIC_INIT_TASK
help
UniCore-32 is 32-bit Instruction Set Architecture,
including a series of low-power-consumption RISC chip
......
......@@ -83,7 +83,6 @@ config X86
select GENERIC_IOMAP
select DCACHE_WORD_ACCESS if !DEBUG_PAGEALLOC
select GENERIC_SMP_IDLE_THREAD
select HAVE_GENERIC_INIT_TASK
config INSTRUCTION_DECODER
def_bool (KPROBES || PERF_EVENTS)
......
......@@ -10,7 +10,6 @@ config XTENSA
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_SHOW
select GENERIC_CPU_DEVICES
select HAVE_GENERIC_INIT_TASK
help
Xtensa processors are 32-bit RISC machines designed by Tensilica
primarily for embedded systems. These processors are both
......
......@@ -9,7 +9,10 @@ else
obj-$(CONFIG_BLK_DEV_INITRD) += initramfs.o
endif
obj-$(CONFIG_GENERIC_CALIBRATE_DELAY) += calibrate.o
obj-$(CONFIG_HAVE_GENERIC_INIT_TASK) += init_task.o
ifneq ($(CONFIG_ARCH_INIT_TASK),y)
obj-y += init_task.o
endif
mounts-y := do_mounts.o
mounts-$(CONFIG_BLK_DEV_RAM) += do_mounts_rd.o
......
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