Commit b2d7a075 authored by Juergen Gross's avatar Juergen Gross Committed by Boris Ostrovsky

x86/pae: use 64 bit atomic xchg function in native_ptep_get_and_clear

Using only 32-bit writes for the pte will result in an intermediate
L1TF vulnerable PTE. When running as a Xen PV guest this will at once
switch the guest to shadow mode resulting in a loss of performance.

Use arch_atomic64_xchg() instead which will perform the requested
operation atomically with all 64 bits.

Some performance considerations according to:

The main number should be the latency, as there is no tight loop around

"lock cmpxchg8b" has a latency of 20 cycles, while "lock xchg" (with a
memory operand) isn't mentioned in that document. "lock xadd" (with xadd
having 3 cycles less latency than xchg) has a latency of 11, so we can
assume a latency of 14 for "lock xchg".
Signed-off-by: default avatarJuergen Gross <>
Reviewed-by: default avatarThomas Gleixner <>
Reviewed-by: default avatarJan Beulich <>
Tested-by: default avatarJason Andryuk <>
Signed-off-by: default avatarBoris Ostrovsky <>
parent f7c90c2a
......@@ -2,6 +2,8 @@
#include <asm/atomic64_32.h>
* Intel Physical Address Extension (PAE) Mode - three-level page
* tables on PPro+ CPUs.
......@@ -150,10 +152,7 @@ static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
pte_t res;
/* xchg acts as a barrier before the setting of the high bits */
res.pte_low = xchg(&ptep->pte_low, 0);
res.pte_high = ptep->pte_high;
ptep->pte_high = 0;
res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0);
return res;
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