Commit cb765f5c authored by Anssi Hannula's avatar Anssi Hannula Committed by Greg Kroah-Hartman

net: macb: do not disable MDIO bus at open/close time

[ Upstream commit 0da70f80 ]

macb_reset_hw() is called from macb_close() and indirectly from
macb_open(). macb_reset_hw() zeroes the NCR register, including the MPE
(Management Port Enable) bit.

This will prevent accessing any other PHYs for other Ethernet MACs on
the MDIO bus, which remains registered at macb_reset_hw() time, until
macb_init_hw() is called from macb_open() which sets the MPE bit again.

I.e. currently the MDIO bus has a short disruption at open time and is
disabled at close time until the interface is opened again.

Fix that by only touching the RE and TE bits when enabling and disabling

v2: Make macb_init_hw() NCR write a single statement.

Fixes: 6c36a707 ("macb: Use generic PHY layer")
Signed-off-by: default avatarAnssi Hannula <>
Reviewed-by: default avatarClaudiu Beznea <>
Tested-by: default avatarClaudiu Beznea <>
Signed-off-by: default avatarDavid S. Miller <>
Signed-off-by: default avatarGreg Kroah-Hartman <>
parent 1ef819e4
......@@ -1884,14 +1884,17 @@ static void macb_reset_hw(struct macb *bp)
struct macb_queue *queue;
unsigned int q;
u32 ctrl = macb_readl(bp, NCR);
/* Disable RX and TX (XXX: Should we halt the transmission
* more gracefully?)
macb_writel(bp, NCR, 0);
ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
/* Clear the stats registers (XXX: Update stats first?) */
macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
macb_writel(bp, NCR, ctrl);
/* Clear all status flags */
macb_writel(bp, TSR, -1);
......@@ -2070,7 +2073,7 @@ static void macb_init_hw(struct macb *bp)
/* Enable TX and RX */
macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
/* The hash address register is 64 bits long and takes up two
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