qlcnic.h 65.8 KB
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/*
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 * QLogic qlcnic NIC Driver
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 * Copyright (c) 2009-2013 QLogic Corporation
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 *
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 * See LICENSE.qlcnic for copyright and licensing details.
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 */

#ifndef _QLCNIC_H_
#define _QLCNIC_H_

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ip.h>
#include <linux/in.h>
#include <linux/tcp.h>
#include <linux/skbuff.h>
#include <linux/firmware.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/timer.h>
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#include <linux/irq.h>
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#include <linux/vmalloc.h>
#include <linux/io.h>
#include <asm/byteorder.h>
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#include <linux/bitops.h>
#include <linux/if_vlan.h>
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#include "qlcnic_hdr.h"
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#include "qlcnic_hw.h"
#include "qlcnic_83xx_hw.h"
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#include "qlcnic_dcb.h"
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#define _QLCNIC_LINUX_MAJOR 5
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#define _QLCNIC_LINUX_MINOR 3
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#define _QLCNIC_LINUX_SUBVERSION 66
#define QLCNIC_LINUX_VERSIONID  "5.3.66"
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#define QLCNIC_DRV_IDC_VER  0x01
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#define QLCNIC_DRIVER_VERSION  ((_QLCNIC_LINUX_MAJOR << 16) |\
		 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
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#define QLCNIC_VERSION_CODE(a, b, c)	(((a) << 24) + ((b) << 16) + (c))
#define _major(v)	(((v) >> 24) & 0xff)
#define _minor(v)	(((v) >> 16) & 0xff)
#define _build(v)	((v) & 0xffff)

/* version in image has weird encoding:
 *  7:0  - major
 * 15:8  - minor
 * 31:16 - build (little endian)
 */
#define QLCNIC_DECODE_VERSION(v) \
	QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))

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#define QLCNIC_MIN_FW_VERSION     QLCNIC_VERSION_CODE(4, 4, 2)
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#define QLCNIC_NUM_FLASH_SECTORS (64)
#define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
#define QLCNIC_FLASH_TOTAL_SIZE  (QLCNIC_NUM_FLASH_SECTORS \
					* QLCNIC_FLASH_SECTOR_SIZE)

#define RCV_DESC_RINGSIZE(rds_ring)	\
	(sizeof(struct rcv_desc) * (rds_ring)->num_desc)
#define RCV_BUFF_RINGSIZE(rds_ring)	\
	(sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
#define STATUS_DESC_RINGSIZE(sds_ring)	\
	(sizeof(struct status_desc) * (sds_ring)->num_desc)
#define TX_BUFF_RINGSIZE(tx_ring)	\
	(sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
#define TX_DESC_RINGSIZE(tx_ring)	\
	(sizeof(struct cmd_desc_type0) * tx_ring->num_desc)

#define QLCNIC_P3P_A0		0x50
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#define QLCNIC_P3P_C0		0x58
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#define QLCNIC_IS_REVISION_P3P(REVISION)     (REVISION >= QLCNIC_P3P_A0)

#define FIRST_PAGE_GROUP_START	0
#define FIRST_PAGE_GROUP_END	0x100000

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#define P3P_MAX_MTU                     (9600)
#define P3P_MIN_MTU                     (68)
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#define QLCNIC_MAX_ETHERHDR                32 /* This contains some padding */

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#define QLCNIC_P3P_RX_BUF_MAX_LEN         (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
#define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN   (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
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#define QLCNIC_CT_DEFAULT_RX_BUF_LEN	2048
#define QLCNIC_LRO_BUFFER_EXTRA		2048

/* Tx defines */
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#define QLCNIC_MAX_FRAGS_PER_TX	14
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#define MAX_TSO_HEADER_DESC	2
#define MGMT_CMD_DESC_RESV	4
#define TX_STOP_THRESH		((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
							+ MGMT_CMD_DESC_RESV)
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#define QLCNIC_MAX_TX_TIMEOUTS	2
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/* Driver will use 1 Tx ring in INT-x/MSI/SRIOV mode. */
#define QLCNIC_SINGLE_RING		1
#define QLCNIC_DEF_SDS_RINGS		4
#define QLCNIC_DEF_TX_RINGS		4
#define QLCNIC_MAX_VNIC_TX_RINGS	4
#define QLCNIC_MAX_VNIC_SDS_RINGS	4
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#define QLCNIC_83XX_MINIMUM_VECTOR	3
#define QLCNIC_82XX_MINIMUM_VECTOR	2
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enum qlcnic_queue_type {
	QLCNIC_TX_QUEUE = 1,
	QLCNIC_RX_QUEUE,
};

/* Operational mode for driver */
#define QLCNIC_VNIC_MODE	0xFF
#define QLCNIC_DEFAULT_MODE	0x0
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/* Virtual NIC function count */
#define QLC_DEFAULT_VNIC_COUNT	8
#define QLC_84XX_VNIC_COUNT	16

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/*
 * Following are the states of the Phantom. Phantom will set them and
 * Host will read to check if the fields are correct.
 */
#define PHAN_INITIALIZE_FAILED		0xffff
#define PHAN_INITIALIZE_COMPLETE	0xff01

/* Host writes the following to notify that it has done the init-handshake */
#define PHAN_INITIALIZE_ACK		0xf00f
#define PHAN_PEG_RCV_INITIALIZED	0xff01

#define NUM_RCV_DESC_RINGS	3

#define RCV_RING_NORMAL 0
#define RCV_RING_JUMBO	1

#define MIN_CMD_DESCRIPTORS		64
#define MIN_RCV_DESCRIPTORS		64
#define MIN_JUMBO_DESCRIPTORS		32

#define MAX_CMD_DESCRIPTORS		1024
#define MAX_RCV_DESCRIPTORS_1G		4096
#define MAX_RCV_DESCRIPTORS_10G 	8192
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#define MAX_RCV_DESCRIPTORS_VF		2048
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#define MAX_JUMBO_RCV_DESCRIPTORS_1G	512
#define MAX_JUMBO_RCV_DESCRIPTORS_10G	1024

#define DEFAULT_RCV_DESCRIPTORS_1G	2048
#define DEFAULT_RCV_DESCRIPTORS_10G	4096
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#define DEFAULT_RCV_DESCRIPTORS_VF	1024
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#define MAX_RDS_RINGS                   2
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#define get_next_index(index, length)	\
	(((index) + 1) & ((length) - 1))

/*
 * Following data structures describe the descriptors that will be used.
 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
 * we are doing LSO (above the 1500 size packet) only.
 */
struct cmd_desc_type0 {
	u8 tcp_hdr_offset;	/* For LSO only */
	u8 ip_hdr_offset;	/* For LSO only */
	__le16 flags_opcode;	/* 15:13 unused, 12:7 opcode, 6:0 flags */
	__le32 nfrags__length;	/* 31:8 total len, 7:0 frag count */

	__le64 addr_buffer2;

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	__le16 encap_descr;	/* 15:10 offset of outer L3 header,
				 * 9:6 number of 32bit words in outer L3 header,
				 * 5 offload outer L4 checksum,
				 * 4 offload outer L3 checksum,
				 * 3 Inner L4 type, TCP=0, UDP=1,
				 * 2 Inner L3 type, IPv4=0, IPv6=1,
				 * 1 Outer L3 type,IPv4=0, IPv6=1,
				 * 0 type of encapsulation, GRE=0, VXLAN=1
				 */
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	__le16 mss;
	u8 port_ctxid;		/* 7:4 ctxid 3:0 port */
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	u8 hdr_length;		/* LSO only : MAC+IP+TCP Hdr size */
	u8 outer_hdr_length;	/* Encapsulation only */
	u8 rsvd1;
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	__le64 addr_buffer3;
	__le64 addr_buffer1;

	__le16 buffer_length[4];

	__le64 addr_buffer4;

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	u8 eth_addr[ETH_ALEN];
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	__le16 vlan_TCI;	/* In case of  encapsulation,
				 * this is for outer VLAN
				 */
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} __attribute__ ((aligned(64)));

/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
struct rcv_desc {
	__le16 reference_handle;
	__le16 reserved;
	__le32 buffer_length;	/* allocated buffer length (usually 2K) */
	__le64 addr_buffer;
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} __packed;
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struct status_desc {
	__le64 status_desc_data[2];
} __attribute__ ((aligned(16)));

/* UNIFIED ROMIMAGE */
#define QLCNIC_UNI_FW_MIN_SIZE		0xc8000
#define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL	0x0
#define QLCNIC_UNI_DIR_SECT_BOOTLD	0x6
#define QLCNIC_UNI_DIR_SECT_FW		0x7

/*Offsets */
#define QLCNIC_UNI_CHIP_REV_OFF		10
#define QLCNIC_UNI_FLAGS_OFF		11
#define QLCNIC_UNI_BIOS_VERSION_OFF 	12
#define QLCNIC_UNI_BOOTLD_IDX_OFF	27
#define QLCNIC_UNI_FIRMWARE_IDX_OFF 	29

struct uni_table_desc{
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	__le32	findex;
	__le32	num_entries;
	__le32	entry_size;
	__le32	reserved[5];
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};

struct uni_data_desc{
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	__le32	findex;
	__le32	size;
	__le32	reserved[5];
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};

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/* Flash Defines and Structures */
#define QLCNIC_FLT_LOCATION	0x3F1000
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#define QLCNIC_FDT_LOCATION     0x3F0000
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#define QLCNIC_B0_FW_IMAGE_REGION 0x74
#define QLCNIC_C0_FW_IMAGE_REGION 0x97
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#define QLCNIC_BOOTLD_REGION    0X72
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struct qlcnic_flt_header {
	u16 version;
	u16 len;
	u16 checksum;
	u16 reserved;
};

struct qlcnic_flt_entry {
	u8 region;
	u8 reserved0;
	u8 attrib;
	u8 reserved1;
	u32 size;
	u32 start_addr;
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	u32 end_addr;
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};

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/* Flash Descriptor Table */
struct qlcnic_fdt {
	u32	valid;
	u16	ver;
	u16	len;
	u16	cksum;
	u16	unused;
	u8	model[16];
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	u8	mfg_id;
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	u16	id;
	u8	flag;
	u8	erase_cmd;
	u8	alt_erase_cmd;
	u8	write_enable_cmd;
	u8	write_enable_bits;
	u8	write_statusreg_cmd;
	u8	unprotected_sec_cmd;
	u8	read_manuf_cmd;
	u32	block_size;
	u32	alt_block_size;
	u32	flash_size;
	u32	write_enable_data;
	u8	readid_addr_len;
	u8	write_disable_bits;
	u8	read_dev_id_len;
	u8	chip_erase_cmd;
	u16	read_timeo;
	u8	protected_sec_cmd;
	u8	resvd[65];
};
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/* Magic number to let user know flash is programmed */
#define	QLCNIC_BDINFO_MAGIC 0x12345678

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#define QLCNIC_BRDTYPE_P3P_REF_QG	0x0021
#define QLCNIC_BRDTYPE_P3P_HMEZ		0x0022
#define QLCNIC_BRDTYPE_P3P_10G_CX4_LP	0x0023
#define QLCNIC_BRDTYPE_P3P_4_GB		0x0024
#define QLCNIC_BRDTYPE_P3P_IMEZ		0x0025
#define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS	0x0026
#define QLCNIC_BRDTYPE_P3P_10000_BASE_T	0x0027
#define QLCNIC_BRDTYPE_P3P_XG_LOM	0x0028
#define QLCNIC_BRDTYPE_P3P_4_GB_MM	0x0029
#define QLCNIC_BRDTYPE_P3P_10G_SFP_CT	0x002a
#define QLCNIC_BRDTYPE_P3P_10G_SFP_QT	0x002b
#define QLCNIC_BRDTYPE_P3P_10G_CX4	0x0031
#define QLCNIC_BRDTYPE_P3P_10G_XFP	0x0032
#define QLCNIC_BRDTYPE_P3P_10G_TP	0x0080
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#define QLCNIC_MSIX_TABLE_OFFSET	0x44

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/* Flash memory map */
#define QLCNIC_BRDCFG_START	0x4000		/* board config */
#define QLCNIC_BOOTLD_START	0x10000		/* bootld */
#define QLCNIC_IMAGE_START	0x43000		/* compressed image */
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#define QLCNIC_USER_START	0x3E8000	/* Firmware info */
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#define QLCNIC_FW_VERSION_OFFSET	(QLCNIC_USER_START+0x408)
#define QLCNIC_FW_SIZE_OFFSET		(QLCNIC_USER_START+0x40c)
#define QLCNIC_FW_SERIAL_NUM_OFFSET	(QLCNIC_USER_START+0x81c)
#define QLCNIC_BIOS_VERSION_OFFSET	(QLCNIC_USER_START+0x83c)

#define QLCNIC_BRDTYPE_OFFSET		(QLCNIC_BRDCFG_START+0x8)
#define QLCNIC_FW_MAGIC_OFFSET		(QLCNIC_BRDCFG_START+0x128)

#define QLCNIC_FW_MIN_SIZE		(0x3fffff)
#define QLCNIC_UNIFIED_ROMIMAGE  	0
#define QLCNIC_FLASH_ROMIMAGE		1
#define QLCNIC_UNKNOWN_ROMIMAGE		0xff

#define QLCNIC_UNIFIED_ROMIMAGE_NAME	"phanfw.bin"
#define QLCNIC_FLASH_ROMIMAGE_NAME	"flash"

extern char qlcnic_driver_name[];

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extern int qlcnic_use_msi;
extern int qlcnic_use_msi_x;
extern int qlcnic_auto_fw_reset;
extern int qlcnic_load_fw_file;

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/* Number of status descriptors to handle per interrupt */
#define MAX_STATUS_HANDLE	(64)

/*
 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
 */
struct qlcnic_skb_frag {
	u64 dma;
	u64 length;
};

/*    Following defines are for the state of the buffers    */
#define	QLCNIC_BUFFER_FREE	0
#define	QLCNIC_BUFFER_BUSY	1

/*
 * There will be one qlcnic_buffer per skb packet.    These will be
 * used to save the dma info for pci_unmap_page()
 */
struct qlcnic_cmd_buffer {
	struct sk_buff *skb;
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	struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
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	u32 frag_count;
};

/* In rx_buffer, we do not need multiple fragments as is a single buffer */
struct qlcnic_rx_buffer {
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	u16 ref_handle;
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	struct sk_buff *skb;
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	struct list_head list;
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	u64 dma;
};

/* Board types */
#define	QLCNIC_GBE	0x01
#define	QLCNIC_XGBE	0x02

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/*
 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
 * adjusted based on configured MTU.
 */
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#define QLCNIC_INTR_COAL_TYPE_RX		1
#define QLCNIC_INTR_COAL_TYPE_TX		2
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#define QLCNIC_INTR_COAL_TYPE_RX_TX		3
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#define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US	3
#define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS	256

#define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US	64
#define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS	64
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#define QLCNIC_INTR_DEFAULT			0x04
#define QLCNIC_CONFIG_INTR_COALESCE		3
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#define QLCNIC_DEV_INFO_SIZE			2
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struct qlcnic_nic_intr_coalesce {
	u8	type;
	u8	sts_ring_mask;
	u16	rx_packets;
	u16	rx_time_us;
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	u16	tx_packets;
	u16	tx_time_us;
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	u16	flag;
	u32	timer_out;
};

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struct qlcnic_83xx_dump_template_hdr {
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	u32	type;
	u32	offset;
	u32	size;
	u32	cap_mask;
	u32	num_entries;
	u32	version;
	u32	timestamp;
	u32	checksum;
	u32	drv_cap_mask;
	u32	sys_info[3];
	u32	saved_state[16];
	u32	cap_sizes[8];
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	u32	ocm_wnd_reg[16];
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	u32	rsvd[0];
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};

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struct qlcnic_82xx_dump_template_hdr {
	u32	type;
	u32	offset;
	u32	size;
	u32	cap_mask;
	u32	num_entries;
	u32	version;
	u32	timestamp;
	u32	checksum;
	u32	drv_cap_mask;
	u32	sys_info[3];
	u32	saved_state[16];
	u32	cap_sizes[8];
	u32	rsvd[7];
	u32	capabilities;
	u32	rsvd1[0];
};

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#define QLC_PEX_DMA_READ_SIZE	(PAGE_SIZE * 16)

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struct qlcnic_fw_dump {
	u8	clr;	/* flag to indicate if dump is cleared */
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	bool	enable; /* enable/disable dump */
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	u32	size;	/* total size of the dump */
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	u32	cap_mask; /* Current capture mask */
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	void	*data;	/* dump data area */
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	void	*tmpl_hdr;
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	dma_addr_t phys_addr;
	void	*dma_buffer;
	bool	use_pex_dma;
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	/* Read only elements which are common between 82xx and 83xx
	 * template header. Update these values immediately after we read
	 * template header from Firmware
	 */
	u32	tmpl_hdr_size;
	u32	version;
	u32	num_entries;
	u32	offset;
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};

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/*
 * One hardware_context{} per adapter
 * contains interrupt info as well shared hardware info.
 */
struct qlcnic_hardware_context {
	void __iomem *pci_base0;
	void __iomem *ocm_win_crb;

	unsigned long pci_len0;

	rwlock_t crb_lock;
	struct mutex mem_lock;

	u8 revision_id;
	u8 pci_func;
	u8 linkup;
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	u8 loopback_state;
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	u8 beacon_state;
	u8 has_link_events;
	u8 fw_type;
	u8 physical_port;
	u8 reset_context;
	u8 msix_supported;
	u8 max_mac_filters;
	u8 mc_enabled;
	u8 max_mc_count;
	u8 diag_test;
	u8 num_msix;
	u8 nic_mode;
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	int diag_cnt;
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	u16 max_uc_count;
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	u16 port_type;
	u16 board_type;
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	u16 supported_type;
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	u16 link_speed;
	u16 link_duplex;
	u16 link_autoneg;
	u16 module_type;

	u16 op_mode;
	u16 switch_mode;
	u16 max_tx_ques;
	u16 max_rx_ques;
	u16 max_mtu;
	u32 msg_enable;
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	u16 total_nic_func;
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	u16 max_pci_func;
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	u32 max_vnic_func;
	u32 total_pci_func;
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	u32 capabilities;
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	u32 extra_capability[3];
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	u32 temp;
	u32 int_vec_bit;
	u32 fw_hal_version;
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	u32 port_config;
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	struct qlcnic_hardware_ops *hw_ops;
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	struct qlcnic_nic_intr_coalesce coal;
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	struct qlcnic_fw_dump fw_dump;
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	struct qlcnic_fdt fdt;
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	struct qlc_83xx_reset reset;
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	struct qlc_83xx_idc idc;
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	struct qlc_83xx_fw_info *fw_info;
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	struct qlcnic_intrpt_config *intr_tbl;
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	struct qlcnic_sriov *sriov;
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	u32 *reg_tbl;
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	u32 *ext_reg_tbl;
	u32 mbox_aen[QLC_83XX_MBX_AEN_CNT];
	u32 mbox_reg[4];
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	struct qlcnic_mailbox *mailbox;
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	u8 extend_lb_time;
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	u8 phys_port_id[ETH_ALEN];
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	u8 lb_mode;
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	u8 vxlan_port_count;
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	u16 vxlan_port;
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	struct device *hwmon_dev;
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	u32 post_mode;
	bool run_post;
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};

struct qlcnic_adapter_stats {
	u64  xmitcalled;
	u64  xmitfinished;
	u64  rxdropped;
	u64  txdropped;
	u64  csummed;
	u64  rx_pkts;
	u64  lro_pkts;
	u64  rxbytes;
	u64  txbytes;
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	u64  lrobytes;
	u64  lso_frames;
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	u64  encap_lso_frames;
	u64  encap_tx_csummed;
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	u64  encap_rx_csummed;
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	u64  xmit_on;
	u64  xmit_off;
	u64  skb_alloc_failure;
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	u64  null_rxbuf;
	u64  rx_dma_map_error;
	u64  tx_dma_map_error;
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	u64  spurious_intr;
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	u64  mac_filter_limit_overrun;
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	u64  mbx_spurious_intr;
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};

/*
 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
 */
struct qlcnic_host_rds_ring {
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	void __iomem *crb_rcv_producer;
	struct rcv_desc *desc_head;
	struct qlcnic_rx_buffer *rx_buf_arr;
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	u32 num_desc;
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	u32 producer;
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	u32 dma_size;
	u32 skb_size;
	u32 flags;
	struct list_head free_list;
	spinlock_t lock;
	dma_addr_t phys_addr;
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} ____cacheline_internodealigned_in_smp;
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struct qlcnic_host_sds_ring {
	u32 consumer;
	u32 num_desc;
	void __iomem *crb_sts_consumer;

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	struct qlcnic_host_tx_ring *tx_ring;
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	struct status_desc *desc_head;
	struct qlcnic_adapter *adapter;
	struct napi_struct napi;
	struct list_head free_list[NUM_RCV_DESC_RINGS];

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	void __iomem *crb_intr_mask;
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	int irq;

	dma_addr_t phys_addr;
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	char name[IFNAMSIZ + 12];
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} ____cacheline_internodealigned_in_smp;
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struct qlcnic_tx_queue_stats {
	u64 xmit_on;
	u64 xmit_off;
	u64 xmit_called;
	u64 xmit_finished;
	u64 tx_bytes;
};

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struct qlcnic_host_tx_ring {
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	int irq;
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	void __iomem *crb_intr_mask;
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	char name[IFNAMSIZ + 12];
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	u16 ctx_id;
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	u32 state;
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	u32 producer;
	u32 sw_consumer;
	u32 num_desc;
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	struct qlcnic_tx_queue_stats tx_stats;
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	void __iomem *crb_cmd_producer;
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	struct cmd_desc_type0 *desc_head;
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	struct qlcnic_adapter *adapter;
	struct napi_struct napi;
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	struct qlcnic_cmd_buffer *cmd_buf_arr;
	__le32 *hw_consumer;

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	dma_addr_t phys_addr;
	dma_addr_t hw_cons_phys_addr;
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	struct netdev_queue *txq;
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	/* Lock to protect Tx descriptors cleanup */
	spinlock_t tx_clean_lock;
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} ____cacheline_internodealigned_in_smp;
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/*
 * Receive context. There is one such structure per instance of the
 * receive processing. Any state information that is relevant to
 * the receive, and is must be in this structure. The global data may be
 * present elsewhere.
 */
struct qlcnic_recv_context {
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	struct qlcnic_host_rds_ring *rds_rings;
	struct qlcnic_host_sds_ring *sds_rings;
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	u32 state;
	u16 context_id;
	u16 virt_port;
};

/* HW context creation */

#define QLCNIC_OS_CRB_RETRY_COUNT	4000

#define QLCNIC_CDRP_CMD_BIT		0x80000000

/*
 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
 * in the crb QLCNIC_CDRP_CRB_OFFSET.
 */
#define QLCNIC_CDRP_FORM_RSP(rsp)	(rsp)
#define QLCNIC_CDRP_IS_RSP(rsp)	(((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)

#define QLCNIC_CDRP_RSP_OK		0x00000001
#define QLCNIC_CDRP_RSP_FAIL		0x00000002
#define QLCNIC_CDRP_RSP_TIMEOUT 	0x00000003

/*
 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
 * the crb QLCNIC_CDRP_CRB_OFFSET.
 */
#define QLCNIC_CDRP_FORM_CMD(cmd)	(QLCNIC_CDRP_CMD_BIT | (cmd))

#define QLCNIC_RCODE_SUCCESS		0
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#define QLCNIC_RCODE_INVALID_ARGS	6
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#define QLCNIC_RCODE_NOT_SUPPORTED	9
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#define QLCNIC_RCODE_NOT_PERMITTED	10
#define QLCNIC_RCODE_NOT_IMPL		15
#define QLCNIC_RCODE_INVALID		16
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#define QLCNIC_RCODE_TIMEOUT		17
#define QLCNIC_DESTROY_CTX_RESET	0

/*
 * Capabilities Announced
 */
#define QLCNIC_CAP0_LEGACY_CONTEXT	(1)
#define QLCNIC_CAP0_LEGACY_MN		(1 << 2)
#define QLCNIC_CAP0_LSO 		(1 << 6)
#define QLCNIC_CAP0_JUMBO_CONTIGUOUS	(1 << 7)
#define QLCNIC_CAP0_LRO_CONTIGUOUS	(1 << 8)
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#define QLCNIC_CAP0_VALIDOFF		(1 << 11)
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#define QLCNIC_CAP0_LRO_MSS		(1 << 21)
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#define QLCNIC_CAP0_TX_MULTI		(1 << 22)
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/*
 * Context state
 */
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#define QLCNIC_HOST_CTX_STATE_FREED	0
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#define QLCNIC_HOST_CTX_STATE_ACTIVE	2

/*
 * Rx context
 */

struct qlcnic_hostrq_sds_ring {
	__le64 host_phys_addr;	/* Ring base addr */
	__le32 ring_size;		/* Ring entries */
	__le16 msi_index;
	__le16 rsvd;		/* Padding */
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} __packed;
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struct qlcnic_hostrq_rds_ring {
	__le64 host_phys_addr;	/* Ring base addr */
	__le64 buff_size;		/* Packet buffer size */
	__le32 ring_size;		/* Ring entries */
	__le32 ring_kind;		/* Class of ring */
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} __packed;
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struct qlcnic_hostrq_rx_ctx {
	__le64 host_rsp_dma_addr;	/* Response dma'd here */
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	__le32 capabilities[4];		/* Flag bit vector */
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	__le32 host_int_crb_mode;	/* Interrupt crb usage */
	__le32 host_rds_crb_mode;	/* RDS crb usage */
	/* These ring offsets are relative to data[0] below */
	__le32 rds_ring_offset;	/* Offset to RDS config */
	__le32 sds_ring_offset;	/* Offset to SDS config */
	__le16 num_rds_rings;	/* Count of RDS rings */
	__le16 num_sds_rings;	/* Count of SDS rings */
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	__le16 valid_field_offset;
	u8  txrx_sds_binding;
	u8  msix_handler;
	u8  reserved[128];      /* reserve space for future expansion*/
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	/* MUST BE 64-bit aligned.
	   The following is packed:
	   - N hostrq_rds_rings
	   - N hostrq_sds_rings */
	char data[0];
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} __packed;
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struct qlcnic_cardrsp_rds_ring{
	__le32 host_producer_crb;	/* Crb to use */
	__le32 rsvd1;		/* Padding */
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} __packed;
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struct qlcnic_cardrsp_sds_ring {
	__le32 host_consumer_crb;	/* Crb to use */
	__le32 interrupt_crb;	/* Crb to use */
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} __packed;
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struct qlcnic_cardrsp_rx_ctx {
	/* These ring offsets are relative to data[0] below */
	__le32 rds_ring_offset;	/* Offset to RDS config */
	__le32 sds_ring_offset;	/* Offset to SDS config */
	__le32 host_ctx_state;	/* Starting State */
	__le32 num_fn_per_port;	/* How many PCI fn share the port */
	__le16 num_rds_rings;	/* Count of RDS rings */
	__le16 num_sds_rings;	/* Count of SDS rings */
	__le16 context_id;		/* Handle for context */
	u8  phys_port;		/* Physical id of port */
	u8  virt_port;		/* Virtual/Logical id of port */
	u8  reserved[128];	/* save space for future expansion */
	/*  MUST BE 64-bit aligned.
	   The following is packed:
	   - N cardrsp_rds_rings
	   - N cardrs_sds_rings */
	char data[0];
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} __packed;
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#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings)	\
	(sizeof(HOSTRQ_RX) + 					\
	(rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) +		\
	(sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))

#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) 	\
	(sizeof(CARDRSP_RX) + 					\
	(rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + 		\
	(sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))

/*
 * Tx context
 */

struct qlcnic_hostrq_cds_ring {
	__le64 host_phys_addr;	/* Ring base addr */
	__le32 ring_size;		/* Ring entries */
	__le32 rsvd;		/* Padding */
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} __packed;
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struct qlcnic_hostrq_tx_ctx {
	__le64 host_rsp_dma_addr;	/* Response dma'd here */
	__le64 cmd_cons_dma_addr;	/*  */
	__le64 dummy_dma_addr;	/*  */
	__le32 capabilities[4];	/* Flag bit vector */
	__le32 host_int_crb_mode;	/* Interrupt crb usage */
	__le32 rsvd1;		/* Padding */
	__le16 rsvd2;		/* Padding */
	__le16 interrupt_ctl;
	__le16 msi_index;
	__le16 rsvd3;		/* Padding */
	struct qlcnic_hostrq_cds_ring cds_ring;	/* Desc of cds ring */
	u8  reserved[128];	/* future expansion */
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} __packed;
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struct qlcnic_cardrsp_cds_ring {
	__le32 host_producer_crb;	/* Crb to use */
	__le32 interrupt_crb;	/* Crb to use */
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} __packed;
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struct qlcnic_cardrsp_tx_ctx {
	__le32 host_ctx_state;	/* Starting state */
	__le16 context_id;		/* Handle for context */
	u8  phys_port;		/* Physical id of port */
	u8  virt_port;		/* Virtual/Logical id of port */
	struct qlcnic_cardrsp_cds_ring cds_ring;	/* Card cds settings */
	u8  reserved[128];	/* future expansion */
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} __packed;
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#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX)	(sizeof(HOSTRQ_TX))
#define SIZEOF_CARDRSP_TX(CARDRSP_TX)	(sizeof(CARDRSP_TX))

/* CRB */

#define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE	0
#define QLCNIC_HOST_RDS_CRB_MODE_SHARED	1
#define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM	2
#define QLCNIC_HOST_RDS_CRB_MODE_MAX	3

#define QLCNIC_HOST_INT_CRB_MODE_UNIQUE	0
#define QLCNIC_HOST_INT_CRB_MODE_SHARED	1
#define QLCNIC_HOST_INT_CRB_MODE_NORX	2
#define QLCNIC_HOST_INT_CRB_MODE_NOTX	3
#define QLCNIC_HOST_INT_CRB_MODE_NORXTX	4


/* MAC */

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#define MC_COUNT_P3P	38
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#define QLCNIC_MAC_NOOP	0
#define QLCNIC_MAC_ADD	1
#define QLCNIC_MAC_DEL	2
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#define QLCNIC_MAC_VLAN_ADD	3
#define QLCNIC_MAC_VLAN_DEL	4
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enum qlcnic_mac_type {
	QLCNIC_UNICAST_MAC,
	QLCNIC_MULTICAST_MAC,
	QLCNIC_BROADCAST_MAC,
};

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struct qlcnic_mac_vlan_list {
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	struct list_head list;
	uint8_t mac_addr[ETH_ALEN+2];
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	u16 vlan_id;
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	enum qlcnic_mac_type mac_type;
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};

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/* MAC Learn */
#define NO_MAC_LEARN		0
#define DRV_MAC_LEARN		1
#define FDB_MAC_LEARN		2

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#define QLCNIC_HOST_REQUEST	0x13
#define QLCNIC_REQUEST		0x14

#define QLCNIC_MAC_EVENT	0x1

#define QLCNIC_IP_UP		2
#define QLCNIC_IP_DOWN		3

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#define QLCNIC_ILB_MODE		0x1
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#define QLCNIC_ELB_MODE		0x2
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#define QLCNIC_LB_MODE_MASK	0x3
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#define QLCNIC_LINKEVENT	0x1
#define QLCNIC_LB_RESPONSE	0x2
#define QLCNIC_IS_LB_CONFIGURED(VAL)	\
		(VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))

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/*
 * Driver --> Firmware
 */
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#define QLCNIC_H2C_OPCODE_CONFIG_RSS			0x1
#define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE		0x3
#define QLCNIC_H2C_OPCODE_CONFIG_LED			0x4
#define QLCNIC_H2C_OPCODE_LRO_REQUEST			0x7
#define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE		0xc
#define QLCNIC_H2C_OPCODE_CONFIG_IPADDR		0x12
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#define QLCNIC_H2C_OPCODE_GET_LINKEVENT		0x15
#define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING		0x17
#define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO		0x18
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#define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK		0x13

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/*
 * Firmware --> Driver
 */

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#define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK		0x8f
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#define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE	0x8D
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#define QLCNIC_C2H_OPCODE_GET_DCB_AEN			0x90
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#define VPORT_MISS_MODE_DROP		0 /* drop all unmatched */
#define VPORT_MISS_MODE_ACCEPT_ALL	1 /* accept all packets */
#define VPORT_MISS_MODE_ACCEPT_MULTI	2 /* accept unmatched multicast */

#define QLCNIC_LRO_REQUEST_CLEANUP	4

/* Capabilites received */
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#define QLCNIC_FW_CAPABILITY_TSO		BIT_1
#define QLCNIC_FW_CAPABILITY_BDG		BIT_8
#define QLCNIC_FW_CAPABILITY_FVLANTX		BIT_9
#define QLCNIC_FW_CAPABILITY_HW_LRO		BIT_10
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#define QLCNIC_FW_CAPABILITY_2_MULTI_TX		BIT_4
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#define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK	BIT_27
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#define QLCNIC_FW_CAPABILITY_MORE_CAPS		BIT_31

#define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG	BIT_2
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#define QLCNIC_FW_CAP2_HW_LRO_IPV6		BIT_3
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#define QLCNIC_FW_CAPABILITY_SET_DRV_VER	BIT_5
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#define QLCNIC_FW_CAPABILITY_2_BEACON		BIT_7
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#define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG	BIT_9
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#define QLCNIC_FW_CAPABILITY_2_EXT_ISCSI_DUMP	BIT_13
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#define QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD	BIT_0
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#define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD	BIT_1
#define QLCNIC_83XX_FW_CAPAB_ENCAP_CKO_OFFLOAD	BIT_4

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/* module types */
#define LINKEVENT_MODULE_NOT_PRESENT			1
#define LINKEVENT_MODULE_OPTICAL_UNKNOWN		2
#define LINKEVENT_MODULE_OPTICAL_SRLR			3
#define LINKEVENT_MODULE_OPTICAL_LRM			4
#define LINKEVENT_MODULE_OPTICAL_SFP_1G 		5
#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE	6
#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN	7
#define LINKEVENT_MODULE_TWINAX 			8

#define LINKSPEED_10GBPS	10000
#define LINKSPEED_1GBPS 	1000
#define LINKSPEED_100MBPS	100
#define LINKSPEED_10MBPS	10

#define LINKSPEED_ENCODED_10MBPS	0
#define LINKSPEED_ENCODED_100MBPS	1
#define LINKSPEED_ENCODED_1GBPS 	2

#define LINKEVENT_AUTONEG_DISABLED	0
#define LINKEVENT_AUTONEG_ENABLED	1

#define LINKEVENT_HALF_DUPLEX		0
#define LINKEVENT_FULL_DUPLEX		1

#define LINKEVENT_LINKSPEED_MBPS	0
#define LINKEVENT_LINKSPEED_ENCODED	1

/* firmware response header:
 *	63:58 - message type
 *	57:56 - owner
 *	55:53 - desc count
 *	52:48 - reserved
 *	47:40 - completion id
 *	39:32 - opcode
 *	31:16 - error code
 *	15:00 - reserved
 */
#define qlcnic_get_nic_msg_opcode(msg_hdr)	\
	((msg_hdr >> 32) & 0xFF)

struct qlcnic_fw_msg {
	union {
		struct {
			u64 hdr;
			u64 body[7];
		};
		u64 words[8];
	};
};

struct qlcnic_nic_req {
	__le64 qhdr;
	__le64 req_hdr;
	__le64 words[6];
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} __packed;
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struct qlcnic_mac_req {
	u8 op;
	u8 tag;
	u8 mac_addr[6];
};

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struct qlcnic_vlan_req {
	__le16 vlan_id;
	__le16 rsvd[3];
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} __packed;
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struct qlcnic_ipaddr {
	__be32 ipv4;
	__be32 ipv6[4];
};

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#define QLCNIC_MSI_ENABLED		0x02
#define QLCNIC_MSIX_ENABLED		0x04
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#define QLCNIC_LRO_ENABLED		0x01
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#define QLCNIC_LRO_DISABLED		0x00
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#define QLCNIC_BRIDGE_ENABLED       	0X10
#define QLCNIC_DIAG_ENABLED		0x20
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#define QLCNIC_ESWITCH_ENABLED		0x40
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#define QLCNIC_ADAPTER_INITIALIZED	0x80
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#define QLCNIC_TAGGING_ENABLED		0x100
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#define QLCNIC_MACSPOOF			0x200
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#define QLCNIC_MAC_OVERRIDE_DISABLED	0x400
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#define QLCNIC_PROMISC_DISABLED		0x800
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#define QLCNIC_NEED_FLR			0x1000
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#define QLCNIC_FW_RESET_OWNER		0x2000
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#define QLCNIC_FW_HANG			0x4000
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#define QLCNIC_FW_LRO_MSS_CAP		0x8000
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#define QLCNIC_TX_INTR_SHARED		0x10000
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#define QLCNIC_APP_CHANGED_FLAGS	0x20000
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#define QLCNIC_HAS_PHYS_PORT_ID		0x40000
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#define QLCNIC_TSS_RSS			0x80000
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#define QLCNIC_ADD_VXLAN_PORT		0x100000
#define QLCNIC_DEL_VXLAN_PORT		0x200000
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#define QLCNIC_VLAN_FILTERING		0x800000

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#define QLCNIC_IS_MSI_FAMILY(adapter) \
	((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
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#define QLCNIC_IS_TSO_CAPABLE(adapter)  \
	((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
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#define QLCNIC_BEACON_EANBLE		0xC
#define QLCNIC_BEACON_DISABLE		0xD

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#define QLCNIC_BEACON_ON		2
#define QLCNIC_BEACON_OFF		0

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#define QLCNIC_MSIX_TBL_SPACE		8192
#define QLCNIC_PCI_REG_MSIX_TBL 	0x44
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#define QLCNIC_MSIX_TBL_PGSIZE		4096
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#define QLCNIC_ADAPTER_UP_MAGIC 777

#define __QLCNIC_FW_ATTACHED		0
#define __QLCNIC_DEV_UP 		1
#define __QLCNIC_RESETTING		2
#define __QLCNIC_START_FW 		4
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#define __QLCNIC_AER			5
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#define __QLCNIC_DIAG_RES_ALLOC		6
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#define __QLCNIC_LED_ENABLE		7
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#define __QLCNIC_ELB_INPROGRESS		8
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#define __QLCNIC_MULTI_TX_UNIQUE	9
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#define __QLCNIC_SRIOV_ENABLE		10
#define __QLCNIC_SRIOV_CAPABLE		11
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#define __QLCNIC_MBX_POLL_ENABLE	12
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#define __QLCNIC_DIAG_MODE		13
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#define __QLCNIC_MAINTENANCE_MODE	16
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#define QLCNIC_INTERRUPT_TEST		1
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#define QLCNIC_LOOPBACK_TEST		2
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#define QLCNIC_LED_TEST		3
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#define QLCNIC_FILTER_AGE	80
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#define QLCNIC_READD_AGE	20
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#define QLCNIC_LB_MAX_FILTERS	64
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#define QLCNIC_LB_BUCKET_SIZE	32
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#define QLCNIC_ILB_MAX_RCV_LOOP	10
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struct qlcnic_filter {
	struct hlist_node fnode;
	u8 faddr[ETH_ALEN];
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	u16 vlan_id;
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	unsigned long ftime;
};

struct qlcnic_filter_hash {
	struct hlist_head *fhead;
	u8 fnum;
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	u16 fmax;
	u16 fbucket_size;
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};

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/* Mailbox specific data structures */
struct qlcnic_mailbox {
	struct workqueue_struct	*work_q;
	struct qlcnic_adapter	*adapter;
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	const struct qlcnic_mbx_ops *ops;
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	struct work_struct	work;
	struct completion	completion;
	struct list_head	cmd_q;
	unsigned long		status;
	spinlock_t		queue_lock;	/* Mailbox queue lock */
	spinlock_t		aen_lock;	/* Mailbox response/AEN lock */
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	u32			rsp_status;
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	u32			num_cmds;
};

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struct qlcnic_adapter {
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	struct qlcnic_hardware_context *ahw;
	struct qlcnic_recv_context *recv_ctx;
	struct qlcnic_host_tx_ring *tx_ring;
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	struct net_device *netdev;
	struct pci_dev *pdev;

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	unsigned long state;
	u32 flags;
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	u16 num_txd;
	u16 num_rxd;
	u16 num_jumbo_rxd;
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	u16 max_rxd;
	u16 max_jumbo_rxd;
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	u8 max_rds_rings;
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	u8 max_sds_rings; /* max sds rings supported by adapter */
	u8 max_tx_rings;  /* max tx rings supported by adapter */

	u8 drv_tx_rings;  /* max tx rings supported by driver */
	u8 drv_sds_rings; /* max sds rings supported by driver */

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	u8 drv_tss_rings; /* tss ring input */
	u8 drv_rss_rings; /* rss ring input */

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	u8 rx_csum;
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	u8 portnum;

	u8 fw_wait_cnt;
	u8 fw_fail_cnt;
	u8 tx_timeo_cnt;
	u8 need_fw_reset;
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	u8 reset_ctx_cnt;
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	u16 is_up;
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	u16 rx_pvid;
	u16 tx_pvid;
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	u32 irq;
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	u32 heartbeat;
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	u8 dev_state;
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	u8 reset_ack_timeo;
	u8 dev_init_timeo;
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	u8 mac_addr[ETH_ALEN];

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	u64 dev_rst_time;
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	bool drv_mac_learn;
	bool fdb_mac_learn;
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	bool rx_mac_learn;
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	unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
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	u8 flash_mfg_id;
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	struct qlcnic_npar_info *npars;
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	struct qlcnic_eswitch *eswitch;
	struct qlcnic_nic_template *nic_ops;

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	struct qlcnic_adapter_stats stats;
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	struct list_head mac_list;
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	void __iomem	*tgt_mask_reg;
	void __iomem	*tgt_status_reg;
	void __iomem	*crb_int_state_reg;
	void __iomem	*isr_int_vec;

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	struct msix_entry *msix_entries;
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	struct workqueue_struct *qlcnic_wq;
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	struct delayed_work fw_work;
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	struct delayed_work idc_aen_work;
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	struct delayed_work mbx_poll_work;
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	struct qlcnic_dcb *dcb;
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	struct qlcnic_filter_hash fhash;
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	struct qlcnic_filter_hash rx_fhash;
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	struct list_head vf_mc_list;
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	spinlock_t mac_learn_lock;
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	/* spinlock for catching rcv filters for eswitch traffic */
	spinlock_t rx_mac_learn_lock;
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	u32 file_prd_off;	/*File fw product offset*/
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	u32 fw_version;
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	u32 offload_flags;
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	const struct firmware *fw;
};

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struct qlcnic_info_le {
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	__le16	pci_func;
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	__le16	op_mode;	/* 1 = Priv, 2 = NP, 3 = NP passthru */
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	__le16	phys_port;
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	__le16	switch_mode;	/* 0 = disabled, 1 = int, 2 = ext */
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	__le32	capabilities;
	u8	max_mac_filters;
	u8	reserved1;
	__le16	max_mtu;

	__le16	max_tx_ques;
	__le16	max_rx_ques;
	__le16	min_tx_bw;
	__le16	max_tx_bw;
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	__le32  op_type;
	__le16  max_bw_reg_offset;
	__le16  max_linkspeed_reg_offset;
	__le32  capability1;
	__le32  capability2;
	__le32  capability3;
	__le16  max_tx_mac_filters;
	__le16  max_rx_mcast_mac_filters;
	__le16  max_rx_ucast_mac_filters;
	__le16  max_rx_ip_addr;
	__le16  max_rx_lro_flow;
	__le16  max_rx_status_rings;
	__le16  max_rx_buf_rings;
	__le16  max_tx_vlan_keys;
	u8      total_pf;
	u8      total_rss_engines;
	__le16  max_vports;
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	__le16	linkstate_reg_offset;
	__le16	bit_offsets;
	__le16  max_local_ipv6_addrs;
	__le16  max_remote_ipv6_addrs;
	u8	reserved2[56];
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} __packed;
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struct qlcnic_info {
	u16	pci_func;
	u16	op_mode;
	u16	phys_port;
	u16	switch_mode;
	u32	capabilities;
	u8	max_mac_filters;
	u16	max_mtu;
	u16	max_tx_ques;
	u16	max_rx_ques;
	u16	min_tx_bw;
	u16	max_tx_bw;
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	u32	op_type;
	u16	max_bw_reg_offset;
	u16	max_linkspeed_reg_offset;
	u32	capability1;
	u32	capability2;
	u32	capability3;
	u16	max_tx_mac_filters;
	u16	max_rx_mcast_mac_filters;
	u16	max_rx_ucast_mac_filters;
	u16	max_rx_ip_addr;
	u16	max_rx_lro_flow;
	u16	max_rx_status_rings;
	u16	max_rx_buf_rings;
	u16	max_tx_vlan_keys;
	u8      total_pf;
	u8      total_rss_engines;
	u16	max_vports;
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	u16	linkstate_reg_offset;
	u16	bit_offsets;
	u16	max_local_ipv6_addrs;
	u16	max_remote_ipv6_addrs;
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};
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struct qlcnic_pci_info_le {
	__le16	id;		/* pci function id */
	__le16	active;		/* 1 = Enabled */
	__le16	type;		/* 1 = NIC, 2 = FCoE, 3 = iSCSI */
	__le16	default_port;	/* default port number */

	__le16	tx_min_bw;	/* Multiple of 100mbpc */
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	__le16	tx_max_bw;
	__le16	reserved1[2];

	u8	mac[ETH_ALEN];
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	__le16  func_count;
	u8      reserved2[104];

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} __packed;
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struct qlcnic_pci_info {
	u16	id;
	u16	active;
	u16	type;
	u16	default_port;
	u16	tx_min_bw;
	u16	tx_max_bw;
	u8	mac[ETH_ALEN];
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	u16  func_count;
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};

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struct qlcnic_npar_info {
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	bool	eswitch_status;
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	u16	pvid;
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	u16	min_bw;
	u16	max_bw;
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	u8	phy_port;
	u8	type;
	u8	active;
	u8	enable_pm;
	u8	dest_npar;
	u8	discard_tagged;
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	u8	mac_override;
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	u8	mac_anti_spoof;
	u8	promisc_mode;
	u8	offload_flags;
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	u8      pci_func;
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	u8      mac[ETH_ALEN];
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};
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struct qlcnic_eswitch {
	u8	port;
	u8	active_vports;
	u8	active_vlans;
	u8	active_ucast_filters;
	u8	max_ucast_filters;
	u8	max_active_vlans;

	u32	flags;
#define QLCNIC_SWITCH_ENABLE		BIT_1
#define QLCNIC_SWITCH_VLAN_FILTERING	BIT_2
#define QLCNIC_SWITCH_PROMISC_MODE	BIT_3
#define QLCNIC_SWITCH_PORT_MIRRORING	BIT_4
};

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#define MAX_BW			100	/* % of link speed */
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#define MIN_BW			1	/* % of link speed */
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#define MAX_VLAN_ID		4095
#define MIN_VLAN_ID		2
#define DEFAULT_MAC_LEARN	1

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#define IS_VALID_VLAN(vlan)	(vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
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#define IS_VALID_BW(bw)		(bw <= MAX_BW)
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struct qlcnic_pci_func_cfg {
	u16	func_type;
	u16	min_bw;
	u16	max_bw;
	u16	port_num;
	u8	pci_func;
	u8	func_state;
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	u8	def_mac_addr[ETH_ALEN];
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};

struct qlcnic_npar_func_cfg {
	u32	fw_capab;
	u16	port_num;
	u16	min_bw;
	u16	max_bw;
	u16	max_tx_queues;
	u16	max_rx_queues;
	u8	pci_func;
	u8	op_mode;
};

struct qlcnic_pm_func_cfg {
	u8	pci_func;
	u8	action;
	u8	dest_npar;
	u8	reserved[5];
};

struct qlcnic_esw_func_cfg {
	u16	vlan_id;
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	u8	op_mode;
	u8	op_type;
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	u8	pci_func;
	u8	host_vlan_tag;
	u8	promisc_mode;
	u8	discard_tagged;
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	u8	mac_override;
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	u8	mac_anti_spoof;
	u8	offload_flags;
	u8	reserved[5];
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};

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#define QLCNIC_STATS_VERSION		1
#define QLCNIC_STATS_PORT		1
#define QLCNIC_STATS_ESWITCH		2
#define QLCNIC_QUERY_RX_COUNTER		0
#define QLCNIC_QUERY_TX_COUNTER		1
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#define QLCNIC_STATS_NOT_AVAIL	0xffffffffffffffffULL
#define QLCNIC_FILL_STATS(VAL1) \
	(((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
#define QLCNIC_MAC_STATS 1
#define QLCNIC_ESW_STATS 2
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#define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
do {	\
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	if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \
	    ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
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		(VAL1) = (VAL2); \
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	else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \
		 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
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			(VAL1) += (VAL2); \
} while (0)

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struct qlcnic_mac_statistics_le {
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