smsc75xx.c 57 KB
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 /***************************************************************************
 *
 * Copyright (C) 2007-2010 SMSC
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, see <http://www.gnu.org/licenses/>.
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 *
 *****************************************************************************/

#include <linux/module.h>
#include <linux/kmod.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/usb.h>
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#include <linux/bitrev.h>
#include <linux/crc16.h>
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#include <linux/crc32.h>
#include <linux/usb/usbnet.h>
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#include <linux/slab.h>
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#include "smsc75xx.h"

#define SMSC_CHIPNAME			"smsc75xx"
#define SMSC_DRIVER_VERSION		"1.0.0"
#define HS_USB_PKT_SIZE			(512)
#define FS_USB_PKT_SIZE			(64)
#define DEFAULT_HS_BURST_CAP_SIZE	(16 * 1024 + 5 * HS_USB_PKT_SIZE)
#define DEFAULT_FS_BURST_CAP_SIZE	(6 * 1024 + 33 * FS_USB_PKT_SIZE)
#define DEFAULT_BULK_IN_DELAY		(0x00002000)
#define MAX_SINGLE_PACKET_SIZE		(9000)
#define LAN75XX_EEPROM_MAGIC		(0x7500)
#define EEPROM_MAC_OFFSET		(0x01)
#define DEFAULT_TX_CSUM_ENABLE		(true)
#define DEFAULT_RX_CSUM_ENABLE		(true)
#define SMSC75XX_INTERNAL_PHY_ID	(1)
#define SMSC75XX_TX_OVERHEAD		(8)
#define MAX_RX_FIFO_SIZE		(20 * 1024)
#define MAX_TX_FIFO_SIZE		(12 * 1024)
#define USB_VENDOR_ID_SMSC		(0x0424)
#define USB_PRODUCT_ID_LAN7500		(0x7500)
#define USB_PRODUCT_ID_LAN7505		(0x7505)
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#define RXW_PADDING			2
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#define SUPPORTED_WAKE			(WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
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					 WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
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#define SUSPEND_SUSPEND0		(0x01)
#define SUSPEND_SUSPEND1		(0x02)
#define SUSPEND_SUSPEND2		(0x04)
#define SUSPEND_SUSPEND3		(0x08)
#define SUSPEND_ALLMODES		(SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
					 SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)

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struct smsc75xx_priv {
	struct usbnet *dev;
	u32 rfe_ctl;
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	u32 wolopts;
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	u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
	struct mutex dataport_mutex;
	spinlock_t rfe_ctl_lock;
	struct work_struct set_multicast;
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	u8 suspend_flags;
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};

struct usb_context {
	struct usb_ctrlrequest req;
	struct usbnet *dev;
};

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static bool turbo_mode = true;
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module_param(turbo_mode, bool, 0644);
MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");

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static int smsc75xx_link_ok_nopm(struct usbnet *dev);
static int smsc75xx_phy_gig_workaround(struct usbnet *dev);

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static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
					    u32 *data, int in_pm)
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{
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	u32 buf;
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	int ret;
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	int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
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	BUG_ON(!dev);

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	if (!in_pm)
		fn = usbnet_read_cmd;
	else
		fn = usbnet_read_cmd_nopm;

	ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
		 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
		 0, index, &buf, 4);
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	if (unlikely(ret < 0))
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		netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
			    index, ret);
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	le32_to_cpus(&buf);
	*data = buf;
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	return ret;
}

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static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
					     u32 data, int in_pm)
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{
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	u32 buf;
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	int ret;
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	int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
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	BUG_ON(!dev);

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	if (!in_pm)
		fn = usbnet_write_cmd;
	else
		fn = usbnet_write_cmd_nopm;

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	buf = data;
	cpu_to_le32s(&buf);
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	ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
		 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
		 0, index, &buf, 4);
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	if (unlikely(ret < 0))
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		netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
			    index, ret);
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	return ret;
}

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static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
					       u32 *data)
{
	return __smsc75xx_read_reg(dev, index, data, 1);
}

static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
						u32 data)
{
	return __smsc75xx_write_reg(dev, index, data, 1);
}

static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
					  u32 *data)
{
	return __smsc75xx_read_reg(dev, index, data, 0);
}

static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
					   u32 data)
{
	return __smsc75xx_write_reg(dev, index, data, 0);
}

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/* Loop until the read is completed with timeout
 * called with phy_mutex held */
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static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
						     int in_pm)
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{
	unsigned long start_time = jiffies;
	u32 val;
	int ret;

	do {
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		ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
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		if (ret < 0) {
			netdev_warn(dev->net, "Error reading MII_ACCESS\n");
			return ret;
		}
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		if (!(val & MII_ACCESS_BUSY))
			return 0;
	} while (!time_after(jiffies, start_time + HZ));

	return -EIO;
}

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static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
				int in_pm)
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{
	struct usbnet *dev = netdev_priv(netdev);
	u32 val, addr;
	int ret;

	mutex_lock(&dev->phy_mutex);

	/* confirm MII not busy */
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	ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
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	if (ret < 0) {
		netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
		goto done;
	}
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	/* set the address, index & direction (read from PHY) */
	phy_id &= dev->mii.phy_id_mask;
	idx &= dev->mii.reg_num_mask;
	addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
		| ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
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		| MII_ACCESS_READ | MII_ACCESS_BUSY;
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	ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
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	if (ret < 0) {
		netdev_warn(dev->net, "Error writing MII_ACCESS\n");
		goto done;
	}
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	ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
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	if (ret < 0) {
		netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
		goto done;
	}
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	ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
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	if (ret < 0) {
		netdev_warn(dev->net, "Error reading MII_DATA\n");
		goto done;
	}
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	ret = (u16)(val & 0xFFFF);

done:
	mutex_unlock(&dev->phy_mutex);
	return ret;
}

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static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
				  int idx, int regval, int in_pm)
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{
	struct usbnet *dev = netdev_priv(netdev);
	u32 val, addr;
	int ret;

	mutex_lock(&dev->phy_mutex);

	/* confirm MII not busy */
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	ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
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	if (ret < 0) {
		netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
		goto done;
	}
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	val = regval;
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	ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
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	if (ret < 0) {
		netdev_warn(dev->net, "Error writing MII_DATA\n");
		goto done;
	}
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	/* set the address, index & direction (write to PHY) */
	phy_id &= dev->mii.phy_id_mask;
	idx &= dev->mii.reg_num_mask;
	addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
		| ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
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		| MII_ACCESS_WRITE | MII_ACCESS_BUSY;
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	ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
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	if (ret < 0) {
		netdev_warn(dev->net, "Error writing MII_ACCESS\n");
		goto done;
	}
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	ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
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	if (ret < 0) {
		netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
		goto done;
	}
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done:
	mutex_unlock(&dev->phy_mutex);
}

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static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
				   int idx)
{
	return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
}

static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
				     int idx, int regval)
{
	__smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
}

static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
{
	return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
}

static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
				int regval)
{
	__smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
}

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static int smsc75xx_wait_eeprom(struct usbnet *dev)
{
	unsigned long start_time = jiffies;
	u32 val;
	int ret;

	do {
		ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
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		if (ret < 0) {
			netdev_warn(dev->net, "Error reading E2P_CMD\n");
			return ret;
		}
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		if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
			break;
		udelay(40);
	} while (!time_after(jiffies, start_time + HZ));

	if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
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		netdev_warn(dev->net, "EEPROM read operation timeout\n");
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		return -EIO;
	}

	return 0;
}

static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
{
	unsigned long start_time = jiffies;
	u32 val;
	int ret;

	do {
		ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
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		if (ret < 0) {
			netdev_warn(dev->net, "Error reading E2P_CMD\n");
			return ret;
		}
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		if (!(val & E2P_CMD_BUSY))
			return 0;

		udelay(40);
	} while (!time_after(jiffies, start_time + HZ));

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	netdev_warn(dev->net, "EEPROM is busy\n");
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	return -EIO;
}

static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
				u8 *data)
{
	u32 val;
	int i, ret;

	BUG_ON(!dev);
	BUG_ON(!data);

	ret = smsc75xx_eeprom_confirm_not_busy(dev);
	if (ret)
		return ret;

	for (i = 0; i < length; i++) {
		val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
		ret = smsc75xx_write_reg(dev, E2P_CMD, val);
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		if (ret < 0) {
			netdev_warn(dev->net, "Error writing E2P_CMD\n");
			return ret;
		}
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		ret = smsc75xx_wait_eeprom(dev);
		if (ret < 0)
			return ret;

		ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
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		if (ret < 0) {
			netdev_warn(dev->net, "Error reading E2P_DATA\n");
			return ret;
		}
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		data[i] = val & 0xFF;
		offset++;
	}

	return 0;
}

static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
				 u8 *data)
{
	u32 val;
	int i, ret;

	BUG_ON(!dev);
	BUG_ON(!data);

	ret = smsc75xx_eeprom_confirm_not_busy(dev);
	if (ret)
		return ret;

	/* Issue write/erase enable command */
	val = E2P_CMD_BUSY | E2P_CMD_EWEN;
	ret = smsc75xx_write_reg(dev, E2P_CMD, val);
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	if (ret < 0) {
		netdev_warn(dev->net, "Error writing E2P_CMD\n");
		return ret;
	}
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	ret = smsc75xx_wait_eeprom(dev);
	if (ret < 0)
		return ret;

	for (i = 0; i < length; i++) {

		/* Fill data register */
		val = data[i];
		ret = smsc75xx_write_reg(dev, E2P_DATA, val);
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		if (ret < 0) {
			netdev_warn(dev->net, "Error writing E2P_DATA\n");
			return ret;
		}
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		/* Send "write" command */
		val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
		ret = smsc75xx_write_reg(dev, E2P_CMD, val);
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		if (ret < 0) {
			netdev_warn(dev->net, "Error writing E2P_CMD\n");
			return ret;
		}
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		ret = smsc75xx_wait_eeprom(dev);
		if (ret < 0)
			return ret;

		offset++;
	}

	return 0;
}

static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
{
	int i, ret;

	for (i = 0; i < 100; i++) {
		u32 dp_sel;
		ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
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		if (ret < 0) {
			netdev_warn(dev->net, "Error reading DP_SEL\n");
			return ret;
		}
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		if (dp_sel & DP_SEL_DPRDY)
			return 0;

		udelay(40);
	}

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	netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
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	return -EIO;
}

static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
				   u32 length, u32 *buf)
{
	struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
	u32 dp_sel;
	int i, ret;

	mutex_lock(&pdata->dataport_mutex);

	ret = smsc75xx_dataport_wait_not_busy(dev);
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	if (ret < 0) {
		netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
		goto done;
	}
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	ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
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	if (ret < 0) {
		netdev_warn(dev->net, "Error reading DP_SEL\n");
		goto done;
	}
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	dp_sel &= ~DP_SEL_RSEL;
	dp_sel |= ram_select;
	ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
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	if (ret < 0) {
		netdev_warn(dev->net, "Error writing DP_SEL\n");
		goto done;
	}
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	for (i = 0; i < length; i++) {
		ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
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		if (ret < 0) {
			netdev_warn(dev->net, "Error writing DP_ADDR\n");
			goto done;
		}
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		ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
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		if (ret < 0) {
			netdev_warn(dev->net, "Error writing DP_DATA\n");
			goto done;
		}
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		ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
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		if (ret < 0) {
			netdev_warn(dev->net, "Error writing DP_CMD\n");
			goto done;
		}
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		ret = smsc75xx_dataport_wait_not_busy(dev);
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		if (ret < 0) {
			netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
			goto done;
		}
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	}

done:
	mutex_unlock(&pdata->dataport_mutex);
	return ret;
}

/* returns hash bit number for given MAC address */
static u32 smsc75xx_hash(char addr[ETH_ALEN])
{
	return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
}

static void smsc75xx_deferred_multicast_write(struct work_struct *param)
{
	struct smsc75xx_priv *pdata =
		container_of(param, struct smsc75xx_priv, set_multicast);
	struct usbnet *dev = pdata->dev;
	int ret;

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	netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
		  pdata->rfe_ctl);
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	smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
		DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);

	ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
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	if (ret < 0)
		netdev_warn(dev->net, "Error writing RFE_CRL\n");
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}

static void smsc75xx_set_multicast(struct net_device *netdev)
{
	struct usbnet *dev = netdev_priv(netdev);
	struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
	unsigned long flags;
	int i;

	spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);

	pdata->rfe_ctl &=
		~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
	pdata->rfe_ctl |= RFE_CTL_AB;

	for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
		pdata->multicast_hash_table[i] = 0;

	if (dev->net->flags & IFF_PROMISC) {
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		netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
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		pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
	} else if (dev->net->flags & IFF_ALLMULTI) {
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		netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
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		pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
	} else if (!netdev_mc_empty(dev->net)) {
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		struct netdev_hw_addr *ha;
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		netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
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		pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;

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		netdev_for_each_mc_addr(ha, netdev) {
			u32 bitnum = smsc75xx_hash(ha->addr);
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			pdata->multicast_hash_table[bitnum / 32] |=
				(1 << (bitnum % 32));
		}
	} else {
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		netif_dbg(dev, drv, dev->net, "receive own packets only\n");
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		pdata->rfe_ctl |= RFE_CTL_DPF;
	}

	spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);

	/* defer register writes to a sleepable context */
	schedule_work(&pdata->set_multicast);
}

static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
					    u16 lcladv, u16 rmtadv)
{
	u32 flow = 0, fct_flow = 0;
	int ret;

	if (duplex == DUPLEX_FULL) {
		u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);

		if (cap & FLOW_CTRL_TX) {
			flow = (FLOW_TX_FCEN | 0xFFFF);
			/* set fct_flow thresholds to 20% and 80% */
			fct_flow = (8 << 8) | 32;
		}

		if (cap & FLOW_CTRL_RX)
			flow |= FLOW_RX_FCEN;

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		netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
			  (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
			  (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
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	} else {
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		netif_dbg(dev, link, dev->net, "half duplex\n");
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	}

	ret = smsc75xx_write_reg(dev, FLOW, flow);
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	if (ret < 0) {
		netdev_warn(dev->net, "Error writing FLOW\n");
		return ret;
	}
625 626

	ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
627 628 629 630
	if (ret < 0) {
		netdev_warn(dev->net, "Error writing FCT_FLOW\n");
		return ret;
	}
631 632 633 634 635 636 637

	return 0;
}

static int smsc75xx_link_reset(struct usbnet *dev)
{
	struct mii_if_info *mii = &dev->mii;
638
	struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
639 640 641
	u16 lcladv, rmtadv;
	int ret;

642
	/* write to clear phy interrupt status */
643 644
	smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
		PHY_INT_SRC_CLEAR_ALL);
645 646

	ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
647 648 649 650
	if (ret < 0) {
		netdev_warn(dev->net, "Error writing INT_STS\n");
		return ret;
	}
651 652 653 654 655 656

	mii_check_media(mii, 1, 1);
	mii_ethtool_gset(&dev->mii, &ecmd);
	lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
	rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);

657 658
	netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
		  ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
659 660 661 662 663 664 665 666 667

	return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
}

static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
{
	u32 intdata;

	if (urb->actual_length != 4) {
668 669
		netdev_warn(dev->net, "unexpected urb length %d\n",
			    urb->actual_length);
670 671 672 673 674 675
		return;
	}

	memcpy(&intdata, urb->transfer_buffer, 4);
	le32_to_cpus(&intdata);

676
	netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
677 678 679 680

	if (intdata & INT_ENP_PHY_INT)
		usbnet_defer_kevent(dev, EVENT_LINK_RESET);
	else
681 682
		netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
			    intdata);
683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705
}

static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
{
	return MAX_EEPROM_SIZE;
}

static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
				       struct ethtool_eeprom *ee, u8 *data)
{
	struct usbnet *dev = netdev_priv(netdev);

	ee->magic = LAN75XX_EEPROM_MAGIC;

	return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
}

static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
				       struct ethtool_eeprom *ee, u8 *data)
{
	struct usbnet *dev = netdev_priv(netdev);

	if (ee->magic != LAN75XX_EEPROM_MAGIC) {
706 707
		netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
			    ee->magic);
708 709 710 711 712 713
		return -EINVAL;
	}

	return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
}

714 715 716 717 718 719 720 721 722 723 724 725 726 727 728
static void smsc75xx_ethtool_get_wol(struct net_device *net,
				     struct ethtool_wolinfo *wolinfo)
{
	struct usbnet *dev = netdev_priv(net);
	struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);

	wolinfo->supported = SUPPORTED_WAKE;
	wolinfo->wolopts = pdata->wolopts;
}

static int smsc75xx_ethtool_set_wol(struct net_device *net,
				    struct ethtool_wolinfo *wolinfo)
{
	struct usbnet *dev = netdev_priv(net);
	struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
729
	int ret;
730

731 732 733
	if (wolinfo->wolopts & ~SUPPORTED_WAKE)
		return -EINVAL;

734
	pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
735 736

	ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
737 738
	if (ret < 0)
		netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
739

740
	return ret;
741 742
}

743 744 745 746 747 748 749 750 751 752 753
static const struct ethtool_ops smsc75xx_ethtool_ops = {
	.get_link	= usbnet_get_link,
	.nway_reset	= usbnet_nway_reset,
	.get_drvinfo	= usbnet_get_drvinfo,
	.get_msglevel	= usbnet_get_msglevel,
	.set_msglevel	= usbnet_set_msglevel,
	.get_settings	= usbnet_get_settings,
	.set_settings	= usbnet_set_settings,
	.get_eeprom_len	= smsc75xx_ethtool_get_eeprom_len,
	.get_eeprom	= smsc75xx_ethtool_get_eeprom,
	.set_eeprom	= smsc75xx_ethtool_set_eeprom,
754 755
	.get_wol	= smsc75xx_ethtool_get_wol,
	.set_wol	= smsc75xx_ethtool_set_wol,
756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775
};

static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
{
	struct usbnet *dev = netdev_priv(netdev);

	if (!netif_running(netdev))
		return -EINVAL;

	return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
}

static void smsc75xx_init_mac_address(struct usbnet *dev)
{
	/* try reading mac address from EEPROM */
	if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
			dev->net->dev_addr) == 0) {
		if (is_valid_ether_addr(dev->net->dev_addr)) {
			/* eeprom values are valid so use them */
			netif_dbg(dev, ifup, dev->net,
776
				  "MAC address read from EEPROM\n");
777 778 779 780 781
			return;
		}
	}

	/* no eeprom, or eeprom values are invalid. generate random MAC */
782
	eth_hw_addr_random(dev->net);
783
	netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
784 785 786 787 788 789 790 791 792
}

static int smsc75xx_set_mac_address(struct usbnet *dev)
{
	u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
		dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
	u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;

	int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
793 794 795 796
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
		return ret;
	}
797 798

	ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
799 800 801 802
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
		return ret;
	}
803 804 805

	addr_hi |= ADDR_FILTX_FB_VALID;
	ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
806 807 808 809
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
		return ret;
	}
810 811

	ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
812 813
	if (ret < 0)
		netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
814

815
	return ret;
816 817 818 819
}

static int smsc75xx_phy_initialize(struct usbnet *dev)
{
820
	int bmcr, ret, timeout = 0;
821 822 823 824 825 826 827

	/* Initialize MII structure */
	dev->mii.dev = dev->net;
	dev->mii.mdio_read = smsc75xx_mdio_read;
	dev->mii.mdio_write = smsc75xx_mdio_write;
	dev->mii.phy_id_mask = 0x1f;
	dev->mii.reg_num_mask = 0x1f;
828
	dev->mii.supports_gmii = 1;
829 830 831 832 833 834 835 836
	dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;

	/* reset phy and wait for reset to complete */
	smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);

	do {
		msleep(10);
		bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
837 838 839 840
		if (bmcr < 0) {
			netdev_warn(dev->net, "Error reading MII_BMCR\n");
			return bmcr;
		}
841
		timeout++;
842
	} while ((bmcr & BMCR_RESET) && (timeout < 100));
843 844

	if (timeout >= 100) {
845
		netdev_warn(dev->net, "timeout on PHY Reset\n");
846 847 848
		return -EIO;
	}

849 850 851
	/* phy workaround for gig link */
	smsc75xx_phy_gig_workaround(dev);

852 853 854
	smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
		ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
		ADVERTISE_PAUSE_ASYM);
855 856
	smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
		ADVERTISE_1000FULL);
857

858 859
	/* read and write to clear phy interrupt status */
	ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
860 861 862 863 864
	if (ret < 0) {
		netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
		return ret;
	}

865
	smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
866 867 868 869 870

	smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
		PHY_INT_MASK_DEFAULT);
	mii_nway_restart(&dev->mii);

871
	netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
872 873 874 875 876 877 878 879 880 881
	return 0;
}

static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
{
	int ret = 0;
	u32 buf;
	bool rxenabled;

	ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
882 883 884 885
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
		return ret;
	}
886 887 888 889 890 891

	rxenabled = ((buf & MAC_RX_RXEN) != 0);

	if (rxenabled) {
		buf &= ~MAC_RX_RXEN;
		ret = smsc75xx_write_reg(dev, MAC_RX, buf);
892 893 894 895
		if (ret < 0) {
			netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
			return ret;
		}
896 897 898 899 900 901 902
	}

	/* add 4 to size for FCS */
	buf &= ~MAC_RX_MAX_SIZE;
	buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);

	ret = smsc75xx_write_reg(dev, MAC_RX, buf);
903 904 905 906
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
		return ret;
	}
907 908 909 910

	if (rxenabled) {
		buf |= MAC_RX_RXEN;
		ret = smsc75xx_write_reg(dev, MAC_RX, buf);
911 912 913 914
		if (ret < 0) {
			netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
			return ret;
		}
915 916 917 918 919 920 921 922
	}

	return 0;
}

static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
{
	struct usbnet *dev = netdev_priv(netdev);
923 924 925 926
	int ret;

	if (new_mtu > MAX_SINGLE_PACKET_SIZE)
		return -EINVAL;
927

928
	ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
929 930 931 932
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to set mac rx frame length\n");
		return ret;
	}
933 934 935 936

	return usbnet_change_mtu(netdev, new_mtu);
}

937
/* Enable or disable Rx checksum offload engine */
938 939
static int smsc75xx_set_features(struct net_device *netdev,
	netdev_features_t features)
940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956
{
	struct usbnet *dev = netdev_priv(netdev);
	struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);

	if (features & NETIF_F_RXCSUM)
		pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
	else
		pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);

	spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
	/* it's racing here! */

	ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
957
	if (ret < 0) {
958
		netdev_warn(dev->net, "Error writing RFE_CTL\n");
959 960 961
		return ret;
	}
	return 0;
962 963
}

964
static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
965 966 967 968 969
{
	int timeout = 0;

	do {
		u32 buf;
970 971 972 973
		int ret;

		ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);

974 975 976 977
		if (ret < 0) {
			netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
			return ret;
		}
978 979 980 981 982 983 984 985

		if (buf & PMT_CTL_DEV_RDY)
			return 0;

		msleep(10);
		timeout++;
	} while (timeout < 100);

986
	netdev_warn(dev->net, "timeout waiting for device ready\n");
987 988 989
	return -EIO;
}

990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045
static int smsc75xx_phy_gig_workaround(struct usbnet *dev)
{
	struct mii_if_info *mii = &dev->mii;
	int ret = 0, timeout = 0;
	u32 buf, link_up = 0;

	/* Set the phy in Gig loopback */
	smsc75xx_mdio_write(dev->net, mii->phy_id, MII_BMCR, 0x4040);

	/* Wait for the link up */
	do {
		link_up = smsc75xx_link_ok_nopm(dev);
		usleep_range(10000, 20000);
		timeout++;
	} while ((!link_up) && (timeout < 1000));

	if (timeout >= 1000) {
		netdev_warn(dev->net, "Timeout waiting for PHY link up\n");
		return -EIO;
	}

	/* phy reset */
	ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
		return ret;
	}

	buf |= PMT_CTL_PHY_RST;

	ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
		return ret;
	}

	timeout = 0;
	do {
		usleep_range(10000, 20000);
		ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
		if (ret < 0) {
			netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n",
				    ret);
			return ret;
		}
		timeout++;
	} while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));

	if (timeout >= 100) {
		netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
		return -EIO;
	}

	return 0;
}

1046 1047 1048 1049 1050 1051
static int smsc75xx_reset(struct usbnet *dev)
{
	struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
	u32 buf;
	int ret = 0, timeout;

1052
	netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
1053

1054
	ret = smsc75xx_wait_ready(dev, 0);
1055 1056 1057 1058
	if (ret < 0) {
		netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
		return ret;
	}
1059

1060
	ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1061 1062 1063 1064
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
		return ret;
	}
1065 1066 1067 1068

	buf |= HW_CFG_LRST;

	ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1069 1070 1071 1072
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
		return ret;
	}
1073 1074 1075 1076 1077

	timeout = 0;
	do {
		msleep(10);
		ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1078 1079 1080 1081
		if (ret < 0) {
			netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
			return ret;
		}
1082 1083 1084 1085
		timeout++;
	} while ((buf & HW_CFG_LRST) && (timeout < 100));

	if (timeout >= 100) {
1086
		netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
1087 1088 1089
		return -EIO;
	}

1090
	netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
1091 1092

	ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1093 1094 1095 1096
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
		return ret;
	}
1097 1098 1099 1100

	buf |= PMT_CTL_PHY_RST;

	ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
1101 1102 1103 1104
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
		return ret;
	}
1105 1106 1107 1108 1109

	timeout = 0;
	do {
		msleep(10);
		ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1110 1111 1112 1113
		if (ret < 0) {
			netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
			return ret;
		}
1114 1115 1116 1117
		timeout++;
	} while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));

	if (timeout >= 100) {
1118
		netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
1119 1120 1121
		return -EIO;
	}

1122
	netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
1123 1124

	ret = smsc75xx_set_mac_address(dev);
1125 1126 1127 1128
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to set mac address\n");
		return ret;
	}
1129

1130 1131
	netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
		  dev->net->dev_addr);
1132 1133

	ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1134 1135 1136 1137
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
		return ret;
	}
1138

1139 1140
	netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
		  buf);
1141 1142 1143 1144

	buf |= HW_CFG_BIR;

	ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1145 1146 1147 1148
	if (ret < 0) {
		netdev_warn(dev->net,  "Failed to write HW_CFG: %d\n", ret);
		return ret;
	}
1149 1150

	ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1151 1152 1153 1154
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
		return ret;
	}
1155

1156 1157
	netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
		  buf);
1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169

	if (!turbo_mode) {
		buf = 0;
		dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
	} else if (dev->udev->speed == USB_SPEED_HIGH) {
		buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
		dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
	} else {
		buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
		dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
	}

1170 1171
	netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
		  (ulong)dev->rx_urb_size);
1172 1173

	ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
1174 1175 1176 1177
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
		return ret;
	}
1178 1179

	ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
1180 1181 1182 1183
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
		return ret;
	}
1184 1185

	netif_dbg(dev, ifup, dev->net,
1186
		  "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
1187 1188

	ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
1189 1190 1191 1192
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
		return ret;
	}
1193 1194

	ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
1195 1196 1197 1198
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
		return ret;
	}
1199 1200

	netif_dbg(dev, ifup, dev->net,
1201
		  "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
1202 1203 1204

	if (turbo_mode) {
		ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1205 1206 1207 1208
		if (ret < 0) {
			netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
			return ret;
		}
1209

1210
		netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
1211 1212 1213 1214

		buf |= (HW_CFG_MEF | HW_CFG_BCE);

		ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1215 1216 1217 1218
		if (ret < 0) {
			netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
			return ret;
		}
1219 1220

		ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1221 1222 1223 1224
		if (ret < 0) {
			netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
			return ret;
		}
1225

1226
		netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
1227 1228 1229 1230 1231
	}

	/* set FIFO sizes */
	buf = (MAX_RX_FIFO_SIZE - 512) / 512;
	ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
1232 1233 1234 1235
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
		return ret;
	}
1236

1237
	netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
1238 1239 1240

	buf = (MAX_TX_FIFO_SIZE - 512) / 512;
	ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
1241 1242 1243 1244
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
		return ret;
	}
1245

1246
	netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
1247 1248

	ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
1249 1250 1251 1252
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
		return ret;
	}
1253 1254

	ret = smsc75xx_read_reg(dev, ID_REV, &buf);
1255 1256 1257 1258
	if (ret < 0) {
		netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
		return ret;
	}
1259

1260
	netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
1261