sdio.c 116 KB
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/*
 * Copyright (c) 2010 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/types.h>
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#include <linux/atomic.h>
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#include <linux/kernel.h>
#include <linux/kthread.h>
#include <linux/printk.h>
#include <linux/pci_ids.h>
#include <linux/netdevice.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/mmc/sdio.h>
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#include <linux/mmc/sdio_ids.h>
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#include <linux/mmc/sdio_func.h>
#include <linux/mmc/card.h>
#include <linux/semaphore.h>
#include <linux/firmware.h>
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#include <linux/module.h>
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#include <linux/bcma/bcma.h>
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#include <linux/debugfs.h>
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#include <linux/vmalloc.h>
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#include <asm/unaligned.h>
#include <defs.h>
#include <brcmu_wifi.h>
#include <brcmu_utils.h>
#include <brcm_hw_ids.h>
#include <soc.h>
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#include "sdio.h"
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#include "chip.h"
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#include "firmware.h"
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#include "core.h"
#include "common.h"
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#define DCMD_RESP_TIMEOUT	msecs_to_jiffies(2500)
#define CTL_DONE_TIMEOUT	msecs_to_jiffies(2500)
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#ifdef DEBUG
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#define BRCMF_TRAP_INFO_SIZE	80

#define CBUF_LEN	(128)

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/* Device console log buffer state */
#define CONSOLE_BUFFER_MAX	2024

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struct rte_log_le {
	__le32 buf;		/* Can't be pointer on (64-bit) hosts */
	__le32 buf_size;
	__le32 idx;
	char *_buf_compat;	/* Redundant pointer for backward compat. */
};

struct rte_console {
	/* Virtual UART
	 * When there is no UART (e.g. Quickturn),
	 * the host should write a complete
	 * input line directly into cbuf and then write
	 * the length into vcons_in.
	 * This may also be used when there is a real UART
	 * (at risk of conflicting with
	 * the real UART).  vcons_out is currently unused.
	 */
	uint vcons_in;
	uint vcons_out;

	/* Output (logging) buffer
	 * Console output is written to a ring buffer log_buf at index log_idx.
	 * The host may read the output when it sees log_idx advance.
	 * Output will be lost if the output wraps around faster than the host
	 * polls.
	 */
	struct rte_log_le log_le;

	/* Console input line buffer
	 * Characters are read one at a time into cbuf
	 * until <CR> is received, then
	 * the buffer is processed as a command line.
	 * Also used for virtual UART.
	 */
	uint cbuf_idx;
	char cbuf[CBUF_LEN];
};

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#endif				/* DEBUG */
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#include <chipcommon.h>

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#include "bus.h"
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#include "debug.h"
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#include "tracepoint.h"
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#define TXQLEN		2048	/* bulk tx queue length */
#define TXHI		(TXQLEN - 256)	/* turn on flow control above TXHI */
#define TXLOW		(TXHI - 256)	/* turn off flow control below TXLOW */
#define PRIOMASK	7

#define TXRETRIES	2	/* # of retries for tx frames */

#define BRCMF_RXBOUND	50	/* Default for max rx frames in
				 one scheduling */

#define BRCMF_TXBOUND	20	/* Default for max tx frames in
				 one scheduling */

#define BRCMF_TXMINMAX	1	/* Max tx frames if rx still pending */

#define MEMBLOCK	2048	/* Block size used for downloading
				 of dongle image */
#define MAX_DATA_BUF	(32 * 1024)	/* Must be large enough to hold
				 biggest possible glom */

#define BRCMF_FIRSTREAD	(1 << 6)

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#define BRCMF_CONSOLE	10	/* watchdog interval to poll console */
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/* SBSDIO_DEVICE_CTL */

/* 1: device will assert busy signal when receiving CMD53 */
#define SBSDIO_DEVCTL_SETBUSY		0x01
/* 1: assertion of sdio interrupt is synchronous to the sdio clock */
#define SBSDIO_DEVCTL_SPI_INTR_SYNC	0x02
/* 1: mask all interrupts to host except the chipActive (rev 8) */
#define SBSDIO_DEVCTL_CA_INT_ONLY	0x04
/* 1: isolate internal sdio signals, put external pads in tri-state; requires
 * sdio bus power cycle to clear (rev 9) */
#define SBSDIO_DEVCTL_PADS_ISO		0x08
/* Force SD->SB reset mapping (rev 11) */
#define SBSDIO_DEVCTL_SB_RST_CTL	0x30
/*   Determined by CoreControl bit */
#define SBSDIO_DEVCTL_RST_CORECTL	0x00
/*   Force backplane reset */
#define SBSDIO_DEVCTL_RST_BPRESET	0x10
/*   Force no backplane reset */
#define SBSDIO_DEVCTL_RST_NOBPRESET	0x20

/* direct(mapped) cis space */

/* MAPPED common CIS address */
#define SBSDIO_CIS_BASE_COMMON		0x1000
/* maximum bytes in one CIS */
#define SBSDIO_CIS_SIZE_LIMIT		0x200
/* cis offset addr is < 17 bits */
#define SBSDIO_CIS_OFT_ADDR_MASK	0x1FFFF

/* manfid tuple length, include tuple, link bytes */
#define SBSDIO_CIS_MANFID_TUPLE_LEN	6

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#define CORE_BUS_REG(base, field) \
		(base + offsetof(struct sdpcmd_regs, field))

/* SDIO function 1 register CHIPCLKCSR */
/* Force ALP request to backplane */
#define SBSDIO_FORCE_ALP		0x01
/* Force HT request to backplane */
#define SBSDIO_FORCE_HT			0x02
/* Force ILP request to backplane */
#define SBSDIO_FORCE_ILP		0x04
/* Make ALP ready (power up xtal) */
#define SBSDIO_ALP_AVAIL_REQ		0x08
/* Make HT ready (power up PLL) */
#define SBSDIO_HT_AVAIL_REQ		0x10
/* Squelch clock requests from HW */
#define SBSDIO_FORCE_HW_CLKREQ_OFF	0x20
/* Status: ALP is ready */
#define SBSDIO_ALP_AVAIL		0x40
/* Status: HT is ready */
#define SBSDIO_HT_AVAIL			0x80
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#define SBSDIO_CSR_MASK			0x1F
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#define SBSDIO_AVBITS		(SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
#define SBSDIO_ALPAV(regval)	((regval) & SBSDIO_AVBITS)
#define SBSDIO_HTAV(regval)	(((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
#define SBSDIO_ALPONLY(regval)	(SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
#define SBSDIO_CLKAV(regval, alponly) \
	(SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))

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/* intstatus */
#define I_SMB_SW0	(1 << 0)	/* To SB Mail S/W interrupt 0 */
#define I_SMB_SW1	(1 << 1)	/* To SB Mail S/W interrupt 1 */
#define I_SMB_SW2	(1 << 2)	/* To SB Mail S/W interrupt 2 */
#define I_SMB_SW3	(1 << 3)	/* To SB Mail S/W interrupt 3 */
#define I_SMB_SW_MASK	0x0000000f	/* To SB Mail S/W interrupts mask */
#define I_SMB_SW_SHIFT	0	/* To SB Mail S/W interrupts shift */
#define I_HMB_SW0	(1 << 4)	/* To Host Mail S/W interrupt 0 */
#define I_HMB_SW1	(1 << 5)	/* To Host Mail S/W interrupt 1 */
#define I_HMB_SW2	(1 << 6)	/* To Host Mail S/W interrupt 2 */
#define I_HMB_SW3	(1 << 7)	/* To Host Mail S/W interrupt 3 */
#define I_HMB_SW_MASK	0x000000f0	/* To Host Mail S/W interrupts mask */
#define I_HMB_SW_SHIFT	4	/* To Host Mail S/W interrupts shift */
#define I_WR_OOSYNC	(1 << 8)	/* Write Frame Out Of Sync */
#define I_RD_OOSYNC	(1 << 9)	/* Read Frame Out Of Sync */
#define	I_PC		(1 << 10)	/* descriptor error */
#define	I_PD		(1 << 11)	/* data error */
#define	I_DE		(1 << 12)	/* Descriptor protocol Error */
#define	I_RU		(1 << 13)	/* Receive descriptor Underflow */
#define	I_RO		(1 << 14)	/* Receive fifo Overflow */
#define	I_XU		(1 << 15)	/* Transmit fifo Underflow */
#define	I_RI		(1 << 16)	/* Receive Interrupt */
#define I_BUSPWR	(1 << 17)	/* SDIO Bus Power Change (rev 9) */
#define I_XMTDATA_AVAIL (1 << 23)	/* bits in fifo */
#define	I_XI		(1 << 24)	/* Transmit Interrupt */
#define I_RF_TERM	(1 << 25)	/* Read Frame Terminate */
#define I_WF_TERM	(1 << 26)	/* Write Frame Terminate */
#define I_PCMCIA_XU	(1 << 27)	/* PCMCIA Transmit FIFO Underflow */
#define I_SBINT		(1 << 28)	/* sbintstatus Interrupt */
#define I_CHIPACTIVE	(1 << 29)	/* chip from doze to active state */
#define I_SRESET	(1 << 30)	/* CCCR RES interrupt */
#define I_IOE2		(1U << 31)	/* CCCR IOE2 Bit Changed */
#define	I_ERRORS	(I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
#define I_DMA		(I_RI | I_XI | I_ERRORS)

/* corecontrol */
#define CC_CISRDY		(1 << 0)	/* CIS Ready */
#define CC_BPRESEN		(1 << 1)	/* CCCR RES signal */
#define CC_F2RDY		(1 << 2)	/* set CCCR IOR2 bit */
#define CC_CLRPADSISO		(1 << 3)	/* clear SDIO pads isolation */
#define CC_XMTDATAAVAIL_MODE	(1 << 4)
#define CC_XMTDATAAVAIL_CTRL	(1 << 5)

/* SDA_FRAMECTRL */
#define SFC_RF_TERM	(1 << 0)	/* Read Frame Terminate */
#define SFC_WF_TERM	(1 << 1)	/* Write Frame Terminate */
#define SFC_CRC4WOOS	(1 << 2)	/* CRC error for write out of sync */
#define SFC_ABORTALL	(1 << 3)	/* Abort all in-progress frames */

/*
 * Software allocation of To SB Mailbox resources
 */

/* tosbmailbox bits corresponding to intstatus bits */
#define SMB_NAK		(1 << 0)	/* Frame NAK */
#define SMB_INT_ACK	(1 << 1)	/* Host Interrupt ACK */
#define SMB_USE_OOB	(1 << 2)	/* Use OOB Wakeup */
#define SMB_DEV_INT	(1 << 3)	/* Miscellaneous Interrupt */

/* tosbmailboxdata */
#define SMB_DATA_VERSION_SHIFT	16	/* host protocol version */

/*
 * Software allocation of To Host Mailbox resources
 */

/* intstatus bits */
#define I_HMB_FC_STATE	I_HMB_SW0	/* Flow Control State */
#define I_HMB_FC_CHANGE	I_HMB_SW1	/* Flow Control State Changed */
#define I_HMB_FRAME_IND	I_HMB_SW2	/* Frame Indication */
#define I_HMB_HOST_INT	I_HMB_SW3	/* Miscellaneous Interrupt */

/* tohostmailboxdata */
#define HMB_DATA_NAKHANDLED	1	/* retransmit NAK'd frame */
#define HMB_DATA_DEVREADY	2	/* talk to host after enable */
#define HMB_DATA_FC		4	/* per prio flowcontrol update flag */
#define HMB_DATA_FWREADY	8	/* fw ready for protocol activity */

#define HMB_DATA_FCDATA_MASK	0xff000000
#define HMB_DATA_FCDATA_SHIFT	24

#define HMB_DATA_VERSION_MASK	0x00ff0000
#define HMB_DATA_VERSION_SHIFT	16

/*
 * Software-defined protocol header
 */

/* Current protocol version */
#define SDPCM_PROT_VERSION	4

/*
 * Shared structure between dongle and the host.
 * The structure contains pointers to trap or assert information.
 */
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#define SDPCM_SHARED_VERSION       0x0003
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#define SDPCM_SHARED_VERSION_MASK  0x00FF
#define SDPCM_SHARED_ASSERT_BUILT  0x0100
#define SDPCM_SHARED_ASSERT        0x0200
#define SDPCM_SHARED_TRAP          0x0400

/* Space for header read, limit for data packets */
#define MAX_HDR_READ	(1 << 6)
#define MAX_RX_DATASZ	2048

/* Bump up limit on waiting for HT to account for first startup;
 * if the image is doing a CRC calculation before programming the PMU
 * for HT availability, it could take a couple hundred ms more, so
 * max out at a 1 second (1000000us).
 */
#undef PMU_MAX_TRANSITION_DLY
#define PMU_MAX_TRANSITION_DLY 1000000

/* Value for ChipClockCSR during initial setup */
#define BRCMF_INIT_CLKCTL1	(SBSDIO_FORCE_HW_CLKREQ_OFF |	\
					SBSDIO_ALP_AVAIL_REQ)

/* Flags for SDH calls */
#define F2SYNC	(SDIO_REQ_4BYTE | SDIO_REQ_FIXED)

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#define BRCMF_IDLE_ACTIVE	0	/* Do not request any SD clock change
					 * when idle
					 */
#define BRCMF_IDLE_INTERVAL	1

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#define KSO_WAIT_US 50
#define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
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#define BRCMF_SDIO_MAX_ACCESS_ERRORS	5
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/*
 * Conversion of 802.1D priority to precedence level
 */
static uint prio2prec(u32 prio)
{
	return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
	       (prio^2) : prio;
}

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#ifdef DEBUG
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/* Device console log buffer state */
struct brcmf_console {
	uint count;		/* Poll interval msec counter */
	uint log_addr;		/* Log struct address (fixed) */
	struct rte_log_le log_le;	/* Log struct (host copy) */
	uint bufsize;		/* Size of log buffer */
	u8 *buf;		/* Log buffer (host copy) */
	uint last;		/* Last buffer read index */
};
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struct brcmf_trap_info {
	__le32		type;
	__le32		epc;
	__le32		cpsr;
	__le32		spsr;
	__le32		r0;	/* a1 */
	__le32		r1;	/* a2 */
	__le32		r2;	/* a3 */
	__le32		r3;	/* a4 */
	__le32		r4;	/* v1 */
	__le32		r5;	/* v2 */
	__le32		r6;	/* v3 */
	__le32		r7;	/* v4 */
	__le32		r8;	/* v5 */
	__le32		r9;	/* sb/v6 */
	__le32		r10;	/* sl/v7 */
	__le32		r11;	/* fp/v8 */
	__le32		r12;	/* ip */
	__le32		r13;	/* sp */
	__le32		r14;	/* lr */
	__le32		pc;	/* r15 */
};
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#endif				/* DEBUG */
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struct sdpcm_shared {
	u32 flags;
	u32 trap_addr;
	u32 assert_exp_addr;
	u32 assert_file_addr;
	u32 assert_line;
	u32 console_addr;	/* Address of struct rte_console */
	u32 msgtrace_addr;
	u8 tag[32];
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	u32 brpt_addr;
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};

struct sdpcm_shared_le {
	__le32 flags;
	__le32 trap_addr;
	__le32 assert_exp_addr;
	__le32 assert_file_addr;
	__le32 assert_line;
	__le32 console_addr;	/* Address of struct rte_console */
	__le32 msgtrace_addr;
	u8 tag[32];
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	__le32 brpt_addr;
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};

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/* dongle SDIO bus specific header info */
struct brcmf_sdio_hdrinfo {
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	u8 seq_num;
	u8 channel;
	u16 len;
	u16 len_left;
	u16 len_nxtfrm;
	u8 dat_offset;
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	bool lastfrm;
	u16 tail_pad;
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};
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/*
 * hold counter variables
 */
struct brcmf_sdio_count {
	uint intrcount;		/* Count of device interrupt callbacks */
	uint lastintrs;		/* Count as of last watchdog timer */
	uint pollcnt;		/* Count of active polls */
	uint regfails;		/* Count of R_REG failures */
	uint tx_sderrs;		/* Count of tx attempts with sd errors */
	uint fcqueued;		/* Tx packets that got queued */
	uint rxrtx;		/* Count of rtx requests (NAK to dongle) */
	uint rx_toolong;	/* Receive frames too long to receive */
	uint rxc_errors;	/* SDIO errors when reading control frames */
	uint rx_hdrfail;	/* SDIO errors on header reads */
	uint rx_badhdr;		/* Bad received headers (roosync?) */
	uint rx_badseq;		/* Mismatched rx sequence number */
	uint fc_rcvd;		/* Number of flow-control events received */
	uint fc_xoff;		/* Number which turned on flow-control */
	uint fc_xon;		/* Number which turned off flow-control */
	uint rxglomfail;	/* Failed deglom attempts */
	uint rxglomframes;	/* Number of glom frames (superframes) */
	uint rxglompkts;	/* Number of packets from glom frames */
	uint f2rxhdrs;		/* Number of header reads */
	uint f2rxdata;		/* Number of frame data reads */
	uint f2txdata;		/* Number of f2 frame writes */
	uint f1regdata;		/* Number of f1 register accesses */
	uint tickcnt;		/* Number of watchdog been schedule */
	ulong tx_ctlerrs;	/* Err of sending ctrl frames */
	ulong tx_ctlpkts;	/* Ctrl frames sent to dongle */
	ulong rx_ctlerrs;	/* Err of processing rx ctrl frames */
	ulong rx_ctlpkts;	/* Ctrl frames processed from dongle */
	ulong rx_readahead_cnt;	/* packets where header read-ahead was used */
};

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/* misc chip info needed by some of the routines */
/* Private data for SDIO bus interaction */
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struct brcmf_sdio {
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	struct brcmf_sdio_dev *sdiodev;	/* sdio device handler */
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	struct brcmf_chip *ci;	/* Chip info struct */
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	u32 hostintmask;	/* Copy of Host Interrupt Mask */
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	atomic_t intstatus;	/* Intstatus bits (events) pending */
	atomic_t fcstate;	/* State of dongle flow-control */
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	uint blocksize;		/* Block size of SDIO transfers */
	uint roundup;		/* Max roundup limit */

	struct pktq txq;	/* Queue length used for flow-control */
	u8 flowcontrol;	/* per prio flow control bitmask */
	u8 tx_seq;		/* Transmit sequence number (next) */
	u8 tx_max;		/* Maximum transmit sequence allowed */

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	u8 *hdrbuf;		/* buffer for handling rx frame */
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	u8 *rxhdr;		/* Header of current rx frame (in hdrbuf) */
	u8 rx_seq;		/* Receive sequence number (expected) */
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	struct brcmf_sdio_hdrinfo cur_read;
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				/* info of current read frame */
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	bool rxskip;		/* Skip receive (awaiting NAK ACK) */
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	bool rxpending;		/* Data frame pending in dongle */
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	uint rxbound;		/* Rx frames to read before resched */
	uint txbound;		/* Tx frames to send before resched */
	uint txminmax;

	struct sk_buff *glomd;	/* Packet containing glomming descriptor */
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	struct sk_buff_head glom; /* Packet list for glommed superframe */
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	u8 *rxbuf;		/* Buffer for receiving control packets */
	uint rxblen;		/* Allocated length of rxbuf */
	u8 *rxctl;		/* Aligned pointer into rxbuf */
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	u8 *rxctl_orig;		/* pointer for freeing rxctl */
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	uint rxlen;		/* Length of valid data in buffer */
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	spinlock_t rxctl_lock;	/* protection lock for ctrl frame resources */
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	u8 sdpcm_ver;	/* Bus protocol reported by dongle */

	bool intr;		/* Use interrupts */
	bool poll;		/* Use polling */
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	atomic_t ipend;		/* Device interrupt is pending */
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	uint spurious;		/* Count of spurious interrupts */
	uint pollrate;		/* Ticks between device polls */
	uint polltick;		/* Tick counter */

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#ifdef DEBUG
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	uint console_interval;
	struct brcmf_console console;	/* Console output polling support */
	uint console_addr;	/* Console address from shared struct */
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#endif				/* DEBUG */
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	uint clkstate;		/* State of sd and backplane clock(s) */
	s32 idletime;		/* Control for activity timeout */
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	s32 idlecount;		/* Activity timeout counter */
	s32 idleclock;		/* How to set bus driver when idle */
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	bool rxflow_mode;	/* Rx flow control mode */
	bool rxflow;		/* Is rx flow control on */
	bool alp_only;		/* Don't use HT clock (ALP only) */

	u8 *ctrl_frame_buf;
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	u16 ctrl_frame_len;
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	bool ctrl_frame_stat;
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	int ctrl_frame_err;
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	spinlock_t txq_lock;		/* protect bus->txq */
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	wait_queue_head_t ctrl_wait;
	wait_queue_head_t dcmd_resp_wait;

	struct timer_list timer;
	struct completion watchdog_wait;
	struct task_struct *watchdog_tsk;
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	bool wd_active;
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	struct workqueue_struct *brcmf_wq;
	struct work_struct datawork;
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	bool dpc_triggered;
	bool dpc_running;
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	bool txoff;		/* Transmit flow-controlled */
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	struct brcmf_sdio_count sdcnt;
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	bool sr_enabled; /* SaveRestore enabled */
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	bool sleeping;
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	u8 tx_hdrlen;		/* sdio bus header length for tx packet */
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	bool txglom;		/* host tx glomming enable flag */
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	u16 head_align;		/* buffer pointer alignment */
	u16 sgentry_align;	/* scatter-gather buffer alignment */
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};

/* clkstate */
#define CLK_NONE	0
#define CLK_SDONLY	1
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#define CLK_PENDING	2
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#define CLK_AVAIL	3

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#ifdef DEBUG
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static int qcount[NUMPRIO];
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#endif				/* DEBUG */
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#define DEFAULT_SDIO_DRIVE_STRENGTH	6	/* in milliamps */
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#define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)

/* Limit on rounding up frames */
static const uint max_roundup = 512;

#define ALIGNMENT  4

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enum brcmf_sdio_frmtype {
	BRCMF_SDIO_FT_NORMAL,
	BRCMF_SDIO_FT_SUPER,
	BRCMF_SDIO_FT_SUB,
};

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#define SDIOD_DRVSTR_KEY(chip, pmu)     (((chip) << 16) | (pmu))

/* SDIO Pad drive strength to select value mappings */
struct sdiod_drive_str {
	u8 strength;	/* Pad Drive Strength in mA */
	u8 sel;		/* Chip-specific select value */
};

/* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
	{32, 0x6},
	{26, 0x7},
	{22, 0x4},
	{16, 0x5},
	{12, 0x2},
	{8, 0x3},
	{4, 0x0},
	{0, 0x1}
};

/* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
	{6, 0x7},
	{5, 0x6},
	{4, 0x5},
	{3, 0x4},
	{2, 0x2},
	{1, 0x1},
	{0, 0x0}
};

/* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
	{3, 0x3},
	{2, 0x2},
	{1, 0x1},
	{0, 0x0} };

/* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
	{16, 0x7},
	{12, 0x5},
	{8,  0x3},
	{4,  0x1}
};

596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612
BRCMF_FW_NVRAM_DEF(43143, "brcmfmac43143-sdio.bin", "brcmfmac43143-sdio.txt");
BRCMF_FW_NVRAM_DEF(43241B0, "brcmfmac43241b0-sdio.bin",
		   "brcmfmac43241b0-sdio.txt");
BRCMF_FW_NVRAM_DEF(43241B4, "brcmfmac43241b4-sdio.bin",
		   "brcmfmac43241b4-sdio.txt");
BRCMF_FW_NVRAM_DEF(43241B5, "brcmfmac43241b5-sdio.bin",
		   "brcmfmac43241b5-sdio.txt");
BRCMF_FW_NVRAM_DEF(4329, "brcmfmac4329-sdio.bin", "brcmfmac4329-sdio.txt");
BRCMF_FW_NVRAM_DEF(4330, "brcmfmac4330-sdio.bin", "brcmfmac4330-sdio.txt");
BRCMF_FW_NVRAM_DEF(4334, "brcmfmac4334-sdio.bin", "brcmfmac4334-sdio.txt");
BRCMF_FW_NVRAM_DEF(43340, "brcmfmac43340-sdio.bin", "brcmfmac43340-sdio.txt");
BRCMF_FW_NVRAM_DEF(4335, "brcmfmac4335-sdio.bin", "brcmfmac4335-sdio.txt");
BRCMF_FW_NVRAM_DEF(43362, "brcmfmac43362-sdio.bin", "brcmfmac43362-sdio.txt");
BRCMF_FW_NVRAM_DEF(4339, "brcmfmac4339-sdio.bin", "brcmfmac4339-sdio.txt");
BRCMF_FW_NVRAM_DEF(43430, "brcmfmac43430-sdio.bin", "brcmfmac43430-sdio.txt");
BRCMF_FW_NVRAM_DEF(43455, "brcmfmac43455-sdio.bin", "brcmfmac43455-sdio.txt");
BRCMF_FW_NVRAM_DEF(4354, "brcmfmac4354-sdio.bin", "brcmfmac4354-sdio.txt");
613
BRCMF_FW_NVRAM_DEF(4356, "brcmfmac4356-sdio.bin", "brcmfmac4356-sdio.txt");
614 615 616 617 618 619 620 621 622 623

static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
624
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),
625 626 627 628 629
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFF, 43430),
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
630 631
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
	BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356)
632 633
};

634 635 636 637 638 639 640 641 642 643 644
static void pkt_align(struct sk_buff *p, int len, int align)
{
	uint datalign;
	datalign = (unsigned long)(p->data);
	datalign = roundup(datalign, (align)) - datalign;
	if (datalign)
		skb_pull(p, datalign);
	__skb_trim(p, len);
}

/* To check if there's window offered */
645
static bool data_ok(struct brcmf_sdio *bus)
646 647 648 649 650 651 652 653 654
{
	return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
	       ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
}

/*
 * Reads a register in the SDIO hardware block. This block occupies a series of
 * adresses on the 32 bit backplane bus.
 */
655
static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
656
{
657
	struct brcmf_core *core;
658
	int ret;
659

660 661
	core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
	*regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
662 663

	return ret;
664 665
}

666
static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
667
{
668
	struct brcmf_core *core;
669
	int ret;
670

671 672
	core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
	brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
673 674

	return ret;
675 676
}

677
static int
678
brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
679 680 681
{
	u8 wr_val = 0, rd_val, cmp_val, bmask;
	int err = 0;
682
	int err_cnt = 0;
683 684
	int try_cnt = 0;

685
	brcmf_dbg(TRACE, "Enter: on=%d\n", on);
686 687 688

	wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
	/* 1st KSO write goes to AOS wake up core if device is asleep  */
689 690
	brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
			  wr_val, &err);
691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715

	if (on) {
		/* device WAKEUP through KSO:
		 * write bit 0 & read back until
		 * both bits 0 (kso bit) & 1 (dev on status) are set
		 */
		cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
			  SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
		bmask = cmp_val;
		usleep_range(2000, 3000);
	} else {
		/* Put device to sleep, turn off KSO */
		cmp_val = 0;
		/* only check for bit0, bit1(dev on status) may not
		 * get cleared right away
		 */
		bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
	}

	do {
		/* reliable KSO bit set/clr:
		 * the sdiod sleep write access is synced to PMU 32khz clk
		 * just one write attempt may fail,
		 * read it back until it matches written value
		 */
716 717
		rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
					   &err);
718 719 720 721 722 723 724
		if (!err) {
			if ((rd_val & bmask) == cmp_val)
				break;
			err_cnt = 0;
		}
		/* bail out upon subsequent access errors */
		if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS))
725 726
			break;
		udelay(KSO_WAIT_US);
727 728
		brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
				  wr_val, &err);
729 730
	} while (try_cnt++ < MAX_KSO_ATTEMPTS);

731 732 733 734 735 736 737
	if (try_cnt > 2)
		brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
			  rd_val, err);

	if (try_cnt > MAX_KSO_ATTEMPTS)
		brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);

738 739 740
	return err;
}

741 742 743
#define HOSTINTMASK		(I_HMB_SW_MASK | I_CHIPACTIVE)

/* Turn backplane clock on or off */
744
static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
745 746 747 748 749
{
	int err;
	u8 clkctl, clkreq, devctl;
	unsigned long timeout;

750
	brcmf_dbg(SDIO, "Enter\n");
751 752 753

	clkctl = 0;

754 755 756 757 758
	if (bus->sr_enabled) {
		bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
		return 0;
	}

759 760 761 762 763
	if (on) {
		/* Request HT Avail */
		clkreq =
		    bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;

764 765
		brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
				  clkreq, &err);
766
		if (err) {
767
			brcmf_err("HT Avail request error: %d\n", err);
768 769 770 771
			return -EBADE;
		}

		/* Check current status */
772 773
		clkctl = brcmf_sdiod_regrb(bus->sdiodev,
					   SBSDIO_FUNC1_CHIPCLKCSR, &err);
774
		if (err) {
775
			brcmf_err("HT Avail read error: %d\n", err);
776 777 778 779 780 781
			return -EBADE;
		}

		/* Go to pending and await interrupt if appropriate */
		if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
			/* Allow only clock-available interrupt */
782 783
			devctl = brcmf_sdiod_regrb(bus->sdiodev,
						   SBSDIO_DEVICE_CTL, &err);
784
			if (err) {
785
				brcmf_err("Devctl error setting CA: %d\n",
786 787 788 789 790
					  err);
				return -EBADE;
			}

			devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
791 792
			brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
					  devctl, &err);
793
			brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
794 795 796 797 798
			bus->clkstate = CLK_PENDING;

			return 0;
		} else if (bus->clkstate == CLK_PENDING) {
			/* Cancel CA-only interrupt filter */
799 800
			devctl = brcmf_sdiod_regrb(bus->sdiodev,
						   SBSDIO_DEVICE_CTL, &err);
801
			devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
802 803
			brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
					  devctl, &err);
804 805 806 807 808 809
		}

		/* Otherwise, wait here (polling) for HT Avail */
		timeout = jiffies +
			  msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
		while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
810 811 812
			clkctl = brcmf_sdiod_regrb(bus->sdiodev,
						   SBSDIO_FUNC1_CHIPCLKCSR,
						   &err);
813 814 815 816 817 818
			if (time_after(jiffies, timeout))
				break;
			else
				usleep_range(5000, 10000);
		}
		if (err) {
819
			brcmf_err("HT Avail request error: %d\n", err);
820 821 822
			return -EBADE;
		}
		if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
823
			brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
824 825 826 827 828 829
				  PMU_MAX_TRANSITION_DLY, clkctl);
			return -EBADE;
		}

		/* Mark clock available */
		bus->clkstate = CLK_AVAIL;
830
		brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
831

832
#if defined(DEBUG)
833
		if (!bus->alp_only) {
834
			if (SBSDIO_ALPONLY(clkctl))
835
				brcmf_err("HT Clock should be on\n");
836
		}
837
#endif				/* defined (DEBUG) */
838 839 840 841 842 843

	} else {
		clkreq = 0;

		if (bus->clkstate == CLK_PENDING) {
			/* Cancel CA-only interrupt filter */
844 845
			devctl = brcmf_sdiod_regrb(bus->sdiodev,
						   SBSDIO_DEVICE_CTL, &err);
846
			devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
847 848
			brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
					  devctl, &err);
849 850 851
		}

		bus->clkstate = CLK_SDONLY;
852 853
		brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
				  clkreq, &err);
854
		brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
855
		if (err) {
856
			brcmf_err("Failed access turning clock off: %d\n",
857 858 859 860 861 862 863 864
				  err);
			return -EBADE;
		}
	}
	return 0;
}

/* Change idle/active SD state */
865
static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
866
{
867
	brcmf_dbg(SDIO, "Enter\n");
868 869 870 871 872 873 874 875 876 877

	if (on)
		bus->clkstate = CLK_SDONLY;
	else
		bus->clkstate = CLK_NONE;

	return 0;
}

/* Transition SD and backplane clock readiness */
878
static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
879
{
880
#ifdef DEBUG
881
	uint oldstate = bus->clkstate;
882
#endif				/* DEBUG */
883

884
	brcmf_dbg(SDIO, "Enter\n");
885 886

	/* Early exit if we're already there */
887
	if (bus->clkstate == target)
888 889 890 891 892 893
		return 0;

	switch (target) {
	case CLK_AVAIL:
		/* Make sure SD clock is available */
		if (bus->clkstate == CLK_NONE)
894
			brcmf_sdio_sdclk(bus, true);
895
		/* Now request HT Avail on the backplane */
896
		brcmf_sdio_htclk(bus, true, pendok);
897 898 899 900 901
		break;

	case CLK_SDONLY:
		/* Remove HT request, or bring up SD clock */
		if (bus->clkstate == CLK_NONE)
902
			brcmf_sdio_sdclk(bus, true);
903
		else if (bus->clkstate == CLK_AVAIL)
904
			brcmf_sdio_htclk(bus, false, false);
905
		else
906
			brcmf_err("request for %d -> %d\n",
907 908 909 910 911 912
				  bus->clkstate, target);
		break;

	case CLK_NONE:
		/* Make sure to remove HT request */
		if (bus->clkstate == CLK_AVAIL)
913
			brcmf_sdio_htclk(bus, false, false);
914
		/* Now remove the SD clock */
915
		brcmf_sdio_sdclk(bus, false);
916 917
		break;
	}
918
#ifdef DEBUG
919
	brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
920
#endif				/* DEBUG */
921 922 923 924

	return 0;
}

925
static int
926
brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
927 928
{
	int err = 0;
929
	u8 clkcsr;
930 931

	brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
932
		  (sleep ? "SLEEP" : "WAKE"),
933
		  (bus->sleeping ? "SLEEP" : "WAKE"));
934 935 936 937

	/* If SR is enabled control bus state with KSO */
	if (bus->sr_enabled) {
		/* Done if we're already in the requested state */
938
		if (sleep == bus->sleeping)
939 940 941 942
			goto end;

		/* Going to sleep */
		if (sleep) {
943 944 945 946 947 948 949 950 951
			clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
						   SBSDIO_FUNC1_CHIPCLKCSR,
						   &err);
			if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
				brcmf_dbg(SDIO, "no clock, set ALP\n");
				brcmf_sdiod_regwb(bus->sdiodev,
						  SBSDIO_FUNC1_CHIPCLKCSR,
						  SBSDIO_ALP_AVAIL_REQ, &err);
			}
952
			err = brcmf_sdio_kso_control(bus, false);
953
		} else {
954
			err = brcmf_sdio_kso_control(bus, true);
955
		}
956
		if (err) {
957 958
			brcmf_err("error while changing bus sleep state %d\n",
				  err);
959
			goto done;
960 961 962 963 964 965 966
		}
	}

end:
	/* control clocks */
	if (sleep) {
		if (!bus->sr_enabled)
967
			brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
968
	} else {
969
		brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
970
		brcmf_sdio_wd_timer(bus, true);
971
	}
972
	bus->sleeping = sleep;
973 974
	brcmf_dbg(SDIO, "new state %s\n",
		  (sleep ? "SLEEP" : "WAKE"));
975 976
done:
	brcmf_dbg(SDIO, "Exit: err=%d\n", err);
977 978 979 980
	return err;

}

981 982 983 984 985 986 987 988 989
#ifdef DEBUG
static inline bool brcmf_sdio_valid_shared_address(u32 addr)
{
	return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
}

static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
				 struct sdpcm_shared *sh)
{
990
	u32 addr = 0;
991 992 993 994 995
	int rv;
	u32 shaddr = 0;
	struct sdpcm_shared_le sh_le;
	__le32 addr_le;

996 997
	sdio_claim_host(bus->sdiodev->func[1]);
	brcmf_sdio_bus_sleep(bus, false, false);
998 999 1000 1001 1002

	/*
	 * Read last word in socram to determine
	 * address of sdpcm_shared structure
	 */
1003 1004 1005 1006 1007
	shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
	if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
		shaddr -= bus->ci->srsize;
	rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
			       (u8 *)&addr_le, 4);
1008
	if (rv < 0)
1009
		goto fail;
1010 1011 1012 1013 1014

	/*
	 * Check if addr is valid.
	 * NVRAM length at the end of memory should have been overwritten.
	 */
1015
	addr = le32_to_cpu(addr_le);
1016
	if (!brcmf_sdio_valid_shared_address(addr)) {
1017 1018 1019
		brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
		rv = -EINVAL;
		goto fail;
1020 1021
	}

1022 1023
	brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);

1024 1025 1026 1027
	/* Read hndrte_shared structure */
	rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
			       sizeof(struct sdpcm_shared_le));
	if (rv < 0)
1028 1029 1030
		goto fail;

	sdio_release_host(bus->sdiodev->func[1]);
1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047

	/* Endianness */
	sh->flags = le32_to_cpu(sh_le.flags);
	sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
	sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
	sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
	sh->assert_line = le32_to_cpu(sh_le.assert_line);
	sh->console_addr = le32_to_cpu(sh_le.console_addr);
	sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);

	if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
		brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
			  SDPCM_SHARED_VERSION,
			  sh->flags & SDPCM_SHARED_VERSION_MASK);
		return -EPROTO;
	}
	return 0;
1048 1049 1050 1051 1052 1053

fail:
	brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
		  rv, addr);
	sdio_release_host(bus->sdiodev->func[1]);
	return rv;
1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068
}

static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
{
	struct sdpcm_shared sh;

	if (brcmf_sdio_readshared(bus, &sh) == 0)
		bus->console_addr = sh.console_addr;
}
#else
static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
{
}
#endif /* DEBUG */

1069
static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1070 1071 1072 1073
{
	u32 intstatus = 0;
	u32 hmb_data;
	u8 fcbits;
1074
	int ret;
1075

1076
	brcmf_dbg(SDIO, "Enter\n");
1077 1078

	/* Read mailbox data and ack that we did so */
1079 1080
	ret = r_sdreg32(bus, &hmb_data,
			offsetof(struct sdpcmd_regs, tohostmailboxdata));
1081

1082
	if (ret == 0)
1083
		w_sdreg32(bus, SMB_INT_ACK,
1084
			  offsetof(struct sdpcmd_regs, tosbmailbox));
1085
	bus->sdcnt.f1regdata += 2;
1086 1087 1088

	/* Dongle recomposed rx frames, accept them again */
	if (hmb_data & HMB_DATA_NAKHANDLED) {
1089
		brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1090 1091
			  bus->rx_seq);
		if (!bus->rxskip)
1092
			brcmf_err("unexpected NAKHANDLED!\n");
1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105

		bus->rxskip = false;
		intstatus |= I_HMB_FRAME_IND;
	}

	/*
	 * DEVREADY does not occur with gSPI.
	 */
	if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
		bus->sdpcm_ver =
		    (hmb_data & HMB_DATA_VERSION_MASK) >>
		    HMB_DATA_VERSION_SHIFT;
		if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1106
			brcmf_err("Version mismatch, dongle reports %d, "
1107 1108 1109
				  "expecting %d\n",
				  bus->sdpcm_ver, SDPCM_PROT_VERSION);
		else
1110
			brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1111
				  bus->sdpcm_ver);
1112 1113 1114 1115 1116 1117

		/*
		 * Retrieve console state address now that firmware should have
		 * updated it.
		 */
		brcmf_sdio_get_console_addr(bus);
1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129
	}

	/*
	 * Flow Control has been moved into the RX headers and this out of band
	 * method isn't used any more.
	 * remaining backward compatible with older dongles.
	 */
	if (hmb_data & HMB_DATA_FC) {
		fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
							HMB_DATA_FCDATA_SHIFT;

		if (fcbits & ~bus->flowcontrol)
1130
			bus->sdcnt.fc_xoff++;
1131 1132

		if (bus->flowcontrol & ~fcbits)
1133
			bus->sdcnt.fc_xon++;
1134

1135
		bus->sdcnt.fc_rcvd++;
1136 1137 1138 1139 1140 1141 1142 1143 1144
		bus->flowcontrol = fcbits;
	}

	/* Shouldn't be any others */
	if (hmb_data & ~(HMB_DATA_DEVREADY |
			 HMB_DATA_NAKHANDLED |
			 HMB_DATA_FC |
			 HMB_DATA_FWREADY |
			 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1145
		brcmf_err("Unknown mailbox data content: 0x%02x\n",
1146 1147 1148 1149 1150
			  hmb_data);

	return intstatus;
}

1151
static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1152 1153 1154 1155 1156 1157
{
	uint retries = 0;
	u16 lastrbc;
	u8 hi, lo;
	int err;

1158
	brcmf_err("%sterminate frame%s\n",
1159 1160 1161 1162
		  abort ? "abort command, " : "",
		  rtx ? ", send NAK" : "");

	if (abort)
1163
		brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1164

1165 1166
	brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
			  SFC_RF_TERM, &err);
1167
	bus->sdcnt.f1regdata++;
1168 1169 1170

	/* Wait until the packet has been flushed (device/FIFO stable) */
	for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1171 1172 1173 1174
		hi = brcmf_sdiod_regrb(bus->sdiodev,
				       SBSDIO_FUNC1_RFRAMEBCHI, &err);
		lo = brcmf_sdiod_regrb(bus->sdiodev,
				       SBSDIO_FUNC1_RFRAMEBCLO, &err);
1175
		bus->sdcnt.f1regdata += 2;
1176 1177 1178 1179 1180

		if ((hi == 0) && (lo == 0))
			break;

		if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1181
			brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1182 1183 1184 1185 1186 1187
				  lastrbc, (hi << 8) + lo);
		}
		lastrbc = (hi << 8) + lo;
	}

	if (!retries)
1188
		brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1189
	else
1190
		brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1191 1192

	if (rtx) {
1193
		bus->sdcnt.rxrtx++;
1194 1195
		err = w_sdreg32(bus, SMB_NAK,
				offsetof(struct sdpcmd_regs, tosbmailbox));
1196

1197
		bus->sdcnt.f1regdata++;
1198
		if (err == 0)
1199 1200 1201 1202
			bus->rxskip = true;
	}

	/* Clear partial in any case */
1203
	bus->cur_read.len = 0;
1204 1205
}

1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227
static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
{
	struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
	u8 i, hi, lo;

	/* On failure, abort the command and terminate the frame */
	brcmf_err("sdio error, abort command and terminate frame\n");
	bus->sdcnt.tx_sderrs++;

	brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
	brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
	bus->sdcnt.f1regdata++;

	for (i = 0; i < 3; i++) {
		hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
		lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
		bus->sdcnt.f1regdata += 2;
		if ((hi == 0) && (lo == 0))
			break;
	}
}

1228
/* return total length of buffer chain */
1229
static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1230 1231 1232 1233 1234 1235 1236 1237 1238 1239
{
	struct sk_buff *p;
	uint total;

	total = 0;
	skb_queue_walk(&bus->glom, p)
		total += p->len;
	return total;
}

1240
static void brcmf_sdio_free_glom(struct