i7300_edac.c 35.3 KB
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/*
 * Intel 7300 class Memory Controllers kernel module (Clarksboro)
 *
 * This file may be distributed under the terms of the
 * GNU General Public License version 2 only.
 *
 * Copyright (c) 2010 by:
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 *	 Mauro Carvalho Chehab
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 *
 * Red Hat Inc. http://www.redhat.com
 *
 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
 *	http://www.intel.com/Assets/PDF/datasheet/318082.pdf
 *
 * TODO: The chipset allow checking for PCI Express errors also. Currently,
 *	 the driver covers only memory error errors
 *
 * This driver uses "csrows" EDAC attribute to represent DIMM slot#
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/edac.h>
#include <linux/mmzone.h>

#include "edac_core.h"

/*
 * Alter this version for the I7300 module when modifications are made
 */
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Michal Marek committed
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#define I7300_REVISION    " Ver: 1.0.0"
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#define EDAC_MOD_STR      "i7300_edac"

#define i7300_printk(level, fmt, arg...) \
	edac_printk(level, "i7300", fmt, ##arg)

#define i7300_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)

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/***********************************************
 * i7300 Limit constants Structs and static vars
 ***********************************************/

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/*
 * Memory topology is organized as:
 *	Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
 *	Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
 * Each channel can have to 8 DIMM sets (called as SLOTS)
 * Slots should generally be filled in pairs
 *	Except on Single Channel mode of operation
 *		just slot 0/channel0 filled on this mode
 *	On normal operation mode, the two channels on a branch should be
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 *		filled together for the same SLOT#
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 * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
 *		channels on both branches should be filled
 */

/* Limits for i7300 */
#define MAX_SLOTS		8
#define MAX_BRANCHES		2
#define MAX_CH_PER_BRANCH	2
#define MAX_CHANNELS		(MAX_CH_PER_BRANCH * MAX_BRANCHES)
#define MAX_MIR			3

#define to_channel(ch, branch)	((((branch)) << 1) | (ch))

#define to_csrow(slot, ch, branch)					\
		(to_channel(ch, branch) | ((slot) << 2))

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/* Device name and register DID (Device ID) */
struct i7300_dev_info {
	const char *ctl_name;	/* name for this device */
	u16 fsb_mapping_errors;	/* DID for the branchmap,control */
};

/* Table of devices attributes supported by this driver */
static const struct i7300_dev_info i7300_devs[] = {
	{
		.ctl_name = "I7300",
		.fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
	},
};

struct i7300_dimm_info {
	int megabytes;		/* size, 0 means not present  */
};

/* driver private data structure */
struct i7300_pvt {
	struct pci_dev *pci_dev_16_0_fsb_ctlr;		/* 16.0 */
	struct pci_dev *pci_dev_16_1_fsb_addr_map;	/* 16.1 */
	struct pci_dev *pci_dev_16_2_fsb_err_regs;	/* 16.2 */
	struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES];	/* 21.0  and 22.0 */

	u16 tolm;				/* top of low memory */
	u64 ambase;				/* AMB BAR */

	u32 mc_settings;			/* Report several settings */
	u32 mc_settings_a;

	u16 mir[MAX_MIR];			/* Memory Interleave Reg*/

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	u16 mtr[MAX_SLOTS][MAX_BRANCHES];	/* Memory Technlogy Reg */
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	u16 ambpresent[MAX_CHANNELS];		/* AMB present regs */

	/* DIMM information matrix, allocating architecture maximums */
	struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS];

	/* Temporary buffer for use when preparing error messages */
	char *tmp_prt_buffer;
};

/* FIXME: Why do we need to have this static? */
static struct edac_pci_ctl_info *i7300_pci;

/***************************************************
 * i7300 Register definitions for memory enumeration
 ***************************************************/

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/*
 * Device 16,
 * Function 0: System Address (not documented)
 * Function 1: Memory Branch Map, Control, Errors Register
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 */

	/* OFFSETS for Function 0 */
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#define AMBASE			0x48 /* AMB Mem Mapped Reg Region Base */
#define MAXCH			0x56 /* Max Channel Number */
#define MAXDIMMPERCH		0x57 /* Max DIMM PER Channel Number */
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	/* OFFSETS for Function 1 */
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#define MC_SETTINGS		0x40
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  #define IS_MIRRORED(mc)		((mc) & (1 << 16))
  #define IS_ECC_ENABLED(mc)		((mc) & (1 << 5))
  #define IS_RETRY_ENABLED(mc)		((mc) & (1 << 31))
  #define IS_SCRBALGO_ENHANCED(mc)	((mc) & (1 << 8))
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#define MC_SETTINGS_A		0x58
  #define IS_SINGLE_MODE(mca)		((mca) & (1 << 14))
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#define TOLM			0x6C

#define MIR0			0x80
#define MIR1			0x84
#define MIR2			0x88
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/*
 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
 * seems that we cannot use this information directly for the same usage.
 * Each memory slot may have up to 2 AMB interfaces, one for income and another
 * for outcome interface to the next slot.
 * For now, the driver just stores the AMB present registers, but rely only at
 * the MTR info to detect memory.
 * Datasheet is also not clear about how to map each AMBPRESENT registers to
 * one of the 4 available channels.
 */
#define AMBPRESENT_0	0x64
#define AMBPRESENT_1	0x66

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static const u16 mtr_regs[MAX_SLOTS] = {
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	0x80, 0x84, 0x88, 0x8c,
	0x82, 0x86, 0x8a, 0x8e
};

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/*
 * Defines to extract the vaious fields from the
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 *	MTRx - Memory Technology Registers
 */
#define MTR_DIMMS_PRESENT(mtr)		((mtr) & (1 << 8))
#define MTR_DIMMS_ETHROTTLE(mtr)	((mtr) & (1 << 7))
#define MTR_DRAM_WIDTH(mtr)		(((mtr) & (1 << 6)) ? 8 : 4)
#define MTR_DRAM_BANKS(mtr)		(((mtr) & (1 << 5)) ? 8 : 4)
#define MTR_DIMM_RANKS(mtr)		(((mtr) & (1 << 4)) ? 1 : 0)
#define MTR_DIMM_ROWS(mtr)		(((mtr) >> 2) & 0x3)
#define MTR_DRAM_BANKS_ADDR_BITS	2
#define MTR_DIMM_ROWS_ADDR_BITS(mtr)	(MTR_DIMM_ROWS(mtr) + 13)
#define MTR_DIMM_COLS(mtr)		((mtr) & 0x3)
#define MTR_DIMM_COLS_ADDR_BITS(mtr)	(MTR_DIMM_COLS(mtr) + 10)

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/************************************************
 * i7300 Register definitions for error detection
 ************************************************/
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/*
 * Device 16.1: FBD Error Registers
 */
#define FERR_FAT_FBD	0x98
static const char *ferr_fat_fbd_name[] = {
	[22] = "Non-Redundant Fast Reset Timeout",
	[2]  = ">Tmid Thermal event with intelligent throttling disabled",
	[1]  = "Memory or FBD configuration CRC read error",
	[0]  = "Memory Write error on non-redundant retry or "
	       "FBD configuration Write error on retry",
};
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#define GET_FBD_FAT_IDX(fbderr)	(((fbderr) >> 28) & 3)
#define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 22))
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#define FERR_NF_FBD	0xa0
static const char *ferr_nf_fbd_name[] = {
	[24] = "DIMM-Spare Copy Completed",
	[23] = "DIMM-Spare Copy Initiated",
	[22] = "Redundant Fast Reset Timeout",
	[21] = "Memory Write error on redundant retry",
	[18] = "SPD protocol Error",
	[17] = "FBD Northbound parity error on FBD Sync Status",
	[16] = "Correctable Patrol Data ECC",
	[15] = "Correctable Resilver- or Spare-Copy Data ECC",
	[14] = "Correctable Mirrored Demand Data ECC",
	[13] = "Correctable Non-Mirrored Demand Data ECC",
	[11] = "Memory or FBD configuration CRC read error",
	[10] = "FBD Configuration Write error on first attempt",
	[9]  = "Memory Write error on first attempt",
	[8]  = "Non-Aliased Uncorrectable Patrol Data ECC",
	[7]  = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
	[6]  = "Non-Aliased Uncorrectable Mirrored Demand Data ECC",
	[5]  = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
	[4]  = "Aliased Uncorrectable Patrol Data ECC",
	[3]  = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
	[2]  = "Aliased Uncorrectable Mirrored Demand Data ECC",
	[1]  = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
	[0]  = "Uncorrectable Data ECC on Replay",
};
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#define GET_FBD_NF_IDX(fbderr)	(((fbderr) >> 28) & 3)
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#define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\
			      (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\
			      (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\
			      (1 << 9)  | (1 << 8)  | (1 << 7)  | (1 << 6)  |\
			      (1 << 5)  | (1 << 4)  | (1 << 3)  | (1 << 2)  |\
			      (1 << 1)  | (1 << 0))

#define EMASK_FBD	0xa8
#define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\
			    (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\
			    (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\
			    (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\
			    (1 << 9)  | (1 << 8)  | (1 << 7)  | (1 << 6)  |\
			    (1 << 5)  | (1 << 4)  | (1 << 3)  | (1 << 2)  |\
			    (1 << 1)  | (1 << 0))

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/*
 * Device 16.2: Global Error Registers
 */

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#define FERR_GLOBAL_HI	0x48
static const char *ferr_global_hi_name[] = {
	[3] = "FSB 3 Fatal Error",
	[2] = "FSB 2 Fatal Error",
	[1] = "FSB 1 Fatal Error",
	[0] = "FSB 0 Fatal Error",
};
#define ferr_global_hi_is_fatal(errno)	1

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#define FERR_GLOBAL_LO	0x40
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static const char *ferr_global_lo_name[] = {
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	[31] = "Internal MCH Fatal Error",
	[30] = "Intel QuickData Technology Device Fatal Error",
	[29] = "FSB1 Fatal Error",
	[28] = "FSB0 Fatal Error",
	[27] = "FBD Channel 3 Fatal Error",
	[26] = "FBD Channel 2 Fatal Error",
	[25] = "FBD Channel 1 Fatal Error",
	[24] = "FBD Channel 0 Fatal Error",
	[23] = "PCI Express Device 7Fatal Error",
	[22] = "PCI Express Device 6 Fatal Error",
	[21] = "PCI Express Device 5 Fatal Error",
	[20] = "PCI Express Device 4 Fatal Error",
	[19] = "PCI Express Device 3 Fatal Error",
	[18] = "PCI Express Device 2 Fatal Error",
	[17] = "PCI Express Device 1 Fatal Error",
	[16] = "ESI Fatal Error",
	[15] = "Internal MCH Non-Fatal Error",
	[14] = "Intel QuickData Technology Device Non Fatal Error",
	[13] = "FSB1 Non-Fatal Error",
	[12] = "FSB 0 Non-Fatal Error",
	[11] = "FBD Channel 3 Non-Fatal Error",
	[10] = "FBD Channel 2 Non-Fatal Error",
	[9]  = "FBD Channel 1 Non-Fatal Error",
	[8]  = "FBD Channel 0 Non-Fatal Error",
	[7]  = "PCI Express Device 7 Non-Fatal Error",
	[6]  = "PCI Express Device 6 Non-Fatal Error",
	[5]  = "PCI Express Device 5 Non-Fatal Error",
	[4]  = "PCI Express Device 4 Non-Fatal Error",
	[3]  = "PCI Express Device 3 Non-Fatal Error",
	[2]  = "PCI Express Device 2 Non-Fatal Error",
	[1]  = "PCI Express Device 1 Non-Fatal Error",
	[0]  = "ESI Non-Fatal Error",
};
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#define ferr_global_lo_is_fatal(errno)	((errno < 16) ? 0 : 1)
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#define NRECMEMA	0xbe
  #define NRECMEMA_BANK(v)	(((v) >> 12) & 7)
  #define NRECMEMA_RANK(v)	(((v) >> 8) & 15)

#define NRECMEMB	0xc0
  #define NRECMEMB_IS_WR(v)	((v) & (1 << 31))
  #define NRECMEMB_CAS(v)	(((v) >> 16) & 0x1fff)
  #define NRECMEMB_RAS(v)	((v) & 0xffff)

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#define REDMEMA		0xdc

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#define REDMEMB		0x7c
  #define IS_SECOND_CH(v)	((v) * (1 << 17))

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#define RECMEMA		0xe0
  #define RECMEMA_BANK(v)	(((v) >> 12) & 7)
  #define RECMEMA_RANK(v)	(((v) >> 8) & 15)

#define RECMEMB		0xe4
  #define RECMEMB_IS_WR(v)	((v) & (1 << 31))
  #define RECMEMB_CAS(v)	(((v) >> 16) & 0x1fff)
  #define RECMEMB_RAS(v)	((v) & 0xffff)

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/********************************************
 * i7300 Functions related to error detection
 ********************************************/
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/**
 * get_err_from_table() - Gets the error message from a table
 * @table:	table name (array of char *)
 * @size:	number of elements at the table
 * @pos:	position of the element to be returned
 *
 * This is a small routine that gets the pos-th element of a table. If the
 * element doesn't exist (or it is empty), it returns "reserved".
 * Instead of calling it directly, the better is to call via the macro
 * GET_ERR_FROM_TABLE(), that automatically checks the table size via
 * ARRAY_SIZE() macro
 */
static const char *get_err_from_table(const char *table[], int size, int pos)
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{
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	if (unlikely(pos >= size))
		return "Reserved";

	if (unlikely(!table[pos]))
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		return "Reserved";

	return table[pos];
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}

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#define GET_ERR_FROM_TABLE(table, pos)				\
	get_err_from_table(table, ARRAY_SIZE(table), pos)

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/**
 * i7300_process_error_global() - Retrieve the hardware error information from
 *				  the hardware global error registers and
 *				  sends it to dmesg
 * @mci: struct mem_ctl_info pointer
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 */
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static void i7300_process_error_global(struct mem_ctl_info *mci)
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{
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	struct i7300_pvt *pvt;
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	u32 errnum, error_reg;
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	unsigned long errors;
	const char *specific;
	bool is_fatal;
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	pvt = mci->pvt_info;
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	/* read in the 1st FATAL error register */
	pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
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			      FERR_GLOBAL_HI, &error_reg);
	if (unlikely(error_reg)) {
		errors = error_reg;
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		errnum = find_first_bit(&errors,
					ARRAY_SIZE(ferr_global_hi_name));
		specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum);
		is_fatal = ferr_global_hi_is_fatal(errnum);
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		/* Clear the error bit */
		pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
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				       FERR_GLOBAL_HI, error_reg);
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		goto error_global;
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	}

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	pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
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			      FERR_GLOBAL_LO, &error_reg);
	if (unlikely(error_reg)) {
		errors = error_reg;
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		errnum = find_first_bit(&errors,
					ARRAY_SIZE(ferr_global_lo_name));
		specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum);
		is_fatal = ferr_global_lo_is_fatal(errnum);
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		/* Clear the error bit */
		pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
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				       FERR_GLOBAL_LO, error_reg);
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		goto error_global;
	}
	return;
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error_global:
	i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s\n",
			is_fatal ? "Fatal" : "NOT fatal", specific);
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}

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/**
 * i7300_process_fbd_error() - Retrieve the hardware error information from
 *			       the FBD error registers and sends it via
 *			       EDAC error API calls
 * @mci: struct mem_ctl_info pointer
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 */
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static void i7300_process_fbd_error(struct mem_ctl_info *mci)
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{
	struct i7300_pvt *pvt;
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	u32 errnum, value, error_reg;
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	u16 val16;
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	unsigned branch, channel, bank, rank, cas, ras;
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	u32 syndrome;

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	unsigned long errors;
	const char *specific;
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	bool is_wr;
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	pvt = mci->pvt_info;

	/* read in the 1st FATAL error register */
	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
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			      FERR_FAT_FBD, &error_reg);
	if (unlikely(error_reg & FERR_FAT_FBD_ERR_MASK)) {
		errors = error_reg & FERR_FAT_FBD_ERR_MASK ;
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		errnum = find_first_bit(&errors,
					ARRAY_SIZE(ferr_fat_fbd_name));
		specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum);
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		branch = (GET_FBD_FAT_IDX(error_reg) == 2) ? 1 : 0;
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		pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
				     NRECMEMA, &val16);
		bank = NRECMEMA_BANK(val16);
		rank = NRECMEMA_RANK(val16);

		pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
				NRECMEMB, &value);
		is_wr = NRECMEMB_IS_WR(value);
		cas = NRECMEMB_CAS(value);
		ras = NRECMEMB_RAS(value);

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		/* Clean the error register */
		pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
				FERR_FAT_FBD, error_reg);

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		snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
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			 "Bank=%d RAS=%d CAS=%d Err=0x%lx (%s))",
			 bank, ras, cas, errors, specific);

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		edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 1, 0, 0, 0,
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				     branch, -1, rank,
				     is_wr ? "Write error" : "Read error",
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				     pvt->tmp_prt_buffer);
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	}

	/* read in the 1st NON-FATAL error register */
	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
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			      FERR_NF_FBD, &error_reg);
	if (unlikely(error_reg & FERR_NF_FBD_ERR_MASK)) {
		errors = error_reg & FERR_NF_FBD_ERR_MASK;
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		errnum = find_first_bit(&errors,
					ARRAY_SIZE(ferr_nf_fbd_name));
		specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum);
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		branch = (GET_FBD_NF_IDX(error_reg) == 2) ? 1 : 0;
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		pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
			REDMEMA, &syndrome);

		pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
				     RECMEMA, &val16);
		bank = RECMEMA_BANK(val16);
		rank = RECMEMA_RANK(val16);

		pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
				RECMEMB, &value);
		is_wr = RECMEMB_IS_WR(value);
		cas = RECMEMB_CAS(value);
		ras = RECMEMB_RAS(value);
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		pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
				     REDMEMB, &value);
		channel = (branch << 1);
		if (IS_SECOND_CH(value))
			channel++;

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		/* Clear the error bit */
		pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
				FERR_NF_FBD, error_reg);

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		/* Form out message */
		snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
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			 "DRAM-Bank=%d RAS=%d CAS=%d, Err=0x%lx (%s))",
			 bank, ras, cas, errors, specific);

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		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0,
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				     syndrome,
				     branch >> 1, channel % 2, rank,
				     is_wr ? "Write error" : "Read error",
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				     pvt->tmp_prt_buffer);
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	}
	return;
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}

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/**
 * i7300_check_error() - Calls the error checking subroutines
 * @mci: struct mem_ctl_info pointer
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 */
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static void i7300_check_error(struct mem_ctl_info *mci)
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{
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	i7300_process_error_global(mci);
	i7300_process_fbd_error(mci);
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};
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/**
 * i7300_clear_error() - Clears the error registers
 * @mci: struct mem_ctl_info pointer
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 */
static void i7300_clear_error(struct mem_ctl_info *mci)
{
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	struct i7300_pvt *pvt = mci->pvt_info;
	u32 value;
	/*
	 * All error values are RWC - we need to read and write 1 to the
	 * bit that we want to cleanup
	 */
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	/* Clear global error registers */
	pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
			      FERR_GLOBAL_HI, &value);
	pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
			      FERR_GLOBAL_HI, value);

	pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
			      FERR_GLOBAL_LO, &value);
	pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
			      FERR_GLOBAL_LO, value);

	/* Clear FBD error registers */
	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
			      FERR_FAT_FBD, &value);
	pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
			      FERR_FAT_FBD, value);

	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
			      FERR_NF_FBD, &value);
	pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
			      FERR_NF_FBD, value);
551 552
}

553 554 555 556
/**
 * i7300_enable_error_reporting() - Enable the memory reporting logic at the
 *				    hardware
 * @mci: struct mem_ctl_info pointer
557 558 559
 */
static void i7300_enable_error_reporting(struct mem_ctl_info *mci)
{
560 561 562 563 564 565 566 567 568 569 570 571
	struct i7300_pvt *pvt = mci->pvt_info;
	u32 fbd_error_mask;

	/* Read the FBD Error Mask Register */
	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
			      EMASK_FBD, &fbd_error_mask);

	/* Enable with a '0' */
	fbd_error_mask &= ~(EMASK_FBD_ERR_MASK);

	pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
			       EMASK_FBD, fbd_error_mask);
572
}
573 574 575 576

/************************************************
 * i7300 Functions related to memory enumberation
 ************************************************/
577

578 579 580 581 582 583 584 585
/**
 * decode_mtr() - Decodes the MTR descriptor, filling the edac structs
 * @pvt: pointer to the private data struct used by i7300 driver
 * @slot: DIMM slot (0 to 7)
 * @ch: Channel number within the branch (0 or 1)
 * @branch: Branch number (0 or 1)
 * @dinfo: Pointer to DIMM info where dimm size is stored
 * @p_csrow: Pointer to the struct csrow_info that corresponds to that element
586 587 588 589
 */
static int decode_mtr(struct i7300_pvt *pvt,
		      int slot, int ch, int branch,
		      struct i7300_dimm_info *dinfo,
590
		      struct dimm_info *dimm)
591 592 593 594 595 596 597 598
{
	int mtr, ans, addrBits, channel;

	channel = to_channel(ch, branch);

	mtr = pvt->mtr[slot][branch];
	ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;

599 600
	edac_dbg(2, "\tMTR%d CH%d: DIMMs are %sPresent (mtr)\n",
		 slot, channel, ans ? "" : "NOT ");
601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621

	/* Determine if there is a DIMM present in this DIMM slot */
	if (!ans)
		return 0;

	/* Start with the number of bits for a Bank
	* on the DRAM */
	addrBits = MTR_DRAM_BANKS_ADDR_BITS;
	/* Add thenumber of ROW bits */
	addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
	/* add the number of COLUMN bits */
	addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
	/* add the number of RANK bits */
	addrBits += MTR_DIMM_RANKS(mtr);

	addrBits += 6;	/* add 64 bits per DIMM */
	addrBits -= 20;	/* divide by 2^^20 */
	addrBits -= 3;	/* 8 bits per bytes */

	dinfo->megabytes = 1 << addrBits;

622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640
	edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));

	edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n",
		 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");

	edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
	edac_dbg(2, "\t\tNUMRANK: %s\n",
		 MTR_DIMM_RANKS(mtr) ? "double" : "single");
	edac_dbg(2, "\t\tNUMROW: %s\n",
		 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
		 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
		 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
		 "65,536 - 16 rows");
	edac_dbg(2, "\t\tNUMCOL: %s\n",
		 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
		 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
		 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
		 "reserved");
	edac_dbg(2, "\t\tSIZE: %d MB\n", dinfo->megabytes);
641

642
	/*
643
	 * The type of error detection actually depends of the
644
	 * mode of operation. When it is just one single memory chip, at
645 646
	 * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
	 * In normal or mirrored mode, it uses Lockstep mode,
647 648 649
	 * with the possibility of using an extended algorithm for x8 memories
	 * See datasheet Sections 7.3.6 to 7.3.8
	 */
650

651
	dimm->nr_pages = MiB_TO_PAGES(dinfo->megabytes);
652 653
	dimm->grain = 8;
	dimm->mtype = MEM_FB_DDR2;
654
	if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
655
		dimm->edac_mode = EDAC_SECDED;
656
		edac_dbg(2, "\t\tECC code is 8-byte-over-32-byte SECDED+ code\n");
657
	} else {
658
		edac_dbg(2, "\t\tECC code is on Lockstep mode\n");
659
		if (MTR_DRAM_WIDTH(mtr) == 8)
660
			dimm->edac_mode = EDAC_S8ECD8ED;
661
		else
662
			dimm->edac_mode = EDAC_S4ECD4ED;
663
	}
664 665

	/* ask what device type on this row */
666
	if (MTR_DRAM_WIDTH(mtr) == 8) {
667 668 669
		edac_dbg(2, "\t\tScrub algorithm for x8 is on %s mode\n",
			 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
			 "enhanced" : "normal");
670

671
		dimm->dtype = DEV_X8;
672
	} else
673
		dimm->dtype = DEV_X4;
674 675 676 677

	return mtr;
}

678 679 680
/**
 * print_dimm_size() - Prints dump of the memory organization
 * @pvt: pointer to the private data struct used by i7300 driver
681
 *
682
 * Useful for debug. If debug is disabled, this routine do nothing
683 684 685
 */
static void print_dimm_size(struct i7300_pvt *pvt)
{
686
#ifdef CONFIG_EDAC_DEBUG
687
	struct i7300_dimm_info *dinfo;
688
	char *p;
689 690 691 692
	int space, n;
	int channel, slot;

	space = PAGE_SIZE;
693
	p = pvt->tmp_prt_buffer;
694 695 696 697 698 699 700 701 702

	n = snprintf(p, space, "              ");
	p += n;
	space -= n;
	for (channel = 0; channel < MAX_CHANNELS; channel++) {
		n = snprintf(p, space, "channel %d | ", channel);
		p += n;
		space -= n;
	}
703
	edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
704
	p = pvt->tmp_prt_buffer;
705 706
	space = PAGE_SIZE;
	n = snprintf(p, space, "-------------------------------"
707
			       "------------------------------");
708 709
	p += n;
	space -= n;
710
	edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
711
	p = pvt->tmp_prt_buffer;
712 713 714 715 716 717 718 719 720 721 722 723 724 725
	space = PAGE_SIZE;

	for (slot = 0; slot < MAX_SLOTS; slot++) {
		n = snprintf(p, space, "csrow/SLOT %d  ", slot);
		p += n;
		space -= n;

		for (channel = 0; channel < MAX_CHANNELS; channel++) {
			dinfo = &pvt->dimm_info[slot][channel];
			n = snprintf(p, space, "%4d MB   | ", dinfo->megabytes);
			p += n;
			space -= n;
		}

726
		edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
727
		p = pvt->tmp_prt_buffer;
728 729 730 731
		space = PAGE_SIZE;
	}

	n = snprintf(p, space, "-------------------------------"
732
			       "------------------------------");
733 734
	p += n;
	space -= n;
735
	edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
736
	p = pvt->tmp_prt_buffer;
737
	space = PAGE_SIZE;
738
#endif
739 740
}

741 742 743 744 745
/**
 * i7300_init_csrows() - Initialize the 'csrows' table within
 *			 the mci control structure with the
 *			 addressing of memory.
 * @mci: struct mem_ctl_info pointer
746 747 748 749 750
 */
static int i7300_init_csrows(struct mem_ctl_info *mci)
{
	struct i7300_pvt *pvt;
	struct i7300_dimm_info *dinfo;
751
	int rc = -ENODEV;
752
	int mtr;
753
	int ch, branch, slot, channel, max_channel, max_branch;
754
	struct dimm_info *dimm;
755 756 757

	pvt = mci->pvt_info;

758
	edac_dbg(2, "Memory Technology Registers:\n");
759

760 761 762 763 764 765 766 767
	if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
		max_branch = 1;
		max_channel = 1;
	} else {
		max_branch = MAX_BRANCHES;
		max_channel = MAX_CH_PER_BRANCH;
	}

768
	/* Get the AMB present registers for the four channels */
769
	for (branch = 0; branch < max_branch; branch++) {
770 771
		/* Read and dump branch 0's MTRs */
		channel = to_channel(0, branch);
772 773
		pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
				     AMBPRESENT_0,
774
				&pvt->ambpresent[channel]);
775 776
		edac_dbg(2, "\t\tAMB-present CH%d = 0x%x:\n",
			 channel, pvt->ambpresent[channel]);
777

778 779 780
		if (max_channel == 1)
			continue;

781
		channel = to_channel(1, branch);
782 783
		pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
				     AMBPRESENT_1,
784
				&pvt->ambpresent[channel]);
785 786
		edac_dbg(2, "\t\tAMB-present CH%d = 0x%x:\n",
			 channel, pvt->ambpresent[channel]);
787 788 789 790 791
	}

	/* Get the set of MTR[0-7] regs by each branch */
	for (slot = 0; slot < MAX_SLOTS; slot++) {
		int where = mtr_regs[slot];
792
		for (branch = 0; branch < max_branch; branch++) {
793
			pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
794 795
					where,
					&pvt->mtr[slot][branch]);
796
			for (ch = 0; ch < max_channel; ch++) {
797 798
				int channel = to_channel(ch, branch);

799 800
				dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
					       mci->n_layers, branch, ch, slot);
801

802
				dinfo = &pvt->dimm_info[slot][channel];
803

804
				mtr = decode_mtr(pvt, slot, ch, branch,
805 806
						 dinfo, dimm);

807 808 809 810
				/* if no DIMMS on this row, continue */
				if (!MTR_DIMMS_PRESENT(mtr))
					continue;

811
				rc = 0;
812

813 814 815 816
			}
		}
	}

817
	return rc;
818 819
}

820 821 822 823 824
/**
 * decode_mir() - Decodes Memory Interleave Register (MIR) info
 * @int mir_no: number of the MIR register to decode
 * @mir: array with the MIR data cached on the driver
 */
825 826 827
static void decode_mir(int mir_no, u16 mir[MAX_MIR])
{
	if (mir[mir_no] & 3)
828 829 830 831 832
		edac_dbg(2, "MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n",
			 mir_no,
			 (mir[mir_no] >> 4) & 0xfff,
			 (mir[mir_no] & 1) ? "B0" : "",
			 (mir[mir_no] & 2) ? "B1" : "");
833 834
}

835 836 837
/**
 * i7300_get_mc_regs() - Get the contents of the MC enumeration registers
 * @mci: struct mem_ctl_info pointer
838
 *
839
 * Data read is cached internally for its usage when needed
840 841 842 843 844 845 846 847 848
 */
static int i7300_get_mc_regs(struct mem_ctl_info *mci)
{
	struct i7300_pvt *pvt;
	u32 actual_tolm;
	int i, rc;

	pvt = mci->pvt_info;

849
	pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE,
850 851
			(u32 *) &pvt->ambase);

852
	edac_dbg(2, "AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
853 854

	/* Get the Branch Map regs */
855
	pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm);
856
	pvt->tolm >>= 12;
857 858
	edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n",
		 pvt->tolm, pvt->tolm);
859 860

	actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
861 862
	edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
		 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
863

864
	/* Get memory controller settings */
865
	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS,
866
			     &pvt->mc_settings);
867 868
	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A,
			     &pvt->mc_settings_a);
869

870
	if (IS_SINGLE_MODE(pvt->mc_settings_a))
871
		edac_dbg(0, "Memory controller operating on single mode\n");
872
	else
873 874
		edac_dbg(0, "Memory controller operating on %smirrored mode\n",
			 IS_MIRRORED(pvt->mc_settings) ? "" : "non-");
875

876 877 878 879
	edac_dbg(0, "Error detection is %s\n",
		 IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
	edac_dbg(0, "Retry is %s\n",
		 IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
880 881

	/* Get Memory Interleave Range registers */
882 883 884 885 886 887
	pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0,
			     &pvt->mir[0]);
	pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1,
			     &pvt->mir[1]);
	pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2,
			     &pvt->mir[2]);
888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903

	/* Decode the MIR regs */
	for (i = 0; i < MAX_MIR; i++)
		decode_mir(i, pvt->mir);

	rc = i7300_init_csrows(mci);
	if (rc < 0)
		return rc;

	/* Go and determine the size of each DIMM and place in an
	 * orderly matrix */
	print_dimm_size(pvt);

	return 0;
}

904 905 906 907
/*************************************************
 * i7300 Functions related to device probe/release
 *************************************************/

908 909 910
/**
 * i7300_put_devices() - Release the PCI devices
 * @mci: struct mem_ctl_info pointer
911 912 913 914 915 916 917 918 919 920
 */
static void i7300_put_devices(struct mem_ctl_info *mci)
{
	struct i7300_pvt *pvt;
	int branch;

	pvt = mci->pvt_info;

	/* Decrement usage count for devices */
	for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++)
921 922 923
		pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]);
	pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs);
	pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map);
924 925
}

926 927 928 929
/**
 * i7300_get_devices() - Find and perform 'get' operation on the MCH's
 *			 device/functions we want to reference for this driver
 * @mci: struct mem_ctl_info pointer
930
 *
931 932 933 934 935
 * Access and prepare the several devices for usage:
 * I7300 devices used by this driver:
 *    Device 16, functions 0,1 and 2:	PCI_DEVICE_ID_INTEL_I7300_MCH_ERR
 *    Device 21 function 0:		PCI_DEVICE_ID_INTEL_I7300_MCH_FB0
 *    Device 22 function 0:		PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
936
 */
937
static int i7300_get_devices(struct mem_ctl_info *mci)
938 939 940 941 942 943 944 945
{
	struct i7300_pvt *pvt;
	struct pci_dev *pdev;

	pvt = mci->pvt_info;

	/* Attempt to 'get' the MCH register we want */
	pdev = NULL;
946 947 948
	while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
				      PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
				      pdev))) {
949 950 951
		/* Store device 16 funcs 1 and 2 */
		switch (PCI_FUNC(pdev->devfn)) {
		case 1:
952 953 954
			if (!pvt->pci_dev_16_1_fsb_addr_map)
				pvt->pci_dev_16_1_fsb_addr_map =
							pci_dev_get(pdev);
955 956
			break;
		case 2:
957 958 959
			if (!pvt->pci_dev_16_2_fsb_err_regs)
				pvt->pci_dev_16_2_fsb_err_regs =
							pci_dev_get(pdev);
960 961 962 963
			break;
		}
	}

964 965 966 967 968 969 970 971 972 973 974
	if (!pvt->pci_dev_16_1_fsb_addr_map ||
	    !pvt->pci_dev_16_2_fsb_err_regs) {
		/* At least one device was not found */
		i7300_printk(KERN_ERR,
			"'system address,Process Bus' device not found:"
			"vendor 0x%x device 0x%x ERR funcs (broken BIOS?)\n",
			PCI_VENDOR_ID_INTEL,
			PCI_DEVICE_ID_INTEL_I7300_MCH_ERR);
		goto error;
	}

975 976 977 978 979 980 981 982 983 984 985 986
	edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s  %x:%x\n",
		 pci_name(pvt->pci_dev_16_0_fsb_ctlr),
		 pvt->pci_dev_16_0_fsb_ctlr->vendor,
		 pvt->pci_dev_16_0_fsb_ctlr->device);
	edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s  %x:%x\n",
		 pci_name(pvt->pci_dev_16_1_fsb_addr_map),
		 pvt->pci_dev_16_1_fsb_addr_map->vendor,
		 pvt->pci_dev_16_1_fsb_addr_map->device);
	edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s  %x:%x\n",
		 pci_name(pvt->pci_dev_16_2_fsb_err_regs),
		 pvt->pci_dev_16_2_fsb_err_regs->vendor,
		 pvt->pci_dev_16_2_fsb_err_regs->device);
987

988
	pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
989
					    PCI_DEVICE_ID_INTEL_I7300_MCH_FB0,
990
					    NULL);
991
	if (!pvt->pci_dev_2x_0_fbd_branch[0]) {
992 993 994 995 996 997 998
		i7300_printk(KERN_ERR,
			"MC: 'BRANCH 0' device not found:"
			"vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
			PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0);
		goto error;
	}

999
	pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL,
1000 1001
					    PCI_DEVICE_ID_INTEL_I7300_MCH_FB1,
					    NULL);
1002
	if (!pvt->pci_dev_2x_0_fbd_branch[1]) {
1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018
		i7300_printk(KERN_ERR,
			"MC: 'BRANCH 1' device not found:"
			"vendor 0x%x device 0x%x Func 0 "
			"(broken BIOS?)\n",
			PCI_VENDOR_ID_INTEL,
			PCI_DEVICE_ID_INTEL_I7300_MCH_FB1);
		goto error;
	}

	return 0;

error:
	i7300_put_devices(mci);
	return -ENODEV;
}

1019 1020 1021 1022
/**
 * i7300_init_one() - Probe for one instance of the device
 * @pdev: struct pci_dev pointer
 * @id: struct pci_device_id pointer - currently unused
1023
 */
1024
static int i7300_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1025 1026
{
	struct mem_ctl_info *mci;
1027
	struct edac_mc_layer layers[3];
1028
	struct i7300_pvt *pvt;
1029
	int rc;
1030

1031 1032 1033 1034
	/* wake up device */
	rc = pci_enable_device(pdev);
	if (rc == -EIO)
		return rc;
1035

1036 1037 1038
	edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
		 pdev->bus->number,
		 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1039 1040 1041 1042 1043 1044

	/* We only are looking for func 0 of the set */
	if (PCI_FUNC(pdev->devfn) != 0)
		return -ENODEV;

	/* allocate a new MC control structure */
1045 1046 1047 1048 1049 1050 1051 1052 1053
	layers[0].type = EDAC_MC_LAYER_BRANCH;
	layers[0].size = MAX_BRANCHES;
	layers[0].is_virt_csrow = false;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = MAX_CH_PER_BRANCH;
	layers[1].is_virt_csrow = true;
	layers[2].type = EDAC_MC_LAYER_SLOT;
	layers[2].size = MAX_SLOTS;
	layers[2].is_virt_csrow = true;
1054
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
1055 1056 1057
	if (mci == NULL)
		return -ENOMEM;

1058
	edac_dbg(0, "MC: mci = %p\n", mci);
1059

1060
	mci->pdev = &pdev->dev;	/* record ptr  to the generic device */
1061 1062

	pvt = mci->pvt_info;
1063
	pvt->pci_dev_16_0_fsb_ctlr = pdev;	/* Record this device in our private */
1064

1065 1066 1067 1068 1069 1070
	pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL);
	if (!pvt->tmp_prt_buffer) {
		edac_mc_free(mci);
		return -ENOMEM;
	}

1071
	/* 'get' the pci devices we want to reserve for our use */
1072
	if (i7300_get_devices(mci))
1073 1074 1075 1076 1077 1078 1079 1080
		goto fail0;

	mci->mc_idx = 0;
	mci->mtype_cap = MEM_FLAG_FB_DDR2;
	mci->edac_ctl_cap = EDAC_FLAG_NONE;
	mci->edac_cap = EDAC_FLAG_NONE;
	mci->mod_name = "i7300_edac.c";
	mci->mod_ver = I7300_REVISION;
1081
	mci->ctl_name = i7300_devs[0].ctl_name;
1082 1083 1084 1085 1086 1087 1088 1089 1090
	mci->dev_name = pci_name(pdev);
	mci->ctl_page_to_phys = NULL;

	/* Set the function pointer to an actual operation function */
	mci->edac_check = i7300_check_error;

	/* initialize the MC control structure 'csrows' table
	 * with the mapping and control information */
	if (i7300_get_mc_regs(mci)) {
1091
		edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i7300_init_csrows() returned nonzero value\n");
1092 1093
		mci->edac_cap = EDAC_FLAG_NONE;	/* no csrows found */
	} else {
1094
		edac_dbg(1, "MC: Enable error reporting now\n");
1095 1096 1097 1098 1099
		i7300_enable_error_reporting(mci);
	}

	/* add this new MC control structure to EDAC's list of MCs */
	if (edac_mc_add_mc(mci)) {
1100
		edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127
		/* FIXME: perhaps some code should go here that disables error
		 * reporting if we just enabled it
		 */
		goto fail1;
	}

	i7300_clear_error(mci);

	/* allocating generic PCI control info */
	i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!i7300_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	return 0;

	/* Error exit unwinding stack */
fail1:

	i7300_put_devices(mci);

fail0:
1128
	kfree(pvt->tmp_prt_buffer);
1129 1130 1131 1132
	edac_mc_free(mci);
	return -ENODEV;
}

1133 1134 1135
/**
 * i7300_remove_one() - Remove the driver
 * @pdev: struct pci_dev pointer
1136
 */
1137
static void i7300_remove_one(struct pci_dev *pdev)
1138 1139
{
	struct mem_ctl_info *mci;
1140
	char *tmp;
1141

1142
	edac_dbg(0, "\n");
1143 1144 1145 1146 1147 1148 1149 1150

	if (i7300_pci)
		edac_pci_release_generic_ctl(i7300_pci);

	mci = edac_mc_del_mc(&pdev->dev);
	if (!mci)
		return;

1151 1152
	tmp = ((struct i7300_pvt *)mci->pvt_info)->tmp_prt_buffer;

1153 1154 1155
	/* retrieve references to resources, and free those resources */
	i7300_put_devices(mci);

1156
	kfree(tmp);
1157 1158 1159 1160
	edac_mc_free(mci);
}

/*
1161
 * pci_device_id: table for which devices we are looking for
1162
 *
1163
 * Has only 8086:360c PCI ID
1164
 */
1165
static const struct pci_device_id i7300_pci_tbl[] = {
1166 1167 1168 1169 1170 1171 1172
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
	{0,}			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i7300_pci_tbl);

/*
1173
 * i7300_driver: pci_driver structure for this module
1174 1175 1176 1177
 */
static struct pci_driver i7300_driver = {
	.name = "i7300_edac",
	.probe = i7300_init_one,
1178
	.remove = i7300_remove_one,
1179 1180 1181
	.id_table = i7300_pci_tbl,
};

1182 1183
/**
 * i7300_init() - Registers the driver
1184 1185 1186 1187 1188
 */
static int __init i7300_init(void)
{
	int pci_rc;

1189
	edac_dbg(2, "\n");
1190 1191 1192 1193 1194 1195 1196 1197 1198

	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	opstate_init();

	pci_rc = pci_register_driver(&i7300_driver);

	return (pci_rc < 0) ? pci_rc : 0;
}

1199 1200
/**
 * i7300_init() - Unregisters the driver
1201 1202 1203
 */
static void __exit i7300_exit(void)
{
1204
	edac_dbg(2, "\n");
1205 1206 1207 1208 1209 1210 1211
	pci_unregister_driver(&i7300_driver);
}

module_init(i7300_init);
module_exit(i7300_exit);

MODULE_LICENSE("GPL");
1212
MODULE_AUTHOR("Mauro Carvalho Chehab");
1213 1214 1215 1216 1217 1218
MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
		   I7300_REVISION);

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");