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  • Will Deacon's avatar
    arm64: cpufeature: Fix CTR_EL0 field definitions · be68a8aa
    Will Deacon authored
    
    
    Our field definitions for CTR_EL0 suffer from a number of problems:
    
      - The IDC and DIC fields are missing, which causes us to enable CTR
        trapping on CPUs with either of these returning non-zero values.
    
      - The ERG is FTR_LOWER_SAFE, whereas it should be treated like CWG as
        FTR_HIGHER_SAFE so that applications can use it to avoid false sharing.
    
      - [nit] A RES1 field is described as "RAO"
    
    This patch updates the CTR_EL0 field definitions to fix these issues.
    
    Cc: <stable@vger.kernel.org>
    Cc: Shanker Donthineni <shankerd@codeaurora.org>
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    be68a8aa