Commit 19fe4165 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'edac_for_4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp

Pull EDAC updates from Borislav Petkov:
 "A lot of movement in the EDAC tree this time around, coarse summary
  below:

   - Altera Arria10 enablement of NAND, DMA, USB, QSPI and SD-MMC FIFO
     buffers (Thor Thayer)

   - split the memory controller part out of mpc85xx and share it with a
     new Freescale ARM Layerscape driver (York Sun)

   - amd64_edac fixes (Yazen Ghannam)

   - misc cleanups, refactoring and fixes all over the place"

* tag 'edac_for_4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: (37 commits)
  EDAC, altera: Add IRQ Flags to disable IRQ while handling
  EDAC, altera: Correct EDAC IRQ error message
  EDAC, amd64: Autoload module using x86_cpu_id
  EDAC, sb_edac: Remove NULL pointer check on array pci_tad
  EDAC: Remove NO_IRQ from powerpc-only drivers
  EDAC, fsl_ddr: Fix error return code in fsl_mc_err_probe()
  EDAC, fsl_ddr: Add entry to MAINTAINERS
  EDAC: Move Doug Thompson to CREDITS
  EDAC, I3000: Orphan driver
  EDAC, fsl_ddr: Replace simple_strtoul() with kstrtoul()
  EDAC, layerscape: Add Layerscape EDAC support
  EDAC, fsl_ddr: Fix IRQ dispose warning when module is removed
  EDAC, fsl_ddr: Add support for little endian
  EDAC, fsl_ddr: Add missing DDR DRAM types
  EDAC, fsl_ddr: Rename macros and names
  EDAC, fsl-ddr: Separate FSL DDR driver from MPC85xx
  EDAC, mpc85xx: Replace printk() with pr_* format
  EDAC, mpc85xx: Drop setting/clearing RFXE bit in HID1
  EDAC, altera: Rename MC trigger to common name
  EDAC, altera: Rename device trigger to common name
  ...
parents 58e4411b a29d64a4
......@@ -3523,6 +3523,10 @@ S: 145 Howard St.
S: Northborough, MA 01532
S: USA
N: Doug Thompson
E: dougthompson@xmission.com
D: EDAC
N: Tommy Thorn
E: Tommy.Thorn@irisa.fr
W: http://www.irisa.fr/prive/thorn/index.html
......@@ -3659,6 +3663,10 @@ S: Obere Heerbergstrasse 17
S: 97078 Wuerzburg
S: Germany
N: Jason Uhlenkott
E: juhlenko@akamai.com
D: I3000 EDAC driver
N: Greg Ungerer
E: gerg@snapgear.com
D: uClinux kernel hacker
......
......@@ -90,6 +90,47 @@ Required Properties:
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
NAND FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-nand-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent NAND node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
DMA FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-dma-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent DMA node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
USB FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-usb-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent USB node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
QSPI FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-qspi-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent QSPI node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
SDMMC FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-sdmmc-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent SD/MMC node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order for port A, and then single bit error interrupt,
then double bit error interrupt in this order for port B.
Example:
eccmgr: eccmgr@ffd06000 {
......@@ -132,4 +173,61 @@ Example:
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
<37 IRQ_TYPE_LEVEL_HIGH>;
};
nand-buf-ecc@ff8c2000 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2000 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
<43 IRQ_TYPE_LEVEL_HIGH>;
};
nand-rd-ecc@ff8c2400 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2400 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
<45 IRQ_TYPE_LEVEL_HIGH>;
};
nand-wr-ecc@ff8c2800 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2800 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
<44 IRQ_TYPE_LEVEL_HIGH>;
};
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;
altr,ecc-parent = <&pdma>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<42 IRQ_TYPE_LEVEL_HIGH>;
usb0-ecc@ff8c8800 {
compatible = "altr,socfpga-usb-ecc";
reg = <0xff8c8800 0x400>;
altr,ecc-parent = <&usb0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
<34 IRQ_TYPE_LEVEL_HIGH>;
};
qspi-ecc@ff8c8400 {
compatible = "altr,socfpga-qspi-ecc";
reg = <0xff8c8400 0x400>;
altr,ecc-parent = <&qspi>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<46 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmc-ecc@ff8c2c00 {
compatible = "altr,socfpga-sdmmc-ecc";
reg = <0xff8c2c00 0x400>;
altr,ecc-parent = <&mmc>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<16 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>;
};
};
......@@ -7,6 +7,8 @@ Properties:
"fsl,qoriq-memory-controller".
- reg : Address and size of DDR controller registers
- interrupts : Error interrupt of DDR controller
- little-endian : Specifies little-endian access to registers
If omitted, big-endian will be used.
Example 1:
......
......@@ -4410,7 +4410,6 @@ F: Documentation/filesystems/ecryptfs.txt
F: fs/ecryptfs/
EDAC-CORE
M: Doug Thompson <dougthompson@xmission.com>
M: Borislav Petkov <bp@alien8.de>
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
M: Mauro Carvalho Chehab <mchehab@kernel.org>
......@@ -4423,14 +4422,12 @@ F: drivers/edac/
F: include/linux/edac.h
EDAC-AMD64
M: Doug Thompson <dougthompson@xmission.com>
M: Borislav Petkov <bp@alien8.de>
L: linux-edac@vger.kernel.org
S: Maintained
F: drivers/edac/amd64_edac*
EDAC-CALXEDA
M: Doug Thompson <dougthompson@xmission.com>
M: Robert Richter <rric@kernel.org>
L: linux-edac@vger.kernel.org
S: Maintained
......@@ -4446,17 +4443,21 @@ F: drivers/edac/octeon_edac*
EDAC-E752X
M: Mark Gross <mark.gross@intel.com>
M: Doug Thompson <dougthompson@xmission.com>
L: linux-edac@vger.kernel.org
S: Maintained
F: drivers/edac/e752x_edac.c
EDAC-E7XXX
M: Doug Thompson <dougthompson@xmission.com>
L: linux-edac@vger.kernel.org
S: Maintained
F: drivers/edac/e7xxx_edac.c
EDAC-FSL_DDR
M: York Sun <york.sun@nxp.com>
L: linux-edac@vger.kernel.org
S: Maintained
F: drivers/edac/fsl_ddr_edac.*
EDAC-GHES
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
M: Mauro Carvalho Chehab <mchehab@kernel.org>
......@@ -4471,13 +4472,11 @@ S: Maintained
F: drivers/edac/i82443bxgx_edac.c
EDAC-I3000
M: Jason Uhlenkott <juhlenko@akamai.com>
L: linux-edac@vger.kernel.org
S: Maintained
S: Orphan
F: drivers/edac/i3000_edac.c
EDAC-I5000
M: Doug Thompson <dougthompson@xmission.com>
L: linux-edac@vger.kernel.org
S: Maintained
F: drivers/edac/i5000_edac.c
......
......@@ -639,6 +639,22 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
<37 IRQ_TYPE_LEVEL_HIGH>;
};
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;
altr,ecc-parent = <&pdma>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<42 IRQ_TYPE_LEVEL_HIGH>;
};
usb0-ecc@ff8c8800 {
compatible = "altr,socfpga-usb-ecc";
reg = <0xff8c8800 0x400>;
altr,ecc-parent = <&usb0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
<34 IRQ_TYPE_LEVEL_HIGH>;
};
};
rst: rstmgr@ffd05000 {
......
......@@ -25,3 +25,15 @@
broken-cd;
bus-width = <4>;
};
&eccmgr {
sdmmca-ecc@ff8c2c00 {
compatible = "altr,socfpga-sdmmc-ecc";
reg = <0xff8c2c00 0x400>;
altr,ecc-parent = <&mmc>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<16 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>;
};
};
......@@ -55,6 +55,7 @@ config ARCH_EXYNOS
config ARCH_LAYERSCAPE
bool "ARMv8 based Freescale Layerscape SoC family"
select EDAC_SUPPORT
help
This enables support for the Freescale Layerscape SoC family.
......
......@@ -266,6 +266,13 @@ config EDAC_MPC85XX
Support for error detection and correction on the Freescale
MPC8349, MPC8560, MPC8540, MPC8548, T4240
config EDAC_LAYERSCAPE
tristate "Freescale Layerscape DDR"
depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE
help
Support for error detection and correction on Freescale memory
controllers on Layerscape SoCs.
config EDAC_MV64X60
tristate "Marvell MV64x60"
depends on EDAC_MM_EDAC && MV64X60
......@@ -406,6 +413,41 @@ config EDAC_ALTERA_ETHERNET
Support for error detection and correction on the
Altera Ethernet FIFO Memory for Altera SoCs.
config EDAC_ALTERA_NAND
bool "Altera NAND FIFO ECC"
depends on EDAC_ALTERA=y && MTD_NAND_DENALI
help
Support for error detection and correction on the
Altera NAND FIFO Memory for Altera SoCs.
config EDAC_ALTERA_DMA
bool "Altera DMA FIFO ECC"
depends on EDAC_ALTERA=y && PL330_DMA=y
help
Support for error detection and correction on the
Altera DMA FIFO Memory for Altera SoCs.
config EDAC_ALTERA_USB
bool "Altera USB FIFO ECC"
depends on EDAC_ALTERA=y && USB_DWC2
help
Support for error detection and correction on the
Altera USB FIFO Memory for Altera SoCs.
config EDAC_ALTERA_QSPI
bool "Altera QSPI FIFO ECC"
depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
help
Support for error detection and correction on the
Altera QSPI FIFO Memory for Altera SoCs.
config EDAC_ALTERA_SDMMC
bool "Altera SDMMC FIFO ECC"
depends on EDAC_ALTERA=y && MMC_DW
help
Support for error detection and correction on the
Altera SDMMC FIFO Memory for Altera SoCs.
config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
depends on EDAC_MM_EDAC && ARCH_ZYNQ
......
......@@ -51,7 +51,13 @@ amd64_edac_mod-$(CONFIG_EDAC_AMD64_ERROR_INJECTION) += amd64_edac_inj.o
obj-$(CONFIG_EDAC_AMD64) += amd64_edac_mod.o
obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac.o
mpc85xx_edac_mod-y := fsl_ddr_edac.o mpc85xx_edac.o
obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o
layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o
obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o
obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o
obj-$(CONFIG_EDAC_CELL) += cell_edac.o
obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
......
This diff is collapsed.
......@@ -250,6 +250,8 @@ struct altr_sdram_mc_data {
#define ALTR_A10_ECC_INTTEST_OFST 0x24
#define ALTR_A10_ECC_TSERRA BIT(0)
#define ALTR_A10_ECC_TDERRA BIT(8)
#define ALTR_A10_ECC_TSERRB BIT(16)
#define ALTR_A10_ECC_TDERRB BIT(24)
/* ECC Manager Defines */
#define A10_SYSMGR_ECC_INTMASK_SET_OFST 0x94
......@@ -288,6 +290,9 @@ struct altr_sdram_mc_data {
/* Arria 10 Ethernet ECC Management Group Defines */
#define ALTR_A10_COMMON_ECC_EN_CTL BIT(0)
/* Arria 10 SDMMC ECC Management Group Defines */
#define ALTR_A10_SDMMC_IRQ_MASK (BIT(16) | BIT(15))
/* A10 ECC Controller memory initialization timeout */
#define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000
......@@ -298,7 +303,6 @@ struct edac_device_prv_data {
int ce_clear_mask;
int ue_clear_mask;
int irq_status_mask;
char dbgfs_name[20];
void * (*alloc_mem)(size_t size, void **other);
void (*free_mem)(void *p, size_t size, void *other);
int ecc_enable_mask;
......
......@@ -1425,11 +1425,17 @@ static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
if (intlv_addr & 0x2) {
u8 shift = intlv_addr & 0x1 ? 9 : 6;
u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2;
u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) & 1;
return ((sys_addr >> shift) & 1) ^ temp;
}
if (intlv_addr & 0x4) {
u8 shift = intlv_addr & 0x1 ? 9 : 8;
return (sys_addr >> shift) & 1;
}
return (sys_addr >> (12 + hweight8(intlv_en))) & 1;
}
......@@ -1726,8 +1732,11 @@ static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
if (!(num_dcts_intlv % 2 == 0) || (num_dcts_intlv > 4))
return -EINVAL;
channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en,
num_dcts_intlv, dct_sel);
if (pvt->model >= 0x60)
channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en);
else
channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en,
num_dcts_intlv, dct_sel);
/* Verify we stay within the MAX number of channels allowed */
if (channel > 3)
......@@ -2961,6 +2970,15 @@ static void setup_pci_device(void)
}
}
static const struct x86_cpu_id amd64_cpuids[] = {
{ X86_VENDOR_AMD, 0xF, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
{ X86_VENDOR_AMD, 0x10, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
{ X86_VENDOR_AMD, 0x15, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
{ X86_VENDOR_AMD, 0x16, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
{ }
};
MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids);
static int __init amd64_edac_init(void)
{
int err = -ENODEV;
......
This diff is collapsed.
/*
* Freescale Memory Controller kernel module
*
* Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
* ARM-based Layerscape SoCs including LS2xxx. Originally split
* out from mpc85xx_edac EDAC driver.
*
* Author: Dave Jiang <djiang@mvista.com>
*
* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*
*/
#ifndef _FSL_DDR_EDAC_H_
#define _FSL_DDR_EDAC_H_
#define fsl_mc_printk(mci, level, fmt, arg...) \
edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg)
/*
* DRAM error defines
*/
/* DDR_SDRAM_CFG */
#define FSL_MC_DDR_SDRAM_CFG 0x0110
#define FSL_MC_CS_BNDS_0 0x0000
#define FSL_MC_CS_BNDS_OFS 0x0008
#define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
#define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
#define FSL_MC_ECC_ERR_INJECT 0x0e08
#define FSL_MC_CAPTURE_DATA_HI 0x0e20
#define FSL_MC_CAPTURE_DATA_LO 0x0e24
#define FSL_MC_CAPTURE_ECC 0x0e28
#define FSL_MC_ERR_DETECT 0x0e40
#define FSL_MC_ERR_DISABLE 0x0e44
#define FSL_MC_ERR_INT_EN 0x0e48
#define FSL_MC_CAPTURE_ATRIBUTES 0x0e4c
#define FSL_MC_CAPTURE_ADDRESS 0x0e50
#define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54
#define FSL_MC_ERR_SBE 0x0e58
#define DSC_MEM_EN 0x80000000
#define DSC_ECC_EN 0x20000000
#define DSC_RD_EN 0x10000000
#define DSC_DBW_MASK 0x00180000
#define DSC_DBW_32 0x00080000
#define DSC_DBW_64 0x00000000
#define DSC_SDTYPE_MASK 0x07000000
#define DSC_X32_EN 0x00000020
/* Err_Int_En */
#define DDR_EIE_MSEE 0x1 /* memory select */
#define DDR_EIE_SBEE 0x4 /* single-bit ECC error */
#define DDR_EIE_MBEE 0x8 /* multi-bit ECC error */
/* Err_Detect */
#define DDR_EDE_MSE 0x1 /* memory select */
#define DDR_EDE_SBE 0x4 /* single-bit ECC error */
#define DDR_EDE_MBE 0x8 /* multi-bit ECC error */
#define DDR_EDE_MME 0x80000000 /* multiple memory errors */
/* Err_Disable */
#define DDR_EDI_MSED 0x1 /* memory select disable */
#define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
#define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
struct fsl_mc_pdata {
char *name;
int edac_idx;
void __iomem *mc_vbase;
int irq;
};
int fsl_mc_err_probe(struct platform_device *op);
int fsl_mc_err_remove(struct platform_device *op);
#endif
/*
* Freescale Memory Controller kernel module
*
* Author: York Sun <york.sun@nxp.com>
*
* Copyright 2016 NXP Semiconductor
*
* Derived from mpc85xx_edac.c
* Author: Dave Jiang <djiang@mvista.com>
*
* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include "edac_core.h"
#include "fsl_ddr_edac.h"
static const struct of_device_id fsl_ddr_mc_err_of_match[] = {
{ .compatible = "fsl,qoriq-memory-controller", },
{},
};
MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);
static struct platform_driver fsl_ddr_mc_err_driver = {
.probe = fsl_mc_err_probe,
.remove = fsl_mc_err_remove,
.driver = {
.name = "fsl_ddr_mc_err",
.of_match_table = fsl_ddr_mc_err_of_match,
},
};
static int __init fsl_ddr_mc_init(void)
{
int res;
/* make sure error reporting method is sane */
switch (edac_op_state) {
case EDAC_OPSTATE_POLL:
case EDAC_OPSTATE_INT:
break;
default:
edac_op_state = EDAC_OPSTATE_INT;
break;
}
res = platform_driver_register(&fsl_ddr_mc_err_driver);
if (res) {
pr_err("MC fails to register\n");
return res;
}
return 0;
}
module_init(fsl_ddr_mc_init);
static void __exit fsl_ddr_mc_exit(void)
{
platform_driver_unregister(&fsl_ddr_mc_err_driver);
}
module_exit(fsl_ddr_mc_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("NXP Semiconductor");
module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state,
"EDAC Error Reporting state: 0=Poll, 2=Interrupt");
This diff is collapsed.
......@@ -17,65 +17,6 @@
#define mpc85xx_printk(level, fmt, arg...) \
edac_printk(level, "MPC85xx", fmt, ##arg)
#define mpc85xx_mc_printk(mci, level, fmt, arg...) \
edac_mc_chipset_printk(mci, level, "MPC85xx", fmt, ##arg)
/*
* DRAM error defines
*/
/* DDR_SDRAM_CFG */
#define MPC85XX_MC_DDR_SDRAM_CFG 0x0110
#define MPC85XX_MC_CS_BNDS_0 0x0000
#define MPC85XX_MC_CS_BNDS_1 0x0008
#define MPC85XX_MC_CS_BNDS_2 0x0010
#define MPC85XX_MC_CS_BNDS_3 0x0018
#define MPC85XX_MC_CS_BNDS_OFS 0x0008
#define MPC85XX_MC_DATA_ERR_INJECT_HI 0x0e00
#define MPC85XX_MC_DATA_ERR_INJECT_LO 0x0e04
#define MPC85XX_MC_ECC_ERR_INJECT 0x0e08
#define MPC85XX_MC_CAPTURE_DATA_HI 0x0e20
#define MPC85XX_MC_CAPTURE_DATA_LO 0x0e24
#define MPC85XX_MC_CAPTURE_ECC 0x0e28
#define MPC85XX_MC_ERR_DETECT 0x0e40
#define MPC85XX_MC_ERR_DISABLE 0x0e44
#define MPC85XX_MC_ERR_INT_EN 0x0e48
#define MPC85XX_MC_CAPTURE_ATRIBUTES 0x0e4c
#define MPC85XX_MC_CAPTURE_ADDRESS 0x0e50
#define MPC85XX_MC_CAPTURE_EXT_ADDRESS 0x0e54
#define MPC85XX_MC_ERR_SBE 0x0e58
#define DSC_MEM_EN 0x80000000
#define DSC_ECC_EN 0x20000000
#define DSC_RD_EN 0x10000000
#define DSC_DBW_MASK 0x00180000
#define DSC_DBW_32 0x00080000
#define DSC_DBW_64 0x00000000
#define DSC_SDTYPE_MASK 0x07000000
#define DSC_SDTYPE_DDR 0x02000000
#define DSC_SDTYPE_DDR2 0x03000000
#define DSC_SDTYPE_DDR3 0x07000000
#define DSC_X32_EN 0x00000020
/* Err_Int_En */
#define DDR_EIE_MSEE 0x1 /* memory select */
#define DDR_EIE_SBEE 0x4 /* single-bit ECC error */
#define DDR_EIE_MBEE 0x8 /* multi-bit ECC error */
/* Err_Detect */
#define DDR_EDE_MSE 0x1 /* memory select */
#define DDR_EDE_SBE 0x4 /* single-bit ECC error */
#define DDR_EDE_MBE 0x8 /* multi-bit ECC error */
#define DDR_EDE_MME 0x80000000 /* multiple memory errors */
/* Err_Disable */
#define DDR_EDI_MSED 0x1 /* memory select disable */
#define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
#define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
/*
* L2 Err defines
*/
......@@ -149,13 +90,6 @@
#define MPC85XX_PCIE_ERR_CAP_R2 0x0030
#define MPC85XX_PCIE_ERR_CAP_R3 0x0034
struct mpc85xx_mc_pdata {
char *name;
int edac_idx;
void __iomem *mc_vbase;
int irq;
};
struct mpc85xx_l2_pdata {
char *name;
int edac_idx;
......
......@@ -118,7 +118,6 @@ static int mv64x60_pci_err_probe(struct platform_device *pdev)
pdata->pci_hose = pdev->id;
pdata->name = "mpc85xx_pci_err";
pdata->irq = NO_IRQ;
platform_set_drvdata(pdev, pci);
pci->dev = &pdev->dev;
pci->dev_name = dev_name(&pdev->dev);
......@@ -291,7 +290,6 @@ static int mv64x60_sram_err_probe(struct platform_device *pdev)
pdata = edac_dev->pvt_info;
pdata->name = "mv64x60_sram_err";
pdata->irq = NO_IRQ;
edac_dev->dev = &pdev->dev;
platform_set_drvdata(pdev, edac_dev);
edac_dev->dev_name = dev_name(&pdev->dev);
......@@ -459,7 +457,6 @@ static int mv64x60_cpu_err_probe(struct platform_device *pdev)
pdata = edac_dev->pvt_info;
pdata->name = "mv64x60_cpu_err";
pdata->irq = NO_IRQ;
edac_dev->dev = &pdev->dev;
platform_set_drvdata(pdev, edac_dev);
edac_dev->dev_name = dev_name(&pdev->dev);
......@@ -727,7 +724,6 @@ static int mv64x60_mc_err_probe(struct platform_device *pdev)
mci->pdev = &pdev->dev;
platform_set_drvdata(pdev, mci);
pdata->name = "mv64x60_mc_err";
pdata->irq = NO_IRQ;
mci->dev_name = dev_name(&pdev->dev);
pdata->edac_idx = edac_mc_idx++;
......
......@@ -1029,8 +1029,6 @@ static int ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
pdata = mci->pvt_info;
pdata->dcr_host = *dcr_host;
pdata->irqs.sec = NO_IRQ;
pdata->irqs.ded = NO_IRQ;
/* Initialize controller capabilities and configuration */
......@@ -1111,7 +1109,7 @@ static int ppc4xx_edac_register_irq(struct platform_device *op,
ded_irq = irq_of_parse_and_map(np, INTMAP_ECCDED_INDEX);
sec_irq = irq_of_parse_and_map(np, INTMAP_ECCSEC_INDEX);
if (ded_irq == NO_IRQ || sec_irq == NO_IRQ) {
if (!ded_irq || !sec_irq) {
ppc4xx_edac_mc_printk(KERN_ERR, mci,
"Unable to map interrupts.\n");
status = -ENODEV;
......
......@@ -2474,7 +2474,7 @@ static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
/* Check if everything were registered */
if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
!pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta)
!pvt->pci_ras || !pvt->pci_ta)
goto enodev;
if (saw_chan_mask != 0x0f)
......@@ -2563,8 +2563,7 @@ static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
/* Check if everything were registered */
if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
!pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras ||
!pvt->pci_ta)
!pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta)
goto enodev;
if (saw_chan_mask != 0x0f && /* -EN */
......
......@@ -27,7 +27,7 @@ EXPORT_SYMBOL_GPL(edac_stop_work);
int edac_workqueue_setup(void)
{
wq = create_singlethread_workqueue("edac-poller");
wq = alloc_ordered_workqueue("edac-poller", WQ_MEM_RECLAIM);
if (!wq)
return -ENODEV;
else
......
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