Commit 2474542f authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'for-3.7-rc1' of git://gitorious.org/linux-pwm/linux-pwm

Pull pwm changes from Thierry Reding:
 "All legacy PWM providers have now been moved to the PWM subsystem.
  The plan for 3.8 is to adapt all board files to provide a lookup table
  for PWM devices in order to get rid of the global namespace.
  Subsequently, users of the legacy pwm_request() and pwm_free()
  functions can be migrated to the new pwm_get() and pwm_put()
  functions.  Once this has been completed, the legacy API and the
  compatibility code in the core can be removed.

  In addition to the above, these changes also add support for
  configuring the polarity of a PWM signal (currently only supported on
  ECAP and EHRPWM) and include a much needed rework of the i.MX driver.
  Managed functions to obtain and release a PWM device (devm_pwm_get()
  and devm_pwm_put()) have been added and the pwm-backlight driver has
  been updated to use them.  If the PWM subsystem hasn't been enabled,
  dummy functions are provided that allow the subsystem to safely
  compile out.

  Some common checks on input parameters have been moved to the core and
  removed from the drivers.  Finally, a small fix corrects the
  description of the PWM specifier's second cell in the device tree
  representation."

* tag 'for-3.7-rc1' of git://gitorious.org/linux-pwm/linux-pwm: (23 commits)
  pwm: dt: Fix description of second PWM cell
  pwm: Check for negative duty-cycle and period
  pwm: Add Ingenic JZ4740 support
  MIPS: JZ4740: Export timer API
  pwm: Move PUV3 PWM driver to PWM framework
  unicore32: pwm: Use managed resource allocations
  unicore32: pwm: Remove unnecessary indirection
  unicore32: pwm: Use module_platform_driver()
  unicore32: pwm: Properly remap memory-mapped registers
  pwm-backlight: Use devm_pwm_get() instead of pwm_get()
  pwm: Move AB8500 PWM driver to PWM framework
  pwm: Fix compilation error when CONFIG_PWM is not defined
  pwm: i.MX: fix clock lookup
  pwm: i.MX: use per clock unconditionally
  pwm: i.MX: add devicetree support
  pwm: i.MX: Use module_platform_driver
  pwm: i.MX: add functions to enable/disable pwm.
  pwm: i.MX: remove unnecessary if in pwm_[en|dis]able
  pwm: i.MX: factor out SoC specific functions
  pwm: pwm-tiehrpwm: Add support for configuring polarity of PWM
  ...
parents c7a6ced9 85f8879c
Freescale i.MX PWM controller
Required properties:
- compatible: should be "fsl,<soc>-pwm"
- reg: physical base address and length of the controller's registers
- #pwm-cells: should be 2. The first cell specifies the per-chip index
of the PWM to use and the second cell is the period in nanoseconds.
- interrupts: The interrupt for the pwm controller
Example:
pwm1: pwm@53fb4000 {
#pwm-cells = <2>;
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
reg = <0x53fb4000 0x4000>;
interrupts = <61>;
};
......@@ -4,7 +4,7 @@ Required properties:
- compatible: should be "fsl,imx23-pwm"
- reg: physical base address and length of the controller's registers
- #pwm-cells: should be 2. The first cell specifies the per-chip index
of the PWM to use and the second cell is the duty cycle in nanoseconds.
of the PWM to use and the second cell is the period in nanoseconds.
- fsl,pwm-number: the number of PWM devices
Example:
......
......@@ -7,7 +7,7 @@ Required properties:
- reg: physical base address and length of the controller's registers
- #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
first cell specifies the per-chip index of the PWM to use and the second
cell is the duty cycle in nanoseconds.
cell is the period in nanoseconds.
Example:
......
......@@ -284,3 +284,7 @@ CLOCK
PINCTRL
devm_pinctrl_get()
devm_pinctrl_put()
PWM
devm_pwm_get()
devm_pwm_put()
......@@ -36,7 +36,8 @@ Legacy users can request a PWM device using pwm_request() and free it
after usage with pwm_free().
New users should use the pwm_get() function and pass to it the consumer
device or a consumer name. pwm_put() is used to free the PWM device.
device or a consumer name. pwm_put() is used to free the PWM device. Managed
variants of these functions, devm_pwm_get() and devm_pwm_put(), also exist.
After being requested a PWM has to be configured using:
......
......@@ -31,6 +31,7 @@ extern struct platform_device jz4740_pcm_device;
extern struct platform_device jz4740_codec_device;
extern struct platform_device jz4740_adc_device;
extern struct platform_device jz4740_wdt_device;
extern struct platform_device jz4740_pwm_device;
void jz4740_serial_device_register(void);
......
......@@ -16,7 +16,120 @@
#ifndef __ASM_MACH_JZ4740_TIMER
#define __ASM_MACH_JZ4740_TIMER
#define JZ_REG_TIMER_STOP 0x0C
#define JZ_REG_TIMER_STOP_SET 0x1C
#define JZ_REG_TIMER_STOP_CLEAR 0x2C
#define JZ_REG_TIMER_ENABLE 0x00
#define JZ_REG_TIMER_ENABLE_SET 0x04
#define JZ_REG_TIMER_ENABLE_CLEAR 0x08
#define JZ_REG_TIMER_FLAG 0x10
#define JZ_REG_TIMER_FLAG_SET 0x14
#define JZ_REG_TIMER_FLAG_CLEAR 0x18
#define JZ_REG_TIMER_MASK 0x20
#define JZ_REG_TIMER_MASK_SET 0x24
#define JZ_REG_TIMER_MASK_CLEAR 0x28
#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
#define JZ_TIMER_IRQ_FULL(x) BIT(x)
#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)
#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
extern void __iomem *jz4740_timer_base;
void __init jz4740_timer_init(void);
void jz4740_timer_enable_watchdog(void);
void jz4740_timer_disable_watchdog(void);
static inline void jz4740_timer_stop(unsigned int timer)
{
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
}
static inline void jz4740_timer_start(unsigned int timer)
{
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
}
static inline bool jz4740_timer_is_enabled(unsigned int timer)
{
return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
}
static inline void jz4740_timer_enable(unsigned int timer)
{
writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
}
static inline void jz4740_timer_disable(unsigned int timer)
{
writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
}
static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
{
writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
}
static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
{
writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
}
static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
{
writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
}
static inline uint16_t jz4740_timer_get_count(unsigned int timer)
{
return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
}
static inline void jz4740_timer_ack_full(unsigned int timer)
{
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
}
static inline void jz4740_timer_irq_full_enable(unsigned int timer)
{
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
}
static inline void jz4740_timer_irq_full_disable(unsigned int timer)
{
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
}
static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
{
writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
}
static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
{
return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
}
#endif
......@@ -7,6 +7,3 @@ config JZ4740_QI_LB60
bool "Qi Hardware Ben NanoNote"
endchoice
config HAVE_PWM
bool
......@@ -5,7 +5,7 @@
# Object file lists.
obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
gpio.o clock.o platform.o timer.o pwm.o serial.o
gpio.o clock.o platform.o timer.o serial.o
obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o
......
......@@ -437,6 +437,7 @@ static struct platform_device *jz_platform_devices[] __initdata = {
&jz4740_codec_device,
&jz4740_rtc_device,
&jz4740_adc_device,
&jz4740_pwm_device,
&qi_lb60_gpio_keys,
&qi_lb60_pwm_beeper,
&qi_lb60_charger_device,
......
......@@ -323,3 +323,9 @@ struct platform_device jz4740_wdt_device = {
.num_resources = ARRAY_SIZE(jz4740_wdt_resources),
.resource = jz4740_wdt_resources,
};
/* PWM */
struct platform_device jz4740_pwm_device = {
.name = "jz4740-pwm",
.id = -1,
};
/*
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
* JZ4740 platform PWM support
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/pwm.h>
#include <linux/gpio.h>
#include <asm/mach-jz4740/gpio.h>
#include "timer.h"
static struct clk *jz4740_pwm_clk;
DEFINE_MUTEX(jz4740_pwm_mutex);
struct pwm_device {
unsigned int id;
unsigned int gpio;
bool used;
};
static struct pwm_device jz4740_pwm_list[] = {
{ 2, JZ_GPIO_PWM2, false },
{ 3, JZ_GPIO_PWM3, false },
{ 4, JZ_GPIO_PWM4, false },
{ 5, JZ_GPIO_PWM5, false },
{ 6, JZ_GPIO_PWM6, false },
{ 7, JZ_GPIO_PWM7, false },
};
struct pwm_device *pwm_request(int id, const char *label)
{
int ret = 0;
struct pwm_device *pwm;
if (id < 2 || id > 7 || !jz4740_pwm_clk)
return ERR_PTR(-ENODEV);
mutex_lock(&jz4740_pwm_mutex);
pwm = &jz4740_pwm_list[id - 2];
if (pwm->used)
ret = -EBUSY;
else
pwm->used = true;
mutex_unlock(&jz4740_pwm_mutex);
if (ret)
return ERR_PTR(ret);
ret = gpio_request(pwm->gpio, label);
if (ret) {
printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret);
pwm->used = false;
return ERR_PTR(ret);
}
jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM);
jz4740_timer_start(id);
return pwm;
}
void pwm_free(struct pwm_device *pwm)
{
pwm_disable(pwm);
jz4740_timer_set_ctrl(pwm->id, 0);
jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE);
gpio_free(pwm->gpio);
jz4740_timer_stop(pwm->id);
pwm->used = false;
}
int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
{
unsigned long long tmp;
unsigned long period, duty;
unsigned int prescaler = 0;
unsigned int id = pwm->id;
uint16_t ctrl;
bool is_enabled;
if (duty_ns < 0 || duty_ns > period_ns)
return -EINVAL;
tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns;
do_div(tmp, 1000000000);
period = tmp;
while (period > 0xffff && prescaler < 6) {
period >>= 2;
++prescaler;
}
if (prescaler == 6)
return -EINVAL;
tmp = (unsigned long long)period * duty_ns;
do_div(tmp, period_ns);
duty = period - tmp;
if (duty >= period)
duty = period - 1;
is_enabled = jz4740_timer_is_enabled(id);
if (is_enabled)
pwm_disable(pwm);
jz4740_timer_set_count(id, 0);
jz4740_timer_set_duty(id, duty);
jz4740_timer_set_period(id, period);
ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT |
JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
jz4740_timer_set_ctrl(id, ctrl);
if (is_enabled)
pwm_enable(pwm);
return 0;
}
int pwm_enable(struct pwm_device *pwm)
{
uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
ctrl |= JZ_TIMER_CTRL_PWM_ENABLE;
jz4740_timer_set_ctrl(pwm->id, ctrl);
jz4740_timer_enable(pwm->id);
return 0;
}
void pwm_disable(struct pwm_device *pwm)
{
uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE;
jz4740_timer_disable(pwm->id);
jz4740_timer_set_ctrl(pwm->id, ctrl);
}
static int __init jz4740_pwm_init(void)
{
int ret = 0;
jz4740_pwm_clk = clk_get(NULL, "ext");
if (IS_ERR(jz4740_pwm_clk)) {
ret = PTR_ERR(jz4740_pwm_clk);
jz4740_pwm_clk = NULL;
}
return ret;
}
subsys_initcall(jz4740_pwm_init);
......@@ -20,10 +20,10 @@
#include <linux/clockchips.h>
#include <asm/mach-jz4740/irq.h>
#include <asm/mach-jz4740/timer.h>
#include <asm/time.h>
#include "clock.h"
#include "timer.h"
#define TIMER_CLOCKEVENT 0
#define TIMER_CLOCKSOURCE 1
......
......@@ -17,11 +17,11 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include "timer.h"
#include <asm/mach-jz4740/base.h>
#include <asm/mach-jz4740/timer.h>
void __iomem *jz4740_timer_base;
EXPORT_SYMBOL_GPL(jz4740_timer_base);
void jz4740_timer_enable_watchdog(void)
{
......
/*
* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
* JZ4740 platform timer support
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __MIPS_JZ4740_TIMER_H__
#define __MIPS_JZ4740_TIMER_H__
#include <linux/module.h>
#include <linux/io.h>
#define JZ_REG_TIMER_STOP 0x0C
#define JZ_REG_TIMER_STOP_SET 0x1C
#define JZ_REG_TIMER_STOP_CLEAR 0x2C
#define JZ_REG_TIMER_ENABLE 0x00
#define JZ_REG_TIMER_ENABLE_SET 0x04
#define JZ_REG_TIMER_ENABLE_CLEAR 0x08
#define JZ_REG_TIMER_FLAG 0x10
#define JZ_REG_TIMER_FLAG_SET 0x14
#define JZ_REG_TIMER_FLAG_CLEAR 0x18
#define JZ_REG_TIMER_MASK 0x20
#define JZ_REG_TIMER_MASK_SET 0x24
#define JZ_REG_TIMER_MASK_CLEAR 0x28
#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
#define JZ_TIMER_IRQ_FULL(x) BIT(x)
#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)
#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
extern void __iomem *jz4740_timer_base;
void __init jz4740_timer_init(void);
static inline void jz4740_timer_stop(unsigned int timer)
{
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
}
static inline void jz4740_timer_start(unsigned int timer)
{
writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
}
static inline bool jz4740_timer_is_enabled(unsigned int timer)
{
return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
}
static inline void jz4740_timer_enable(unsigned int timer)
{
writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
}
static inline void jz4740_timer_disable(unsigned int timer)
{
writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
}
static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
{
writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
}
static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
{
writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
}
static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
{
writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
}
static inline uint16_t jz4740_timer_get_count(unsigned int timer)
{
return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
}
static inline void jz4740_timer_ack_full(unsigned int timer)
{
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
}
static inline void jz4740_timer_irq_full_enable(unsigned int timer)
{
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
}
static inline void jz4740_timer_irq_full_disable(unsigned int timer)
{
writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
}
static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
{
writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
}
static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
{
return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
}
#endif
......@@ -21,9 +21,6 @@ config UNICORE32
designs licensed by PKUnity Ltd.
Please see web page at <http://www.pkunity.com/>.
config HAVE_PWM
bool
config GENERIC_GPIO
def_bool y
......@@ -106,7 +103,8 @@ config PUV3_DB0913
config PUV3_NB0916
bool "NetBook board (0916)"
select HAVE_PWM
select PWM
select PWM_PUV3
config PUV3_SMW0919
bool "Security Mini-Workstation board (0919)"
......@@ -220,12 +218,6 @@ config PUV3_GPIO
select GPIO_SYSFS if EXPERIMENTAL
default y
config PUV3_PWM
tristate
default BACKLIGHT_PWM
help
Enable support for NB0916 PWM controllers
if PUV3_NB0916
menu "PKUnity NetBook-0916 Features"
......
......@@ -33,18 +33,16 @@
* Interrupt Enable Reg OST_OIER
*/
#define OST_OIER (PKUNITY_OST_BASE + 0x001C)
/*
* PWM Pulse Width Control Reg OST_PWMPWCR
*/
#define OST_PWMPWCR (PKUNITY_OST_BASE + 0x0080)
/*
* PWM Duty Cycle Control Reg OST_PWMDCCR
*/
#define OST_PWMDCCR (PKUNITY_OST_BASE + 0x0084)
/*
* PWM Period Control Reg OST_PWMPCR
* PWM Registers: IO base address: PKUNITY_OST_BASE + 0x80
* PWCR: Pulse Width Control Reg
* DCCR: Duty Cycle Control Reg
* PCR: Period Control Reg
*/
#define OST_PWMPCR (PKUNITY_OST_BASE + 0x0088)
#define OST_PWM_PWCR (0x00)
#define OST_PWM_DCCR (0x04)
#define OST_PWM_PCR (0x08)
/*
* Match detected 0 OST_OSSR_M0
......
......@@ -16,7 +16,6 @@ obj-$(CONFIG_UNICORE_FPU_F64) += fpu-ucf64.o
obj-$(CONFIG_ARCH_PUV3) += clock.o irq.o time.o
obj-$(CONFIG_PUV3_GPIO) += gpio.o
obj-$(CONFIG_PUV3_PWM) += pwm.o
obj-$(CONFIG_PUV3_PM) += pm.o sleep.o
obj-$(CONFIG_HIBERNATION) += hibernate.o hibernate_asm.o
......
......@@ -60,16 +60,6 @@ config ATMEL_PWM
purposes including software controlled power-efficient backlights
on LCD displays, motor control, and waveform generation.
config AB8500_PWM
bool "AB8500 PWM support"
depends on AB8500_CORE && ARCH_U8500
select HAVE_PWM
depends on !PWM
help
This driver exports functions to enable/disble/config/free Pulse
Width Modulation in the Analog Baseband Chip AB8500.
It is used by led and backlight driver to control the intensity.
config ATMEL_TCLIB
bool "Atmel AT32/AT91 Timer/Counter Library"
depends on (AVR32 || ARCH_AT91)
......
......@@ -44,7 +44,6 @@ obj-$(CONFIG_VMWARE_BALLOON) += vmw_balloon.o
obj-$(CONFIG_ARM_CHARLCD) += arm-charlcd.o
obj-$(CONFIG_PCH_PHUB) += pch_phub.o
obj-y += ti-st/
obj-$(CONFIG_AB8500_PWM) += ab8500-pwm.o
obj-y += lis3lv02d/
obj-y += carma/
obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o
......
menuconfig PWM
bool "Pulse-Width Modulation (PWM) Support"
depends on !MACH_JZ4740 && !PUV3_PWM
help
Generic Pulse-Width Modulation (PWM) support.
......@@ -29,6 +28,15 @@ menuconfig PWM
if PWM
config PWM_AB8500
tristate "AB8500 PWM support"
depends on AB8500_CORE && ARCH_U8500
help
Generic PWM framework driver for Analog Baseband AB8500.
To compile this driver as a module, choose M here: the module
will be called pwm-ab8500.
config PWM_BFIN
tristate "Blackfin PWM support"
depends on BFIN_GPTIMERS
......@@ -47,6 +55,16 @@ config PWM_IMX
To compile this driver as a module, choose M here: the module
will be called pwm-imx.
config PWM_JZ4740
tristate "Ingenic JZ4740 PWM support"
depends on MACH_JZ4740
help
Generic PWM framework driver for Ingenic JZ4740 based
machines.
To compile this driver as a module, choose M here: the module
will be called pwm-jz4740.
config PWM_LPC32XX
tristate "LPC32XX PWM support"
depends on ARCH_LPC32XX
......@@ -67,6 +85,15 @@ config PWM_MXS
To compile this driver as a module, choose M here: the module
will be called pwm-mxs.
config PWM_PUV3
tristate "PKUnity NetBook-0916 PWM support"
depends on ARCH_PUV3
help
Generic PWM framework driver for PKUnity NetBook-0916.
To compile this driver as a module, choose M here: the module
will be called pwm-puv3.
config PWM_PXA
tristate "PXA PWM support"
depends on ARCH_PXA
......
obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
obj-$(CONFIG_PWM_IMX) += pwm-imx.o
obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o
obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o
obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
......
......@@ -371,13 +371,35 @@ EXPORT_SYMBOL_GPL(pwm_free);
*/