Commit 53ec8748 authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo

ARM: dts: imx51: Improve SSI clocks description

SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock
for generating bit clock when SSI operates in master mode.

Add the extra 'baud' clock so that we can have SSI functional in master mode.
Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent 685570ab
......@@ -214,7 +214,9 @@
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x70014000 0x4000>;
interrupts = <30>;
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
<&clks IMX5_CLK_SSI2_ROOT_GATE>;
clock-names = "ipg", "baud";
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
dma-names = "rx", "tx";
......@@ -504,7 +506,9 @@
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fcc000 0x4000>;
interrupts = <29>;
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
<&clks IMX5_CLK_SSI1_ROOT_GATE>;
clock-names = "ipg", "baud";
dmas = <&sdma 28 0 0>,
<&sdma 29 0 0>;
dma-names = "rx", "tx";
......@@ -560,7 +564,9 @@
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fe8000 0x4000>;
interrupts = <96>;
clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
<&clks IMX5_CLK_SSI3_ROOT_GATE>;
clock-names = "ipg", "baud";
dmas = <&sdma 46 0 0>,
<&sdma 47 0 0>;
dma-names = "rx", "tx";
......
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