Commit 581dbc8b authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'pinctrl-v4.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control patches for the v4.5 series.

  Notably I have a patch to driver core from Stephen Boyd in the pull
  request, this has been ACKed by Greg so it should be OK.  The internal
  API needed some tweaking to allow modular Qualcomm pin controllers.

  There is a bit of development history in here but it should all add up
  nicely and has boiled in linux-next.  For example I merged in v4.4-rc5
  to get rid of some nasty merge conflicts.

  Summary:

   - New drivers:
      - PXA2xx pin controller support
      - Broadcom NSP pin controller support

   - New subdrivers:
      - Samsung EXYNOS5410 support
      - Qualcomm MSM8996 support
      - Qualcomm PM8994 support
      - Qualcomm PM8994 MPP support
      - Allwinner sunxi H3 support
      - Allwinner sunxi A80 support
      - Rockchip RK3228 support

   - Rename the Cygnus pinctrl driver to "iproc" as it is more generic
     than was originally thought.

   - A bunch of Lantiq/Xway updates especially from the OpenWRT people.

   - Several refactorings for the Super-H SH PFC pin controllers.
     Adding SCIF_CLK support.

   - Several fixes to the Atlas 7 driver.

   - Various fixes all over the place"

* tag 'pinctrl-v4.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (91 commits)
  pinctrl: mediatek: Modify pinctrl bindings for mt2701
  Revert "pinctrl: qcom: make PMIC drivers bool"
  pinctrl: qcom: Use platform_irq_count() instead of of_irq_count()
  driver-core: platform: Add platform_irq_count()
  pinctrl: lantiq: 2 pins have the wrong mux list
  pinctrl: qcom: make PMIC drivers bool
  pinctrl: nsp-gpio: forever loop in nsp_gpio_get_strength()
  pinctrl: mediatek: convert to arch_initcall
  pinctrl: bcm2835: Fix memory leak in error path
  pinctrl: mediatek: add missing of_node_put
  pinctrl: rockchip: add missing of_node_put
  pinctrl: sh-pfc: add missing of_node_put
  pinctrl: sirf: add missing of_node_put
  pinctrl-tegra: add missing of_node_put
  pinctrl: sunxi: Add A80 special pin controller
  pinctrl: bcm/cygnys/iproc: fixup rebase issue
  pinctrl: fixup problematic flag
  MAINTAINERS: Add co-maintainer for Renesas Pin Controllers
  pinctrl: sh-pfc: r8a7791: add EtherAVB pin groups
  pinctrl: sh-pfc: r8a7795: Add SATA support
  ...
parents fb591fbd 14da0a91
......@@ -17,7 +17,10 @@ Required properties:
"allwinner,sun8i-a23-pinctrl"
"allwinner,sun8i-a23-r-pinctrl"
"allwinner,sun8i-a33-pinctrl"
"allwinner,sun9i-a80-pinctrl"
"allwinner,sun9i-a80-r-pinctrl"
"allwinner,sun8i-a83t-pinctrl"
"allwinner,sun8i-h3-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.
......
Broadcom Cygnus GPIO/PINCONF Controller
Broadcom iProc GPIO/PINCONF Controller
Required properties:
......@@ -7,9 +7,12 @@ Required properties:
"brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio"
- reg:
Define the base and range of the I/O address space that contains the Cygnus
Define the base and range of the I/O address space that contains SoC
GPIO/PINCONF controller registers
- ngpios:
Total number of in-use slots in GPIO controller
- #gpio-cells:
Must be two. The first cell is the GPIO pin number (within the
controller's pin space) and the second cell is used for the following:
......@@ -57,6 +60,7 @@ Example:
compatible = "brcm,cygnus-ccm-gpio";
reg = <0x1800a000 0x50>,
<0x0301d164 0x20>;
ngpios = <24>;
#gpio-cells = <2>;
gpio-controller;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
......@@ -78,6 +82,7 @@ Example:
gpio_asiu: gpio@180a5000 {
compatible = "brcm,cygnus-asiu-gpio";
reg = <0x180a5000 0x668>;
ngpios = <146>;
#gpio-cells = <2>;
gpio-controller;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
......
Broadcom Northstar plus (NSP) GPIO/PINCONF Controller
Required properties:
- compatible:
Must be "brcm,nsp-gpio-a"
- reg:
Should contain the register physical address and length for each of
GPIO base, IO control registers
- #gpio-cells:
Must be two. The first cell is the GPIO pin number (within the
controller's pin space) and the second cell is used for the following:
bit[0]: polarity (0 for active high and 1 for active low)
- gpio-controller:
Specifies that the node is a GPIO controller
- ngpios:
Number of gpios supported (58x25 supports 32 and 58x23 supports 24)
Optional properties:
- interrupts:
Interrupt ID
- interrupt-controller:
Specifies that the node is an interrupt controller
- gpio-ranges:
Specifies the mapping between gpio controller and pin-controllers pins.
This requires 4 fields in cells defined as -
1. Phandle of pin-controller.
2. GPIO base pin offset.
3 Pin-control base pin offset.
4. number of gpio pins which are linearly mapped from pin base.
Supported generic PINCONF properties in child nodes:
- pins:
The list of pins (within the controller's own pin space) that properties
in the node apply to. Pin names are "gpio-<pin>"
- bias-disable:
Disable pin bias
- bias-pull-up:
Enable internal pull up resistor
- bias-pull-down:
Enable internal pull down resistor
- drive-strength:
Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA)
Example:
gpioa: gpio@18000020 {
compatible = "brcm,nsp-gpio-a";
reg = <0x18000020 0x100>,
<0x1803f1c4 0x1c>;
#gpio-cells = <2>;
gpio-controller;
ngpios = <32>;
gpio-ranges = <&pinctrl 0 0 31>;
interrupt-controller;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
/* Hog a few default settings */
pinctrl-names = "default";
pinctrl-0 = <&led>;
led: led {
pins = "gpio-1";
bias-pull-up;
};
pwr: pwr {
gpio-hog;
gpios = <3 1>;
output-high;
};
};
Lantiq XWAY pinmux controller
Required properties:
- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9"
- compatible: "lantiq,pinctrl-xway", (DEPRECATED: Use "lantiq,pinctrl-danube")
"lantiq,pinctrl-xr9", (DEPRECATED: Use "lantiq,xrx100-pinctrl" or
"lantiq,xrx200-pinctrl")
"lantiq,pinctrl-ase", (DEPRECATED: Use "lantiq,ase-pinctrl")
"lantiq,<chip>-pinctrl", where <chip> is:
"ase" (XWAY AMAZON Family)
"danube" (XWAY DANUBE Family)
"xrx100" (XWAY xRX100 Family)
"xrx200" (XWAY xRX200 Family)
"xrx300" (XWAY xRX300 Family)
- reg: Should contain the physical address and length of the gpio/pinmux
register range
......@@ -36,19 +45,87 @@ Required subnode-properties:
Valid values for group and function names:
XWAY: (DEPRECATED: Use DANUBE)
mux groups:
exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2,
spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2,
gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,
req3
additional mux groups (XR9 only):
mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4
functions:
spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu
XR9: ( DEPRECATED: Use xRX100/xRX200)
mux groups:
exin0, exin1, exin2, exin3, exin4, jtag, ebu a23, ebu a24, ebu a25,
ebu clk, ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy,
nand rd, spi, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6,
asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio,
gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2
functions:
spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio, gphy
AMAZON:
mux groups:
exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2,
spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0,
clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2
functions:
spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
DANUBE:
mux groups:
exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi,
gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3,
req1, req2, req3, dfe led0, dfe led1
functions:
spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio
spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
xRX100:
mux groups:
exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio,
dfe led0, dfe led1
functions:
spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
xRX200:
mux groups:
exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
spi_cs6, usif uart_rx, usif uart_tx, usif uart_rts, usif uart_cts,
usif uart_dtr, usif uart_dsr, usif uart_dcd, usif uart_ri, usif spi_di,
usif spi_do, usif spi_clk, usif spi_cs0, usif spi_cs1, usif spi_cs2,
stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1,
gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, dfe led0, dfe led1,
gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2
functions:
spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
xRX300:
mux groups:
exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
spi_clk, spi_cs1, spi_cs4, spi_cs6, usif uart_rx, usif uart_tx,
usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2,
mdio, dfe led0, dfe led1, ephy0 led0, ephy0 led1, ephy1 led0, ephy1 led1
functions:
spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy
Definition of pin configurations:
......@@ -62,15 +139,32 @@ Optional subnode-properties:
0: none, 1: down, 2: up.
- lantiq,open-drain: Boolean, enables open-drain on the defined pin.
Valid values for XWAY pin names:
Valid values for XWAY pin names: (DEPRECATED: Use DANUBE)
Pinconf pins can be referenced via the names io0-io31.
Valid values for XR9 pin names:
Valid values for XR9 pin names: (DEPRECATED: Use xrX100/xRX200)
Pinconf pins can be referenced via the names io0-io55.
Valid values for AMAZON pin names:
Pinconf pins can be referenced via the names io0-io31.
Valid values for DANUBE pin names:
Pinconf pins can be referenced via the names io0-io31.
Valid values for xRX100 pin names:
Pinconf pins can be referenced via the names io0-io55.
Valid values for xRX200 pin names:
Pinconf pins can be referenced via the names io0-io49.
Valid values for xRX300 pin names:
Pinconf pins can be referenced via the names io0-io1,io3-io6,io8-io11,
io13-io19,io23-io27,io34-io36,
io42-io43,io48-io61.
Example:
gpio: pinmux@E100B10 {
compatible = "lantiq,pinctrl-xway";
compatible = "lantiq,danube-pinctrl";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......
......@@ -4,10 +4,11 @@ The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
(a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
(b) "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
(c) "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
(d) "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
- gpio-controller : Marks the device node as a gpio controller.
......
Qualcomm MSM8996 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MSM8996 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,msm8996-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode.
Valid pins are:
gpio0-gpio149
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
sdc2_data sdc1_rclk
Supports bias and drive-strength
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
atest_usb20, atest_char0, dac_calib10, qdss_stm10,
qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
gpio
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@01010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x01010000 0x300000>;
interrupts = <0 208 0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
uart_console_active: uart_console_active {
mux {
pins = "gpio4", "gpio5";
function = "blsp_uart8";
};
config {
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-disable;
};
};
};
......@@ -14,6 +14,7 @@ PMIC's from Qualcomm.
"qcom,pm8917-gpio"
"qcom,pm8921-gpio"
"qcom,pm8941-gpio"
"qcom,pm8994-gpio"
"qcom,pma8084-gpio"
- reg:
......@@ -79,6 +80,7 @@ to specify in a pin configuration subnode:
gpio1-gpio38 for pm8917
gpio1-gpio44 for pm8921
gpio1-gpio36 for pm8941
gpio1-gpio22 for pm8994
gpio1-gpio22 for pma8084
- function:
......
......@@ -15,6 +15,7 @@ of PMIC's from Qualcomm.
"qcom,pm8917-mpp",
"qcom,pm8921-mpp",
"qcom,pm8941-mpp",
"qcom,pm8994-mpp",
"qcom,pma8084-mpp",
- reg:
......
......@@ -21,7 +21,8 @@ defined as gpio sub-nodes of the pinmux controller.
Required properties for iomux controller:
- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
"rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl"
"rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl"
"rockchip,rk3368-pinctrl"
- rockchip,grf: phandle referencing a syscon providing the
"general register files"
......
......@@ -17,6 +17,7 @@ Required Properties:
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
......
......@@ -8366,6 +8366,7 @@ F: drivers/pinctrl/intel/
PIN CONTROLLER - RENESAS
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
M: Geert Uytterhoeven <geert+renesas@glider.be>
L: linux-sh@vger.kernel.org
S: Maintained
F: drivers/pinctrl/sh-pfc/
......@@ -8636,6 +8637,7 @@ S: Maintained
F: arch/arm/mach-pxa/
F: drivers/dma/pxa*
F: drivers/pcmcia/pxa2xx*
F: drivers/pinctrl/pxa/
F: drivers/spi/spi-pxa2xx*
F: drivers/usb/gadget/udc/pxa2*
F: include/sound/pxa2xx-lib.h
......
......@@ -116,6 +116,26 @@ int platform_get_irq(struct platform_device *dev, unsigned int num)
}
EXPORT_SYMBOL_GPL(platform_get_irq);
/**
* platform_irq_count - Count the number of IRQs a platform device uses
* @dev: platform device
*
* Return: Number of IRQs a platform device uses or EPROBE_DEFER
*/
int platform_irq_count(struct platform_device *dev)
{
int ret, nr = 0;
while ((ret = platform_get_irq(dev, nr)) >= 0)
nr++;
if (ret == -EPROBE_DEFER)
return ret;
return nr;
}
EXPORT_SYMBOL_GPL(platform_irq_count);
/**
* platform_get_resource_byname - get a resource for a device by name
* @dev: platform device
......
......@@ -244,7 +244,7 @@ config PINCTRL_ZYNQ
select PINMUX
select GENERIC_PINCONF
help
This selectes the pinctrl driver for Xilinx Zynq.
This selects the pinctrl driver for Xilinx Zynq.
source "drivers/pinctrl/bcm/Kconfig"
source "drivers/pinctrl/berlin/Kconfig"
......@@ -252,6 +252,7 @@ source "drivers/pinctrl/freescale/Kconfig"
source "drivers/pinctrl/intel/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/nomadik/Kconfig"
source "drivers/pinctrl/pxa/Kconfig"
source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/sh-pfc/Kconfig"
......
......@@ -41,15 +41,16 @@ obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
obj-$(CONFIG_ARCH_BCM) += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
obj-$(CONFIG_PINCTRL_BERLIN) += berlin/
obj-y += freescale/
obj-$(CONFIG_X86) += intel/
obj-$(CONFIG_PLAT_ORION) += mvebu/
obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/
obj-y += nomadik/
obj-$(CONFIG_ARCH_PXA) += pxa/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_ARCH_VT8500) += vt8500/
......
......@@ -9,6 +9,7 @@ config PINCTRL_BCM281XX
select PINCONF
select GENERIC_PINCONF
select REGMAP_MMIO
default ARCH_BCM_MOBILE
help
Say Y here to support Broadcom BCM281xx pinctrl driver, which is used
for the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351,
......@@ -20,27 +21,41 @@ config PINCTRL_BCM2835
select PINMUX
select PINCONF
config PINCTRL_CYGNUS_GPIO
bool "Broadcom Cygnus GPIO (with PINCONF) driver"
depends on OF_GPIO && ARCH_BCM_CYGNUS
config PINCTRL_IPROC_GPIO
bool "Broadcom iProc GPIO (with PINCONF) driver"
depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
select GPIOLIB_IRQCHIP
select PINCONF
select GENERIC_PINCONF
default ARCH_BCM_CYGNUS
default ARCH_BCM_IPROC
help
Say yes here to enable the Broadcom Cygnus GPIO driver.
Say yes here to enable the Broadcom iProc GPIO driver.
The Broadcom iProc based SoCs- Cygnus, NS2, NSP and Stingray, use
same GPIO Controller IP hence this driver could be used for all.
The Broadcom Cygnus SoC has 3 GPIO controllers including the ASIU
GPIO controller (ASIU), the chipCommonG GPIO controller (CCM), and
the always-ON GPIO controller (CRMU/AON). All 3 GPIO controllers are
supported by this driver.
All 3 Cygnus GPIO controllers support basic PINCONF functions such
The Broadcom NSP has two GPIO controllers including the ChipcommonA
GPIO, the ChipcommonB GPIO. Later controller is supported by this
driver.
The Broadcom NS2 has two GPIO controller including the CRMU GPIO,
the ChipcommonG GPIO. Both controllers are supported by this driver.
The Broadcom Stingray GPIO controllers are supported by this driver.
All above SoCs GPIO controllers support basic PINCONF functions such
as bias pull up, pull down, and drive strength configurations, when
these pins are muxed to GPIO.
Pins from the ASIU GPIO can be individually muxed to GPIO function,
through interaction with the Cygnus IOMUX controller.
It provides the framework where pins from the individual GPIO can be
individually muxed to GPIO function, through interaction with the
SoCs IOMUX controller. This features could be used only on SoCs which
support individual pin muxing.
config PINCTRL_CYGNUS_MUX
bool "Broadcom Cygnus IOMUX driver"
......@@ -54,3 +69,20 @@ config PINCTRL_CYGNUS_MUX
The Broadcom Cygnus IOMUX driver supports group based IOMUX
configuration, with the exception that certain individual pins
can be overrided to GPIO function
config PINCTRL_NSP_GPIO
bool "Broadcom NSP GPIO (with PINCONF) driver"
depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST)
select GPIOLIB_IRQCHIP
select PINCONF
select GENERIC_PINCONF
default ARCH_BCM_NSP
help
Say yes here to enable the Broadcom NSP GPIO driver.
The Broadcom Northstar Plus SoC ChipcommonA GPIO controller is
supported by this driver.
The ChipcommonA GPIO controller support basic PINCONF functions such
as bias pull up, pull down, and drive strength configurations, when
these pins are muxed to GPIO.
......@@ -2,5 +2,6 @@
obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_CYGNUS_GPIO) += pinctrl-cygnus-gpio.o
obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o
obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o