Commit a585d2b7 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'platform-drivers-x86-v4.2-2' of...

Merge tag 'platform-drivers-x86-v4.2-2' of git://git.infradead.org/users/dvhart/linux-platform-drivers-x86

Pull late x86 platform driver updates from Darren Hart:
 "The following came in a bit later and I wanted them to bake in next a
  few more days before submitting, thus the second pull.

  A new intel_pmc_ipc driver, a symmetrical allocation and free fix in
  dell-laptop, a couple minor fixes, and some updated documentation in
  the dell-laptop comments.

  intel_pmc_ipc:
   - Add Intel Apollo Lake PMC IPC driver

  tc1100-wmi:
   - Delete an unnecessary check before the function call "kfree"

  dell-laptop:
   - Fix allocating & freeing SMI buffer page
   - Show info about WiGig and UWB in debugfs
   - Update information about wireless control"

* tag 'platform-drivers-x86-v4.2-2' of git://git.infradead.org/users/dvhart/linux-platform-drivers-x86:
  intel_pmc_ipc: Add Intel Apollo Lake PMC IPC driver
  tc1100-wmi: Delete an unnecessary check before the function call "kfree"
  dell-laptop: Fix allocating & freeing SMI buffer page
  dell-laptop: Show info about WiGig and UWB in debugfs
  dell-laptop: Update information about wireless control
parents 1dc51b82 0a8b8353
......@@ -5470,6 +5470,13 @@ F: include/linux/mei_cl_bus.h
F: drivers/misc/mei/*
F: Documentation/misc-devices/mei/*
INTEL PMC IPC DRIVER
M: Zha Qipeng<qipeng.zha@intel.com>
L: platform-driver-x86@vger.kernel.org
S: Maintained
F: drivers/platform/x86/intel_pmc_ipc.c
F: arch/x86/include/asm/intel_pmc_ipc.h
IOC3 ETHERNET DRIVER
M: Ralf Baechle <ralf@linux-mips.org>
L: linux-mips@linux-mips.org
......
#ifndef _ASM_X86_INTEL_PMC_IPC_H_
#define _ASM_X86_INTEL_PMC_IPC_H_
/* Commands */
#define PMC_IPC_PMIC_ACCESS 0xFF
#define PMC_IPC_PMIC_ACCESS_READ 0x0
#define PMC_IPC_PMIC_ACCESS_WRITE 0x1
#define PMC_IPC_USB_PWR_CTRL 0xF0
#define PMC_IPC_PMIC_BLACKLIST_SEL 0xEF
#define PMC_IPC_PHY_CONFIG 0xEE
#define PMC_IPC_NORTHPEAK_CTRL 0xED
#define PMC_IPC_PM_DEBUG 0xEC
#define PMC_IPC_PMC_TELEMTRY 0xEB
#define PMC_IPC_PMC_FW_MSG_CTRL 0xEA
/* IPC return code */
#define IPC_ERR_NONE 0
#define IPC_ERR_CMD_NOT_SUPPORTED 1
#define IPC_ERR_CMD_NOT_SERVICED 2
#define IPC_ERR_UNABLE_TO_SERVICE 3
#define IPC_ERR_CMD_INVALID 4
#define IPC_ERR_CMD_FAILED 5
#define IPC_ERR_EMSECURITY 6
#define IPC_ERR_UNSIGNEDKERNEL 7
#if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
/*
* intel_pmc_ipc_simple_command
* @cmd: command
* @sub: sub type
*/
int intel_pmc_ipc_simple_command(int cmd, int sub);
/*
* intel_pmc_ipc_raw_cmd
* @cmd: command
* @sub: sub type
* @in: input data
* @inlen: input length in bytes
* @out: output data
* @outlen: output length in dwords
* @sptr: data writing to SPTR register
* @dptr: data writing to DPTR register
*/
int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
u32 *out, u32 outlen, u32 dptr, u32 sptr);
/*
* intel_pmc_ipc_command
* @cmd: command
* @sub: sub type
* @in: input data
* @inlen: input length in bytes
* @out: output data
* @outlen: output length in dwords
*/
int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
u32 *out, u32 outlen);
#else
static inline int intel_pmc_ipc_simple_command(int cmd, int sub)
{
return -EINVAL;
}
static inline int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
u32 *out, u32 outlen, u32 dptr, u32 sptr)
{
return -EINVAL;
}
static inline int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
u32 *out, u32 outlen)
{
return -EINVAL;
}
#endif /*CONFIG_INTEL_PMC_IPC*/
#endif
......@@ -912,4 +912,11 @@ config PVPANIC
a paravirtualized device provided by QEMU; it lets a virtual machine
(guest) communicate panic events to the host.
config INTEL_PMC_IPC
tristate "Intel PMC IPC Driver"
---help---
This driver provides support for PMC control on some Intel platforms.
The PMC is an ARC processor which defines IPC commands for communication
with other entities in the CPU.
endif # X86_PLATFORM_DEVICES
......@@ -59,3 +59,4 @@ obj-$(CONFIG_INTEL_SMARTCONNECT) += intel-smartconnect.o
obj-$(CONFIG_PVPANIC) += pvpanic.o
obj-$(CONFIG_ALIENWARE_WMI) += alienware-wmi.o
obj-$(CONFIG_INTEL_PMC_IPC) += intel_pmc_ipc.o
......@@ -307,7 +307,6 @@ static const struct dmi_system_id dell_quirks[] __initconst = {
};
static struct calling_interface_buffer *buffer;
static struct page *bufferpage;
static DEFINE_MUTEX(buffer_mutex);
static int hwswitch_state;
......@@ -424,45 +423,125 @@ static inline int dell_smi_error(int value)
}
}
/* Derived from information in DellWirelessCtl.cpp:
Class 17, select 11 is radio control. It returns an array of 32-bit values.
Input byte 0 = 0: Wireless information
result[0]: return code
result[1]:
Bit 0: Hardware switch supported
Bit 1: Wifi locator supported
Bit 2: Wifi is supported
Bit 3: Bluetooth is supported
Bit 4: WWAN is supported
Bit 5: Wireless keyboard supported
Bits 6-7: Reserved
Bit 8: Wifi is installed
Bit 9: Bluetooth is installed
Bit 10: WWAN is installed
Bits 11-15: Reserved
Bit 16: Hardware switch is on
Bit 17: Wifi is blocked
Bit 18: Bluetooth is blocked
Bit 19: WWAN is blocked
Bits 20-31: Reserved
result[2]: NVRAM size in bytes
result[3]: NVRAM format version number
Input byte 0 = 2: Wireless switch configuration
result[0]: return code
result[1]:
Bit 0: Wifi controlled by switch
Bit 1: Bluetooth controlled by switch
Bit 2: WWAN controlled by switch
Bits 3-6: Reserved
Bit 7: Wireless switch config locked
Bit 8: Wifi locator enabled
Bits 9-14: Reserved
Bit 15: Wifi locator setting locked
Bits 16-31: Reserved
*/
/*
* Derived from information in smbios-wireless-ctl:
*
* cbSelect 17, Value 11
*
* Return Wireless Info
* cbArg1, byte0 = 0x00
*
* cbRes1 Standard return codes (0, -1, -2)
* cbRes2 Info bit flags:
*
* 0 Hardware switch supported (1)
* 1 WiFi locator supported (1)
* 2 WLAN supported (1)
* 3 Bluetooth (BT) supported (1)
* 4 WWAN supported (1)
* 5 Wireless KBD supported (1)
* 6 Uw b supported (1)
* 7 WiGig supported (1)
* 8 WLAN installed (1)
* 9 BT installed (1)
* 10 WWAN installed (1)
* 11 Uw b installed (1)
* 12 WiGig installed (1)
* 13-15 Reserved (0)
* 16 Hardware (HW) switch is On (1)
* 17 WLAN disabled (1)
* 18 BT disabled (1)
* 19 WWAN disabled (1)
* 20 Uw b disabled (1)
* 21 WiGig disabled (1)
* 20-31 Reserved (0)
*
* cbRes3 NVRAM size in bytes
* cbRes4, byte 0 NVRAM format version number
*
*
* Set QuickSet Radio Disable Flag
* cbArg1, byte0 = 0x01
* cbArg1, byte1
* Radio ID value:
* 0 Radio Status
* 1 WLAN ID
* 2 BT ID
* 3 WWAN ID
* 4 UWB ID
* 5 WIGIG ID
* cbArg1, byte2 Flag bits:
* 0 QuickSet disables radio (1)
* 1-7 Reserved (0)
*
* cbRes1 Standard return codes (0, -1, -2)
* cbRes2 QuickSet (QS) radio disable bit map:
* 0 QS disables WLAN
* 1 QS disables BT
* 2 QS disables WWAN
* 3 QS disables UWB
* 4 QS disables WIGIG
* 5-31 Reserved (0)
*
* Wireless Switch Configuration
* cbArg1, byte0 = 0x02
*
* cbArg1, byte1
* Subcommand:
* 0 Get config
* 1 Set config
* 2 Set WiFi locator enable/disable
* cbArg1,byte2
* Switch settings (if byte 1==1):
* 0 WLAN sw itch control (1)
* 1 BT sw itch control (1)
* 2 WWAN sw itch control (1)
* 3 UWB sw itch control (1)
* 4 WiGig sw itch control (1)
* 5-7 Reserved (0)
* cbArg1, byte2 Enable bits (if byte 1==2):
* 0 Enable WiFi locator (1)
*
* cbRes1 Standard return codes (0, -1, -2)
* cbRes2 QuickSet radio disable bit map:
* 0 WLAN controlled by sw itch (1)
* 1 BT controlled by sw itch (1)
* 2 WWAN controlled by sw itch (1)
* 3 UWB controlled by sw itch (1)
* 4 WiGig controlled by sw itch (1)
* 5-6 Reserved (0)
* 7 Wireless sw itch config locked (1)
* 8 WiFi locator enabled (1)
* 9-14 Reserved (0)
* 15 WiFi locator setting locked (1)
* 16-31 Reserved (0)
*
* Read Local Config Data (LCD)
* cbArg1, byte0 = 0x10
* cbArg1, byte1 NVRAM index low byte
* cbArg1, byte2 NVRAM index high byte
* cbRes1 Standard return codes (0, -1, -2)
* cbRes2 4 bytes read from LCD[index]
* cbRes3 4 bytes read from LCD[index+4]
* cbRes4 4 bytes read from LCD[index+8]
*
* Write Local Config Data (LCD)
* cbArg1, byte0 = 0x11
* cbArg1, byte1 NVRAM index low byte
* cbArg1, byte2 NVRAM index high byte
* cbArg2 4 bytes to w rite at LCD[index]
* cbArg3 4 bytes to w rite at LCD[index+4]
* cbArg4 4 bytes to w rite at LCD[index+8]
* cbRes1 Standard return codes (0, -1, -2)
*
* Populate Local Config Data from NVRAM
* cbArg1, byte0 = 0x12
* cbRes1 Standard return codes (0, -1, -2)
*
* Commit Local Config Data to NVRAM
* cbArg1, byte0 = 0x13
* cbRes1 Standard return codes (0, -1, -2)
*/
static int dell_rfkill_set(void *data, bool blocked)
{
......@@ -550,12 +629,21 @@ static int dell_debugfs_show(struct seq_file *s, void *data)
(status & BIT(4)) >> 4);
seq_printf(s, "Bit 5 : Wireless keyboard supported: %lu\n",
(status & BIT(5)) >> 5);
seq_printf(s, "Bit 6 : UWB supported: %lu\n",
(status & BIT(6)) >> 6);
seq_printf(s, "Bit 7 : WiGig supported: %lu\n",
(status & BIT(7)) >> 7);
seq_printf(s, "Bit 8 : Wifi is installed: %lu\n",
(status & BIT(8)) >> 8);
seq_printf(s, "Bit 9 : Bluetooth is installed: %lu\n",
(status & BIT(9)) >> 9);
seq_printf(s, "Bit 10: WWAN is installed: %lu\n",
(status & BIT(10)) >> 10);
seq_printf(s, "Bit 11: UWB installed: %lu\n",
(status & BIT(11)) >> 11);
seq_printf(s, "Bit 12: WiGig installed: %lu\n",
(status & BIT(12)) >> 12);
seq_printf(s, "Bit 16: Hardware switch is on: %lu\n",
(status & BIT(16)) >> 16);
seq_printf(s, "Bit 17: Wifi is blocked: %lu\n",
......@@ -564,6 +652,10 @@ static int dell_debugfs_show(struct seq_file *s, void *data)
(status & BIT(18)) >> 18);
seq_printf(s, "Bit 19: WWAN is blocked: %lu\n",
(status & BIT(19)) >> 19);
seq_printf(s, "Bit 20: UWB is blocked: %lu\n",
(status & BIT(20)) >> 20);
seq_printf(s, "Bit 21: WiGig is blocked: %lu\n",
(status & BIT(21)) >> 21);
seq_printf(s, "\nhwswitch_state:\t0x%X\n", hwswitch_state);
seq_printf(s, "Bit 0 : Wifi controlled by switch: %lu\n",
......@@ -572,6 +664,10 @@ static int dell_debugfs_show(struct seq_file *s, void *data)
(hwswitch_state & BIT(1)) >> 1);
seq_printf(s, "Bit 2 : WWAN controlled by switch: %lu\n",
(hwswitch_state & BIT(2)) >> 2);
seq_printf(s, "Bit 3 : UWB controlled by switch: %lu\n",
(hwswitch_state & BIT(3)) >> 3);
seq_printf(s, "Bit 4 : WiGig controlled by switch: %lu\n",
(hwswitch_state & BIT(4)) >> 4);
seq_printf(s, "Bit 7 : Wireless switch config locked: %lu\n",
(hwswitch_state & BIT(7)) >> 7);
seq_printf(s, "Bit 8 : Wifi locator enabled: %lu\n",
......@@ -1972,12 +2068,11 @@ static int __init dell_init(void)
* Allocate buffer below 4GB for SMI data--only 32-bit physical addr
* is passed to SMI handler.
*/
bufferpage = alloc_page(GFP_KERNEL | GFP_DMA32);
if (!bufferpage) {
buffer = (void *)__get_free_page(GFP_KERNEL | GFP_DMA32);
if (!buffer) {
ret = -ENOMEM;
goto fail_buffer;
}
buffer = page_address(bufferpage);
ret = dell_setup_rfkill();
......@@ -2034,7 +2129,7 @@ static int __init dell_init(void)
fail_backlight:
dell_cleanup_rfkill();
fail_rfkill:
free_page((unsigned long)bufferpage);
free_page((unsigned long)buffer);
fail_buffer:
platform_device_del(platform_device);
fail_platform_device2:
......
/*
* intel_pmc_ipc.c: Driver for the Intel PMC IPC mechanism
*
* (C) Copyright 2014-2015 Intel Corporation
*
* This driver is based on Intel SCU IPC driver(intel_scu_opc.c) by
* Sreedhara DS <sreedhara.ds@intel.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*
* PMC running in ARC processor communicates with other entity running in IA
* core through IPC mechanism which in turn messaging between IA core ad PMC.
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/pm.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/pm_qos.h>
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/sched.h>
#include <linux/atomic.h>
#include <linux/notifier.h>
#include <linux/suspend.h>
#include <linux/acpi.h>
#include <asm/intel_pmc_ipc.h>
#include <linux/mfd/lpc_ich.h>
/*
* IPC registers
* The IA write to IPC_CMD command register triggers an interrupt to the ARC,
* The ARC handles the interrupt and services it, writing optional data to
* the IPC1 registers, updates the IPC_STS response register with the status.
*/
#define IPC_CMD 0x0
#define IPC_CMD_MSI 0x100
#define IPC_CMD_SIZE 16
#define IPC_CMD_SUBCMD 12
#define IPC_STATUS 0x04
#define IPC_STATUS_IRQ 0x4
#define IPC_STATUS_ERR 0x2
#define IPC_STATUS_BUSY 0x1
#define IPC_SPTR 0x08
#define IPC_DPTR 0x0C
#define IPC_WRITE_BUFFER 0x80
#define IPC_READ_BUFFER 0x90
/*
* 16-byte buffer for sending data associated with IPC command.
*/
#define IPC_DATA_BUFFER_SIZE 16
#define IPC_LOOP_CNT 3000000
#define IPC_MAX_SEC 3
#define IPC_TRIGGER_MODE_IRQ true
/* exported resources from IFWI */
#define PLAT_RESOURCE_IPC_INDEX 0
#define PLAT_RESOURCE_IPC_SIZE 0x1000
#define PLAT_RESOURCE_GCR_SIZE 0x1000
#define PLAT_RESOURCE_PUNIT_DATA_INDEX 1
#define PLAT_RESOURCE_PUNIT_INTER_INDEX 2
#define PLAT_RESOURCE_ACPI_IO_INDEX 0
/*
* BIOS does not create an ACPI device for each PMC function,
* but exports multiple resources from one ACPI device(IPC) for
* multiple functions. This driver is responsible to create a
* platform device and to export resources for those functions.
*/
#define TCO_DEVICE_NAME "iTCO_wdt"
#define SMI_EN_OFFSET 0x30
#define SMI_EN_SIZE 4
#define TCO_BASE_OFFSET 0x60
#define TCO_REGS_SIZE 16
#define PUNIT_DEVICE_NAME "intel_punit_ipc"
static const int iTCO_version = 3;
static struct intel_pmc_ipc_dev {
struct device *dev;
void __iomem *ipc_base;
bool irq_mode;
int irq;
int cmd;
struct completion cmd_complete;
/* The following PMC BARs share the same ACPI device with the IPC */
void *acpi_io_base;
int acpi_io_size;
struct platform_device *tco_dev;
/* gcr */
void *gcr_base;
int gcr_size;
/* punit */
void *punit_base;
int punit_size;
void *punit_base2;
int punit_size2;
struct platform_device *punit_dev;
} ipcdev;
static char *ipc_err_sources[] = {
[IPC_ERR_NONE] =
"no error",
[IPC_ERR_CMD_NOT_SUPPORTED] =
"command not supported",
[IPC_ERR_CMD_NOT_SERVICED] =
"command not serviced",
[IPC_ERR_UNABLE_TO_SERVICE] =
"unable to service",
[IPC_ERR_CMD_INVALID] =
"command invalid",
[IPC_ERR_CMD_FAILED] =
"command failed",
[IPC_ERR_EMSECURITY] =
"Invalid Battery",
[IPC_ERR_UNSIGNEDKERNEL] =
"Unsigned kernel",
};
/* Prevent concurrent calls to the PMC */
static DEFINE_MUTEX(ipclock);
static inline void ipc_send_command(u32 cmd)
{
ipcdev.cmd = cmd;
if (ipcdev.irq_mode) {
reinit_completion(&ipcdev.cmd_complete);
cmd |= IPC_CMD_MSI;
}
writel(cmd, ipcdev.ipc_base + IPC_CMD);
}
static inline u32 ipc_read_status(void)
{
return readl(ipcdev.ipc_base + IPC_STATUS);
}
static inline void ipc_data_writel(u32 data, u32 offset)
{
writel(data, ipcdev.ipc_base + IPC_WRITE_BUFFER + offset);
}
static inline u8 ipc_data_readb(u32 offset)
{
return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
}
static inline u32 ipc_data_readl(u32 offset)
{
return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
}
static int intel_pmc_ipc_check_status(void)
{
int status;
int ret = 0;
if (ipcdev.irq_mode) {
if (0 == wait_for_completion_timeout(
&ipcdev.cmd_complete, IPC_MAX_SEC * HZ))
ret = -ETIMEDOUT;
} else {
int loop_count = IPC_LOOP_CNT;
while ((ipc_read_status() & IPC_STATUS_BUSY) && --loop_count)
udelay(1);
if (loop_count == 0)
ret = -ETIMEDOUT;
}
status = ipc_read_status();
if (ret == -ETIMEDOUT) {
dev_err(ipcdev.dev,
"IPC timed out, TS=0x%x, CMD=0x%x\n",
status, ipcdev.cmd);
return ret;
}
if (status & IPC_STATUS_ERR) {
int i;
ret = -EIO;
i = (status >> IPC_CMD_SIZE) & 0xFF;
if (i < ARRAY_SIZE(ipc_err_sources))
dev_err(ipcdev.dev,
"IPC failed: %s, STS=0x%x, CMD=0x%x\n",
ipc_err_sources[i], status, ipcdev.cmd);
else
dev_err(ipcdev.dev,
"IPC failed: unknown, STS=0x%x, CMD=0x%x\n",
status, ipcdev.cmd);
if ((i == IPC_ERR_UNSIGNEDKERNEL) || (i == IPC_ERR_EMSECURITY))
ret = -EACCES;
}
return ret;
}
/*
* intel_pmc_ipc_simple_command
* @cmd: command
* @sub: sub type
*/
int intel_pmc_ipc_simple_command(int cmd, int sub)
{
int ret;
mutex_lock(&ipclock);
if (ipcdev.dev == NULL) {
mutex_unlock(&ipclock);
return -ENODEV;
}
ipc_send_command(sub << IPC_CMD_SUBCMD | cmd);
ret = intel_pmc_ipc_check_status();
mutex_unlock(&ipclock);
return ret;
}
EXPORT_SYMBOL_GPL(intel_pmc_ipc_simple_command);
/*
* intel_pmc_ipc_raw_cmd
* @cmd: command
* @sub: sub type
* @in: input data
* @inlen: input length in bytes
* @out: output data
* @outlen: output length in dwords
* @sptr: data writing to SPTR register
* @dptr: data writing to DPTR register
*/
int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out,
u32 outlen, u32 dptr, u32 sptr)
{
u32 wbuf[4] = { 0 };
int ret;
int i;
if (inlen > IPC_DATA_BUFFER_SIZE || outlen > IPC_DATA_BUFFER_SIZE / 4)
return -EINVAL;
mutex_lock(&ipclock);
if (ipcdev.dev == NULL) {
mutex_unlock(&ipclock);
return -ENODEV;
}
memcpy(wbuf, in, inlen);
writel(dptr, ipcdev.ipc_base + IPC_DPTR);
writel(sptr, ipcdev.ipc_base + IPC_SPTR);
/* The input data register is 32bit register and inlen is in Byte */
for (i = 0; i < ((inlen + 3) / 4); i++)
ipc_data_writel(wbuf[i], 4 * i);
ipc_send_command((inlen << IPC_CMD_SIZE) |
(sub << IPC_CMD_SUBCMD) | cmd);
ret = intel_pmc_ipc_check_status();
if (!ret) {
/* out is read from 32bit register and outlen is in 32bit */
for (i = 0; i < outlen; i++)
*out++ = ipc_data_readl(4 * i);
}
mutex_unlock(&ipclock);
return ret;
}
EXPORT_SYMBOL_GPL(intel_pmc_ipc_raw_cmd);
/*
* intel_pmc_ipc_command
* @cmd: command
* @sub: sub type
* @in: input data
* @inlen: input length in bytes
* @out: output data
* @outlen: output length in dwords
*/
int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
u32 *out, u32 outlen)
{
return intel_pmc_ipc_raw_cmd(cmd, sub, in, inlen, out, outlen, 0, 0);
}
EXPORT_SYMBOL_GPL(intel_pmc_ipc_command);
static irqreturn_t ioc(int irq, void