Commit c4fe57f7 authored by Michael van der Westhuizen's avatar Michael van der Westhuizen Committed by Mark Brown

spi: dw: Allow interface drivers to limit data I/O to word sizes

The commit dd114443 ("spi: dw-spi: Convert 16bit accesses to 32bit
accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit.
This, unfortunately, breaks data register access on picoXcell, where the
DW IP needs data register accesses to be word accesses (all other
accesses appear to be OK).

This change introduces a new master variable to allow interface drivers
to specify that 16bit data transfer I/O is required.  This change also
introduces the ability to set this variable via device tree bindings in
the MMIO interface driver.  Both the core and the MMIO interface driver
default to the current 32bit behaviour.

Before this change, on a picoXcell pc3x3:
 spi_master spi32766: interrupt_transfer: fifo overrun/underrun
 m25p80 spi32766.0: error -5 reading 9f
 m25p80: probe of spi32766.0 failed with error -5

After this change:
 m25p80 spi32766.0: m25p40 (512 Kbytes)

Fixes: dd114443 ("spi: dw-spi: Convert 16bit accesses to 32bit accesses")
Signed-off-by: default avatarMichael van der Westhuizen <>
Reviewed-by: default avatarAndy Shevchenko <>
Signed-off-by: default avatarMark Brown <>
parent 4b226fbd
......@@ -74,6 +74,9 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
dws->max_freq = clk_get_rate(dwsmmio->clk);
of_property_read_u32(pdev->dev.of_node, "reg-io-width",
num_cs = 4;
if (pdev->dev.of_node)
......@@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws)
txw = *(u16 *)(dws->tx);
dw_writel(dws, DW_SPI_DR, txw);
dw_write_io_reg(dws, DW_SPI_DR, txw);
dws->tx += dws->n_bytes;
......@@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws)
u16 rxw;
while (max--) {
rxw = dw_readl(dws, DW_SPI_DR);
rxw = dw_read_io_reg(dws, DW_SPI_DR);
/* Care rx only if the transfer's original "rx" is not null */
if (dws->rx_end - dws->len) {
if (dws->n_bytes == 1)
......@@ -109,6 +109,7 @@ struct dw_spi {
u32 fifo_len; /* depth of the FIFO buffer */
u32 max_freq; /* max bus freq supported */
u32 reg_io_width; /* DR I/O width in bytes */
u16 bus_num;
u16 num_cs; /* supported slave numbers */
......@@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
return __raw_readl(dws->regs + offset);
static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
return __raw_readw(dws->regs + offset);
static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
__raw_writel(val, dws->regs + offset);
static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
__raw_writew(val, dws->regs + offset);
static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
switch (dws->reg_io_width) {
case 2:
return dw_readw(dws, offset);
case 4:
return dw_readl(dws, offset);
static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
switch (dws->reg_io_width) {
case 2:
dw_writew(dws, offset, val);
case 4:
dw_writel(dws, offset, val);
static inline void spi_enable_chip(struct dw_spi *dws, int enable)
dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
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