1. 10 Nov, 2018 1 commit
    • Maciej W. Rozycki's avatar
      MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue · 1c84d14e
      Maciej W. Rozycki authored
      [ Upstream commit 5a1aca44 ]
      
      Sanitize FCSR Cause bit handling, following a trail of past attempts:
      
      * commit 42495484 ("MIPS: ptrace: Fix FP context restoration FCSR
      regression"),
      
      * commit 443c4403 ("MIPS: Always clear FCSR cause bits after
      emulation"),
      
      * commit 64bedffe ("MIPS: Clear [MSA]FPE CSR.Cause after
      notify_die()"),
      
      * commit b1442d39 ("MIPS: Prevent user from setting FCSR cause
      bits"),
      
      * commit b54d2901517d ("Properly handle branch delay slots in connection
      with signals.").
      
      Specifically do not mask these bits out in ptrace(2) processing and send
      a SIGFPE signal instead whenever a matching pair of an FCSR Cause and
      Enable bit is seen as execution of an affected context is about to
      resume.  Only then clear Cause bits, and even then do not clear any bits
      that are set but masked with the respective Enable bits.  Adjust Cause
      bit clearing throughout code likewise, except within the FPU emulator
      proper where they are set according to IEEE 754 exceptions raised as the
      operation emulated executed.  Do so so that any IEEE 754 exceptions
      subject to their default handling are recorded like with operations
      executed by FPU hardware.
      Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/14460/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
      1c84d14e
  2. 08 Jun, 2016 1 commit
    • James Hogan's avatar
      MIPS: Fix watchpoint restoration · 68d64569
      James Hogan authored
      commit a7e89326 upstream.
      
      Commit f51246ef ("MIPS: Get rid of finish_arch_switch().") moved the
      __restore_watch() call from finish_arch_switch() (i.e. after resume()
      returns) to before the resume() call in switch_to(). This results in
      watchpoints only being restored when a task is descheduled, preventing
      the watchpoints from being effective most of the time, except due to
      chance before the watchpoints are lazily removed.
      
      Fix the call sequence from switch_to() through to
      mips_install_watch_registers() to pass the task_struct pointer of the
      next task, instead of using current. This allows the watchpoints for the
      next (non-current) task to be restored without reintroducing
      finish_arch_switch().
      
      Fixes: f51246ef ("MIPS: Get rid of finish_arch_switch().")
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12726/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      68d64569
  3. 03 Sep, 2015 2 commits
    • Paul Burton's avatar
      MIPS: Tidy up FPU context switching · 1a3d5957
      Paul Burton authored
      Rather than saving the scalar FP or vector context in the assembly
      resume function, reuse the existing C code we have in fpu.h to do
      exactly that. This reduces duplication, results in a much easier to read
      resume function & should allow the compiler to optimise out more MSA
      code due to is_msa_enabled()/cpu_has_msa being known-zero at compile
      time for kernels without MSA support.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
      Cc: Maciej W. Rozycki <macro@linux-mips.org>
      Cc: linux-kernel@vger.kernel.org
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: Markos Chandras <markos.chandras@imgtec.com>
      Cc: Manuel Lauss <manuel.lauss@gmail.com>
      Patchwork: https://patchwork.linux-mips.org/patch/10830/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      1a3d5957
    • Ralf Baechle's avatar
      MIPS: Get rid of finish_arch_switch(). · f51246ef
      Ralf Baechle authored
      MIPS was using finish_arch_switch() as a hook to restore and initialize
      CPU context for all threads, even newly created kernel and user threads.
      This is however entirely solvable within switch_to() so get rid of
      finish_arch_switch() which is in the way of scheduler cleanups.
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      f51246ef
  4. 04 Aug, 2015 1 commit
    • Ralf Baechle's avatar
      sched, MIPS: Get rid of finish_arch_switch() · 6916ce3f
      Ralf Baechle authored
      MIPS was using finish_arch_switch() as a hook to restore and initialize
      CPU context for all threads, even newly created kernel and user threads.
      This is however entirely solvable within switch_to() so get rid of
      finish_arch_switch() which is in the way of scheduler cleanups.
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Mike Galbraith <efault@gmx.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-kernel@vger.kernel.org
      Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
      6916ce3f
  5. 10 Jun, 2015 1 commit
  6. 17 Feb, 2015 1 commit
    • Markos Chandras's avatar
      MIPS: Make use of the ERETNC instruction on MIPS R6 · 7c151d3d
      Markos Chandras authored
      The ERETNC instruction, introduced in MIPS R5, is similar to the ERET
      one, except it does not clear the LLB bit in the LLADDR register.
      This feature is necessary to safely emulate R2 LL/SC instructions.
      However, on context switches, we need to clear the LLAddr/LLB bit
      in order to make sure that an SC instruction from the new thread
      will never succeed if it happens to interrupt an LL operation on the
      same address from the previous thread.
      Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
      7c151d3d
  7. 26 Aug, 2014 1 commit
  8. 26 Mar, 2014 1 commit
    • Paul Burton's avatar
      MIPS: Basic MSA context switching support · 1db1af84
      Paul Burton authored
      This patch adds support for context switching the MSA vector registers.
      These 128 bit vector registers are aliased with the FP registers - an
      FP register accesses the least significant bits of the vector register
      with which it is aliased (ie. the register with the same index). Due to
      both this & the requirement that the scalar FPU must be 64-bit (FR=1) if
      enabled at the same time as MSA the kernel will enable MSA & scalar FP
      at the same time for tasks which use MSA. If we restore the MSA vector
      context then we might as well enable the scalar FPU since the reason it
      was left disabled was to allow for lazy FP context restoring - but we
      just restored the FP context as it's a subset of the vector context. If
      we restore the FP context and have previously used MSA then we have to
      restore the whole vector context anyway (see comment in
      enable_restore_fp_context for details) so similarly we might as well
      enable MSA.
      
      Thus if a task does not use MSA then it will continue to behave as
      without this patch - the scalar FP context will be saved & restored as
      usual. But if a task executes an MSA instruction then it will save &
      restore the vector context forever more.
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/6431/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      1db1af84
  9. 24 Jan, 2014 1 commit
  10. 13 Jun, 2013 1 commit
  11. 01 Feb, 2013 1 commit
  12. 19 Jul, 2012 1 commit
  13. 28 Mar, 2012 1 commit