1. 15 Sep, 2018 2 commits
  2. 22 Jul, 2018 6 commits
  3. 30 May, 2018 1 commit
  4. 20 Apr, 2018 7 commits
  5. 20 Oct, 2016 1 commit
    • James Morse's avatar
      arm64: cpufeature: Schedule enable() calls instead of calling them via IPI · 2a6dcb2b
      James Morse authored
      The enable() call for a cpufeature/errata is called using on_each_cpu().
      This issues a cross-call IPI to get the work done. Implicitly, this
      stashes the running PSTATE in SPSR when the CPU receives the IPI, and
      restores it when we return. This means an enable() call can never modify
      To allow PAN to do this, change the on_each_cpu() call to use
      stop_machine(). This schedules the work on each CPU which allows
      us to modify PSTATE.
      This involves changing the protype of all the enable() functions.
      enable_cpu_capabilities() is called during boot and enables the feature
      on all online CPUs. This path now uses stop_machine(). CPU features for
      hotplug'd CPUs are enabled by verify_local_cpu_features() which only
      acts on the local CPU, and can already modify the running PSTATE as it
      is called from secondary_start_kernel().
      Reported-by: default avatarTony Thompson <anthony.thompson@arm.com>
      Reported-by: default avatarVladimir Murzin <vladimir.murzin@arm.com>
      Signed-off-by: default avatarJames Morse <james.morse@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
  6. 09 Sep, 2016 2 commits
    • Suzuki K Poulose's avatar
      arm64: Work around systems with mismatched cache line sizes · 116c81f4
      Suzuki K Poulose authored
      Systems with differing CPU i-cache/d-cache line sizes can cause
      problems with the cache management by software when the execution
      is migrated from one to another. Usually, the application reads
      the cache size on a CPU and then uses that length to perform cache
      operations. However, if it gets migrated to another CPU with a smaller
      cache line size, things could go completely wrong. To prevent such
      cases, always use the smallest cache line size among the CPUs. The
      kernel CPU feature infrastructure already keeps track of the safe
      value for all CPUID registers including CTR. This patch works around
      the problem by :
      For kernel, dynamically patch the kernel to read the cache size
      from the system wide copy of CTR_EL0.
      For applications, trap read accesses to CTR_EL0 (by clearing the SCTLR.UCT)
      and emulate the mrs instruction to return the system wide safe value
      of CTR_EL0.
      For faster access (i.e, avoiding to lookup the system wide value of CTR_EL0
      via read_system_reg), we keep track of the pointer to table entry for
      CTR_EL0 in the CPU feature infrastructure.
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Andre Przywara <andre.przywara@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
    • Suzuki K Poulose's avatar
      arm64: Use consistent naming for errata handling · 89ba2645
      Suzuki K Poulose authored
      This is a cosmetic change to rename the functions dealing with
      the errata work arounds to be more consistent with their naming.
      1) check_local_cpu_errata() => update_cpu_errata_workarounds()
      check_local_cpu_errata() actually updates the system's errata work
      arounds. So rename it to reflect the same.
      2) verify_local_cpu_errata() => verify_local_cpu_errata_workarounds()
      Use errata_workarounds instead of _errata.
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Acked-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
  7. 07 Jul, 2016 1 commit
  8. 01 Jul, 2016 2 commits
  9. 25 Apr, 2016 2 commits
  10. 26 Feb, 2016 1 commit
  11. 16 Feb, 2016 1 commit
  12. 24 Nov, 2015 1 commit
  13. 21 Oct, 2015 1 commit
  14. 29 Sep, 2015 1 commit
  15. 01 Apr, 2015 2 commits
  16. 30 Mar, 2015 1 commit
  17. 25 Nov, 2014 5 commits