• Maciej W. Rozycki's avatar
    MIPS: SiByte: Enable swiotlb for SWARM, LittleSur and BigSur · c890a458
    Maciej W. Rozycki authored
    [ Upstream commit e4849aff1e169b86c561738daf8ff020e9de1011 ]
    The Broadcom SiByte BCM1250, BCM1125, and BCM1125H SOCs have an onchip
    DRAM controller that supports memory amounts of up to 16GiB, and due to
    how the address decoder has been wired in the SOC any memory beyond 1GiB
    is actually mapped starting from 4GiB physical up, that is beyond the
    32-bit addressable limit[1].  Consequently if the maximum amount of
    memory has been installed, then it will span up to 19GiB.
    Many of the evaluation boards we support that are based on one of these
    SOCs have their memory soldered and the amount present fits in the
    32-bit address range.  The BCM91250A SWARM board however has actual DIMM
    slots and accepts, depending on the peripherals revision of the SOC, up
    to 4GiB or 8GiB of memory in commercially available JEDEC modules[2].
    I believe this is also the case with the BCM91250C2 LittleSur board.
    This means that up to either 3GiB or 7GiB of memory requires 64-bit
    addressing to access.
    I believe the BCM91480B BigSur board, which has the BCM1480 SOC instead,
    accepts at least as much memory, although I have no documentation or
    actual hardware available to verify that.
    Both systems have PCI slots installed for use by any PCI option boards,
    including ones that only support 32-bit addressing (additionally the
    32-bit PCI host bridge of the BCM1250, BCM1125, and BCM1125H SOCs limits
    addressing to 32-bits), and there is no IOMMU available.  Therefore for
    PCI DMA to work in the presence of memory beyond enable swiotlb for the
    affected systems.
    All the other SOC onchip DMA devices use 40-bit addressing and therefore
    can address the whole memory, so only enable swiotlb if PCI support and
    support for DMA beyond 4GiB have been both enabled in the configuration
    of the kernel.
    This shows up as follows:
    Broadcom SiByte BCM1250 B2 @ 800 MHz (SB1 rev 2)
    Board type: SiByte BCM91250A (SWARM)
    Determined physical RAM map:
     memory: 000000000fe7fe00 @ 0000000000000000 (usable)
     memory: 000000001ffffe00 @ 0000000080000000 (usable)
     memory: 000000000ffffe00 @ 00000000c0000000 (usable)
     memory: 0000000087fffe00 @ 0000000100000000 (usable)
    software IO TLB: mapped [mem 0xcbffc000-0xcfffc000] (64MB)
    in the bootstrap log and removes failures like these:
    defxx 0000:02:00.0: dma_direct_map_page: overflow 0x0000000185bc6080+4608 of device mask ffffffff bus mask 0
    fddi0: Receive buffer allocation failed
    fddi0: Adapter open failed!
    IP-Config: Failed to open fddi0
    defxx 0000:09:08.0: dma_direct_map_page: overflow 0x0000000185bc6080+4608 of device mask ffffffff bus mask 0
    fddi1: Receive buffer allocation failed
    fddi1: Adapter open failed!
    IP-Config: Failed to open fddi1
    when memory beyond 4GiB is handed out to devices that can only do 32-bit
    This updates commit cce335ae ("[MIPS] 64-bit Sibyte kernels need
    [1] "BCM1250/BCM1125/BCM1125H User Manual", Revision 1250_1125-UM100-R,
        Broadcom Corporation, 21 Oct 2002, Section 3: "System Overview",
        "Memory Map", pp. 34-38
    [2] "BCM91250A User Manual", Revision 91250A-UM100-R, Broadcom
        Corporation, 18 May 2004, Section 3: "Physical Description",
        "Supported DRAM", p. 23
    Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
    [paul.burton@mips.com: Remove GPL text from dma.c; SPDX tag covers it]
    Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
    Reviewed-by: default avatarChristoph Hellwig <hch@lst.de>
    Patchwork: https://patchwork.linux-mips.org/patch/21108/
    References: cce335ae ("[MIPS] 64-bit Sibyte kernels need DMA32.")
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: linux-mips@linux-mips.org
    Cc: linux-kernel@vger.kernel.org
    Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
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