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    sparc64: Niagara-4 bzero/memset, plus use MRU stores in page copy. · 9f825962
    David S. Miller authored
    
    
    This adds optimized memset/bzero/page-clear routines for Niagara-4.
    
    We basically can do what powerpc has been able to do for a decade (via
    the "dcbz" instruction), which is use cache line clearing stores for
    bzero and memsets with a 'c' argument of zero.
    
    As long as we make the cache initializing store to each 32-byte
    subblock of the L2 cache line, it works.
    
    As with other Niagara-4 optimized routines, the key is to make sure to
    avoid any usage of the %asi register, as reads and writes to it cost
    at least 50 cycles.
    
    For the user clear cases, we don't use these new routines, we use the
    Niagara-1 variants instead.  Those have to use %asi in an unavoidable
    way.
    
    A Niagara-4 8K page clear costs just under 600 cycles.
    
    Add definitions of the MRU variants of the cache initializing store
    ASIs.  By default, cache initializing stores install the line as Least
    Recently Used.  If we know we're going to use the data immediately
    (which is true for page copies and clears) we can use the Most
    Recently Used variant, to decrease the likelyhood of the lines being
    evicted before they get used.
    
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    9f825962