Commit 6fe07aaf authored by Finn Thain's avatar Finn Thain Committed by James Bottomley

[SCSI] m68k: new mac_esp scsi driver

Replace the mac_esp driver with a new one based on the esp_scsi core.

For esp_scsi: add support for sync transfers for the PIO mode, add a new
esp_driver_ops method to get the maximum dma transfer size (like the old
NCR53C9x driver), and some cleanups.
Signed-off-by: default avatarFinn Thain <fthain@telegraphics.com.au>
Acked-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: default avatarJames Bottomley <James.Bottomley@HansenPartnership.com>
parent 6d9d63b9
......@@ -1677,6 +1677,16 @@ config MAC_SCSI
SCSI-HOWTO, available from
<http://www.tldp.org/docs.html#howto>.
config SCSI_MAC_ESP
tristate "Macintosh NCR53c9[46] SCSI"
depends on MAC && SCSI
help
This is the NCR 53c9x SCSI controller found on most of the 68040
based Macintoshes.
To compile this driver as a module, choose M here: the module
will be called mac_esp.
config MVME147_SCSI
bool "WD33C93 SCSI driver for MVME147"
depends on MVME147 && SCSI=y
......
......@@ -46,6 +46,7 @@ obj-$(CONFIG_MVME147_SCSI) += mvme147.o wd33c93.o
obj-$(CONFIG_SGIWD93_SCSI) += sgiwd93.o wd33c93.o
obj-$(CONFIG_ATARI_SCSI) += atari_scsi.o
obj-$(CONFIG_MAC_SCSI) += mac_scsi.o
obj-$(CONFIG_SCSI_MAC_ESP) += esp_scsi.o mac_esp.o
obj-$(CONFIG_SUN3_SCSI) += sun3_scsi.o sun3_scsi_vme.o
obj-$(CONFIG_MVME16x_SCSI) += 53c700.o mvme16x_scsi.o
obj-$(CONFIG_BVME6000_SCSI) += 53c700.o bvme6000_scsi.o
......
......@@ -978,7 +978,7 @@ static int esp_check_spur_intr(struct esp *esp)
*/
if (!esp->ops->dma_error(esp)) {
printk(KERN_ERR PFX "esp%d: Spurious irq, "
"sreg=%x.\n",
"sreg=%02x.\n",
esp->host->unique_id, esp->sreg);
return -1;
}
......@@ -1447,6 +1447,9 @@ static void esp_msgin_sdtr(struct esp *esp, struct esp_target_data *tp)
if (offset > 15)
goto do_reject;
if (esp->flags & ESP_FLAG_DISABLE_SYNC)
offset = 0;
if (offset) {
int rounded_up, one_clock;
......@@ -1697,7 +1700,12 @@ again:
else
ent->flags &= ~ESP_CMD_FLAG_WRITE;
dma_len = esp_dma_length_limit(esp, dma_addr, dma_len);
if (esp->ops->dma_length_limit)
dma_len = esp->ops->dma_length_limit(esp, dma_addr,
dma_len);
else
dma_len = esp_dma_length_limit(esp, dma_addr, dma_len);
esp->data_dma_len = dma_len;
if (!dma_len) {
......@@ -1761,7 +1769,6 @@ again:
esp_advance_dma(esp, ent, cmd, bytes_sent);
esp_event(esp, ESP_EVENT_CHECK_PHASE);
goto again;
break;
}
case ESP_EVENT_STATUS: {
......@@ -2235,7 +2242,7 @@ static void esp_bootup_reset(struct esp *esp)
static void esp_set_clock_params(struct esp *esp)
{
int fmhz;
int fhz;
u8 ccf;
/* This is getting messy but it has to be done correctly or else
......@@ -2270,9 +2277,9 @@ static void esp_set_clock_params(struct esp *esp)
* This entails the smallest and largest sync period we could ever
* handle on this ESP.
*/
fmhz = esp->cfreq;
fhz = esp->cfreq;
ccf = ((fmhz / 1000000) + 4) / 5;
ccf = ((fhz / 1000000) + 4) / 5;
if (ccf == 1)
ccf = 2;
......@@ -2281,16 +2288,16 @@ static void esp_set_clock_params(struct esp *esp)
* been unable to find the clock-frequency PROM property. All
* other machines provide useful values it seems.
*/
if (fmhz <= 5000000 || ccf < 1 || ccf > 8) {
fmhz = 20000000;
if (fhz <= 5000000 || ccf < 1 || ccf > 8) {
fhz = 20000000;
ccf = 4;
}
esp->cfact = (ccf == 8 ? 0 : ccf);
esp->cfreq = fmhz;
esp->ccycle = ESP_MHZ_TO_CYCLE(fmhz);
esp->cfreq = fhz;
esp->ccycle = ESP_HZ_TO_CYCLE(fhz);
esp->ctick = ESP_TICK(ccf, esp->ccycle);
esp->neg_defp = ESP_NEG_DEFP(fmhz, ccf);
esp->neg_defp = ESP_NEG_DEFP(fhz, ccf);
esp->sync_defp = SYNC_DEFP_SLOW;
}
......@@ -2382,6 +2389,12 @@ static int esp_slave_configure(struct scsi_device *dev)
struct esp_target_data *tp = &esp->target[dev->id];
int goal_tags, queue_depth;
if (esp->flags & ESP_FLAG_DISABLE_SYNC) {
/* Bypass async domain validation */
dev->ppr = 0;
dev->sdtr = 0;
}
goal_tags = 0;
if (dev->tagged_supported) {
......
......@@ -224,7 +224,7 @@
#define ESP_TIMEO_CONST 8192
#define ESP_NEG_DEFP(mhz, cfact) \
((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
#define ESP_MHZ_TO_CYCLE(mhertz) ((1000000000) / ((mhertz) / 1000))
#define ESP_HZ_TO_CYCLE(hertz) ((1000000000) / ((hertz) / 1000))
#define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
/* For slow to medium speed input clock rates we shoot for 5mb/s, but for high
......@@ -368,6 +368,12 @@ struct esp_driver_ops {
*/
int (*irq_pending)(struct esp *esp);
/* Return the maximum allowable size of a DMA transfer for a
* given buffer.
*/
u32 (*dma_length_limit)(struct esp *esp, u32 dma_addr,
u32 dma_len);
/* Reset the DMA engine entirely. On return, ESP interrupts
* should be enabled. Often the interrupt enabling is
* controlled in the DMA engine.
......@@ -471,6 +477,7 @@ struct esp {
#define ESP_FLAG_DOING_SLOWCMD 0x00000004
#define ESP_FLAG_WIDE_CAPABLE 0x00000008
#define ESP_FLAG_QUICKIRQ_CHECK 0x00000010
#define ESP_FLAG_DISABLE_SYNC 0x00000020
u8 select_state;
#define ESP_SELECT_NONE 0x00 /* Not selecting */
......
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