1. 10 Nov, 2018 1 commit
    • Maciej W. Rozycki's avatar
      MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue · 1c84d14e
      Maciej W. Rozycki authored
      [ Upstream commit 5a1aca44 ]
      Sanitize FCSR Cause bit handling, following a trail of past attempts:
      * commit 42495484 ("MIPS: ptrace: Fix FP context restoration FCSR
      * commit 443c4403 ("MIPS: Always clear FCSR cause bits after
      * commit 64bedffe ("MIPS: Clear [MSA]FPE CSR.Cause after
      * commit b1442d39 ("MIPS: Prevent user from setting FCSR cause
      * commit b54d2901517d ("Properly handle branch delay slots in connection
      with signals.").
      Specifically do not mask these bits out in ptrace(2) processing and send
      a SIGFPE signal instead whenever a matching pair of an FCSR Cause and
      Enable bit is seen as execution of an affected context is about to
      resume.  Only then clear Cause bits, and even then do not clear any bits
      that are set but masked with the respective Enable bits.  Adjust Cause
      bit clearing throughout code likewise, except within the FPU emulator
      proper where they are set according to IEEE 754 exceptions raised as the
      operation emulated executed.  Do so so that any IEEE 754 exceptions
      subject to their default handling are recorded like with operations
      executed by FPU hardware.
      Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/14460/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
  2. 07 Apr, 2015 2 commits
  3. 01 Apr, 2015 1 commit
  4. 26 Aug, 2014 1 commit
  5. 30 May, 2014 1 commit
  6. 23 May, 2014 1 commit
  7. 09 May, 2013 1 commit
  8. 12 Apr, 2010 1 commit
  9. 17 Dec, 2009 1 commit
    • David Daney's avatar
      MIPS: Collect FPU emulator statistics per-CPU. · b6ee75ed
      David Daney authored
      On SMP systems, the collection of statistics can cause cache line
      bouncing in the lines associated with the counters.  Also there are
      races incrementing the counters on multiple CPUs.
      To fix both problems, we collect the statistics in per-CPU variables,
      and add them up in the debugfs read operation.
      As a test I ran the LTP float_bessel test on a 12 CPU Octeon system.
      Without CONFIG_DEBUG_FS :             2602 seconds.
      With CONFIG_DEBUG_FS:                 2640 seconds.
      With non-cpu-local atomic statistics: 14569 seconds.
      Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
      Cc: linux-mips@linux-mips.org
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
  10. 30 Oct, 2008 1 commit
  11. 11 Oct, 2008 1 commit
  12. 19 Jun, 2006 1 commit
  13. 29 Oct, 2005 3 commits
  14. 16 Apr, 2005 1 commit
    • Linus Torvalds's avatar
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds authored
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      Let it rip!