1. 23 Jan, 2015 1 commit
    • Suzuki K. Poulose's avatar
      arm64: Emulate SETEND for AArch32 tasks · 2d888f48
      Suzuki K. Poulose authored
      Emulate deprecated 'setend' instruction for AArch32 bit tasks.
      
      	setend [le/be] - Sets the endianness of EL0
      
      On systems with CPUs which support mixed endian at EL0, the hardware
      support for the instruction can be enabled by setting the SCTLR_EL1.SED
      bit. Like the other emulated instructions it is controlled by an entry in
      /proc/sys/abi/. For more information see :
      	Documentation/arm64/legacy_instructions.txt
      
      The instruction is emulated by setting/clearing the SPSR_EL1.E bit, which
      will be reflected in the PSTATE.E in AArch32 context.
      
      This patch also restores the native endianness for the execution of signal
      handlers, since the process could have changed the endianness.
      
      Note: All CPUs on the system must have mixed endian support at EL0. Once the
      handler is registered, hotplugging a CPU which doesn't support mixed endian,
      could lead to unexpected results/behavior in applications.
      Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Punit Agrawal <punit.agrawal@arm.com>
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      2d888f48
  2. 20 Nov, 2014 3 commits
    • Punit Agrawal's avatar
      arm64: Emulate CP15 Barrier instructions · c852f320
      Punit Agrawal authored
      The CP15 barrier instructions (CP15ISB, CP15DSB and CP15DMB) are
      deprecated in the ARMv7 architecture, superseded by ISB, DSB and DMB
      instructions respectively. Some implementations may provide the
      ability to disable the CP15 barriers by disabling the CP15BEN bit in
      SCTLR_EL1. If not enabled, the encodings for these instructions become
      undefined.
      
      To support legacy software using these instructions, this patch
      register hooks to -
      * emulate CP15 barriers and warn the user about their use
      * toggle CP15BEN in SCTLR_EL1
      Signed-off-by: default avatarPunit Agrawal <punit.agrawal@arm.com>
      Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      c852f320
    • Punit Agrawal's avatar
      arm64: Port SWP/SWPB emulation support from arm · bd35a4ad
      Punit Agrawal authored
      The SWP instruction was deprecated in the ARMv6 architecture. The
      ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions
      are treated as undefined from reset, with the ability to enable them
      through the System Control Register SW bit. With ARMv8, the option to
      enable these instructions through System Control Register was dropped
      as well.
      
      To support legacy applications using these instructions, port the
      emulation of the SWP and SWPB instructions from the arm port to arm64.
      Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarPunit Agrawal <punit.agrawal@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      bd35a4ad
    • Punit Agrawal's avatar
      arm64: Add framework for legacy instruction emulation · 587064b6
      Punit Agrawal authored
      Typically, providing support for legacy instructions requires
      emulating the behaviour of instructions whose encodings have become
      undefined. If the instructions haven't been removed from the
      architecture, there maybe an option in the implementation to turn
      on/off the support for these instructions.
      
      Create common infrastructure to support legacy instruction
      emulation. In addition to emulation, also provide an option to support
      hardware execution when supported. The default execution mode (one of
      undef, emulate, hw exeuction) is dependent on the state of the
      instruction (deprecated or obsolete) in the architecture and
      can specified at the time of registering the instruction handlers. The
      runtime state of the emulation can be controlled by writing to
      individual nodes in sysctl. The expected default behaviour is
      documented as part of this patch.
      Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: default avatarPunit Agrawal <punit.agrawal@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      587064b6