rt_imx_uart.c 42.7 KB
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/*
 * Copyright 2012 Wolfgang Grandegger <wg@denx.de>
 *
 * Derived from the Linux IMX UART driver (drivers/tty/serial/imx.c)
 * and 16650A RTserial driver.
 *
 * Copyright (C) 2005-2007 Jan Kiszka <jan.kiszka@web.de>.
 * Copyright (C) 2004 Pengutronix
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/tty.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/console.h>
#include <linux/platform_device.h>
#include <linux/sysrq.h>
#include <linux/dma-mapping.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/rational.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/dma.h>
#include <asm/div64.h>
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#include <linux/platform_data/serial-imx.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
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#include <rtdm/serial.h>
#include <rtdm/driver.h>
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MODULE_AUTHOR("Wolfgang Grandegger <wg@denx.de>");
MODULE_DESCRIPTION("RTDM-based driver for IMX UARTs");
MODULE_VERSION("1.0.0");
MODULE_LICENSE("GPL");

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#define DRIVER_NAME	"xeno_imx_uart"

/* Register definitions */
#define URXD0	0x0  /* Receiver Register */
#define URTX0	0x40 /* Transmitter Register */
#define UCR1	0x80 /* Control Register 1 */
#define UCR2	0x84 /* Control Register 2 */
#define UCR3	0x88 /* Control Register 3 */
#define UCR4	0x8c /* Control Register 4 */
#define UFCR	0x90 /* FIFO Control Register */
#define USR1	0x94 /* Status Register 1 */
#define USR2	0x98 /* Status Register 2 */
#define UESC	0x9c /* Escape Character Register */
#define UTIM	0xa0 /* Escape Timer Register */
#define UBIR	0xa4 /* BRM Incremental Register */
#define UBMR	0xa8 /* BRM Modulator Register */
#define UBRC	0xac /* Baud Rate Count Register */
#define MX2_ONEMS 0xb0 /* One Millisecond register */
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#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/


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/* UART Control Register Bit Fields.*/
#define URXD_CHARRDY	(1<<15)
#define URXD_ERR	(1<<14)
#define URXD_OVRRUN	(1<<13)
#define URXD_FRMERR	(1<<12)
#define URXD_BRK	(1<<11)
#define URXD_PRERR	(1<<10)
#define UCR1_ADEN	(1<<15) /* Auto dectect interrupt */
#define UCR1_ADBR	(1<<14) /* Auto detect baud rate */
#define UCR1_TRDYEN	(1<<13) /* Transmitter ready interrupt enable */
#define UCR1_IDEN	(1<<12) /* Idle condition interrupt */
#define UCR1_RRDYEN	(1<<9)	/* Recv ready interrupt enable */
#define UCR1_RDMAEN	(1<<8)	/* Recv ready DMA enable */
#define UCR1_IREN	(1<<7)	/* Infrared interface enable */
#define UCR1_TXMPTYEN	(1<<6)	/* Transimitter empty interrupt enable */
#define UCR1_RTSDEN	(1<<5)	/* RTS delta interrupt enable */
#define UCR1_SNDBRK	(1<<4)	/* Send break */
#define UCR1_TDMAEN	(1<<3)	/* Transmitter ready DMA enable */
#define MX1_UCR1_UARTCLKEN	(1<<2)	/* UART clock enabled, mx1 only */
#define UCR1_DOZE	(1<<1)	/* Doze */
#define UCR1_UARTEN	(1<<0)	/* UART enabled */
#define UCR2_ESCI	(1<<15) /* Escape seq interrupt enable */
#define UCR2_IRTS	(1<<14) /* Ignore RTS pin */
#define UCR2_CTSC	(1<<13) /* CTS pin control */
#define UCR2_CTS	(1<<12) /* Clear to send */
#define UCR2_ESCEN	(1<<11) /* Escape enable */
#define UCR2_PREN	(1<<8)	/* Parity enable */
#define UCR2_PROE	(1<<7)	/* Parity odd/even */
#define UCR2_STPB	(1<<6)	/* Stop */
#define UCR2_WS		(1<<5)	/* Word size */
#define UCR2_RTSEN	(1<<4)	/* Request to send interrupt enable */
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#define UCR2_ATEN	(1<<3)	/* Aging Timer Enable */
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#define UCR2_TXEN	(1<<2)	/* Transmitter enabled */
#define UCR2_RXEN	(1<<1)	/* Receiver enabled */
#define UCR2_SRST	(1<<0)	/* SW reset */
#define UCR3_DTREN	(1<<13) /* DTR interrupt enable */
#define UCR3_PARERREN	(1<<12) /* Parity enable */
#define UCR3_FRAERREN	(1<<11) /* Frame error interrupt enable */
#define UCR3_DSR	(1<<10) /* Data set ready */
#define UCR3_DCD	(1<<9)	/* Data carrier detect */
#define UCR3_RI		(1<<8)	/* Ring indicator */
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#define UCR3_ADNIMP	(1<<7)	/* Autobaud Detection Not Improved */
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#define UCR3_RXDSEN	(1<<6)	/* Receive status interrupt enable */
#define UCR3_AIRINTEN	(1<<5)	/* Async IR wake interrupt enable */
#define UCR3_AWAKEN	(1<<4)	/* Async wake interrupt enable */
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#define UCR3_DTRDEN	(1<<3)	/* Data Terminal Ready Delta Enable. */
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#define MX1_UCR3_REF25		(1<<3)	/* Ref freq 25 MHz, only on mx1 */
#define MX1_UCR3_REF30		(1<<2)	/* Ref Freq 30 MHz, only on mx1 */
#define MX2_UCR3_RXDMUXSEL	(1<<2)	/* RXD Muxed Input Select, on mx2/mx3 */
#define UCR3_INVT	(1<<1)	/* Inverted Infrared transmission */
#define UCR3_BPEN	(1<<0)	/* Preset registers enable */
#define UCR4_CTSTL_SHF	10	/* CTS trigger level shift */
#define UCR4_CTSTL_MASK	0x3F	/* CTS trigger is 6 bits wide */
#define UCR4_INVR	(1<<9)	/* Inverted infrared reception */
#define UCR4_ENIRI	(1<<8)	/* Serial infrared interrupt enable */
#define UCR4_WKEN	(1<<7)	/* Wake interrupt enable */
#define UCR4_REF16	(1<<6)	/* Ref freq 16 MHz */
#define UCR4_IRSC	(1<<5)	/* IR special case */
#define UCR4_TCEN	(1<<3)	/* Transmit complete interrupt enable */
#define UCR4_BKEN	(1<<2)	/* Break condition interrupt enable */
#define UCR4_OREN	(1<<1)	/* Receiver overrun interrupt enable */
#define UCR4_DREN	(1<<0)	/* Recv data ready interrupt enable */
#define UFCR_RXTL_SHF	0	/* Receiver trigger level shift */
#define UFCR_RFDIV	(7<<7)	/* Reference freq divider mask */
#define UFCR_RFDIV_REG(x)	(((x) < 7 ? 6 - (x) : 6) << 7)
#define UFCR_TXTL_SHF	10	/* Transmitter trigger level shift */
#define UFCR_DCEDTE	(1<<6)
#define USR1_PARITYERR	(1<<15) /* Parity error interrupt flag */
#define USR1_RTSS	(1<<14) /* RTS pin status */
#define USR1_TRDY	(1<<13) /* Transmitter ready interrupt/dma flag */
#define USR1_RTSD	(1<<12) /* RTS delta */
#define USR1_ESCF	(1<<11) /* Escape seq interrupt flag */
#define USR1_FRAMERR	(1<<10) /* Frame error interrupt flag */
#define USR1_RRDY	(1<<9)	/* Receiver ready interrupt/dma flag */
#define USR1_AGTIM	(1<<8)	/* Ageing Timer Interrupt Flag */
#define USR1_DTRD	(1<<7)	/* DTR Delta */
#define USR1_RXDS	(1<<6)	/* Receiver idle interrupt flag */
#define USR1_AIRINT	(1<<5)	/* Async IR wake interrupt flag */
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#define USR1_AWAKE	(1<<4)	/* Async wake interrupt flag */
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#define USR2_ADET	(1<<15) /* Auto baud rate detect complete */
#define USR2_TXFE	(1<<14) /* Transmit buffer FIFO empty */
#define USR2_DTRF	(1<<13) /* DTR edge interrupt flag */
#define USR2_IDLE	(1<<12) /* Idle condition */
#define USR2_RIDELT	(1<<10) /* Ring Indicator Delta */
#define USR2_RIIN	(1<<9)	/* Ring Indicator Input */
#define USR2_IRINT	(1<<8)	/* Serial infrared interrupt flag */
#define USR2_WAKE	(1<<7)	/* Wake */
#define USR2_DCDDELT	(1<<6)	/* Data Carrier Detect Delta */
#define USR2_DCDIN	(1<<5)	/* Data Carrier Detect Input */
#define USR2_RTSF	(1<<4)	/* RTS edge interrupt flag */
#define USR2_TXDC	(1<<3)	/* Transmitter complete */
#define USR2_BRCD	(1<<2)	/* Break condition */
#define USR2_ORE	(1<<1)	/* Overrun error */
#define USR2_RDR	(1<<0)	/* Recv data ready */
#define UTS_FRCPERR	(1<<13) /* Force parity error */
#define UTS_LOOP	(1<<12) /* Loop tx and rx */
#define UTS_TXEMPTY	(1<<6)	/* TxFIFO empty */
#define UTS_RXEMPTY	(1<<5)	/* RxFIFO empty */
#define UTS_TXFULL	(1<<4)	/* TxFIFO full */
#define UTS_RXFULL	(1<<3)	/* RxFIFO full */
#define UTS_SOFTRST	(1<<0)	/* Software reset */

#define IN_BUFFER_SIZE		4096
#define OUT_BUFFER_SIZE		4096

#define TX_FIFO_SIZE		32

#define PARITY_MASK		0x03
#define DATA_BITS_MASK		0x03
#define STOP_BITS_MASK		0x01
#define FIFO_MASK		0xC0
#define EVENT_MASK		0x0F

#define IER_RX			0x01
#define IER_TX			0x02
#define IER_STAT		0x04
#define IER_MODEM		0x08

#define IMX_ISR_PASS_LIMIT	256
#define UART_CREAD_BIT		256

#define RT_IMX_UART_MAX		5

static int tx_fifo[RT_IMX_UART_MAX];
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module_param_array(tx_fifo, int, NULL, 0400);
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MODULE_PARM_DESC(tx_fifo, "Transmitter FIFO size");

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/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
enum imx_uart_type {
	IMX1_UART,
	IMX21_UART,
	IMX53_UART,
	IMX6Q_UART,
};

/* device type dependent stuff */
struct imx_uart_data {
	unsigned int uts_reg;
	enum imx_uart_type devtype;
};


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struct rt_imx_uart_port {
	unsigned char __iomem *membase;	/* read/write[bwl] */
	resource_size_t mapbase;	/* for ioremap */
	unsigned int irq;		/* irq number */
	int tx_fifo;			/* TX fifo size*/
	unsigned int have_rtscts;
	unsigned int use_dcedte;
	unsigned int use_hwflow;
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	struct clk *clk_ipg;		/* clock id for UART clock */
	struct clk *clk_per;		/* clock id for UART clock */
	const struct imx_uart_data *devdata;
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	unsigned int uartclk;		/* base uart clock */
	struct rtdm_device rtdm_dev;	/* RTDM device structure */
};

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static struct imx_uart_data imx_uart_devdata[] = {
	[IMX1_UART] = {
		.uts_reg = IMX1_UTS,
		.devtype = IMX1_UART,
	},
	[IMX21_UART] = {
		.uts_reg = IMX21_UTS,
		.devtype = IMX21_UART,
	},
	[IMX53_UART] = {
		.uts_reg = IMX21_UTS,
		.devtype = IMX53_UART,
	},
	[IMX6Q_UART] = {
		.uts_reg = IMX21_UTS,
		.devtype = IMX6Q_UART,
	},
};

static const struct platform_device_id rt_imx_uart_id_table[] = {
	{
		.name = "imx1-uart",
		.driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
	}, {
		.name = "imx21-uart",
		.driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
	}, {
		.name = "imx53-uart",
		.driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
	}, {
		.name = "imx6q-uart",
		.driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, rt_imx_uart_id_table);

static const struct of_device_id rt_imx_uart_dt_ids[] = {
	{
		.compatible = "fsl,imx6q-uart",
		.data = &imx_uart_devdata[IMX6Q_UART], },
	{
		.compatible = "fsl,imx53-uart",
		.data = &imx_uart_devdata[IMX53_UART], },
	{
		.compatible = "fsl,imx1-uart",
		.data = &imx_uart_devdata[IMX1_UART], },
	{
		.compatible = "fsl,imx21-uart",
		.data = &imx_uart_devdata[IMX21_UART], },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rt_imx_uart_dt_ids);

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struct rt_imx_uart_ctx {
	struct rtser_config config;	/* current device configuration */

	rtdm_irq_t irq_handle;		/* device IRQ handle */
	rtdm_lock_t lock;		/* lock to protect context struct */

	int in_head;			/* RX ring buffer, head pointer */
	int in_tail;			/* RX ring buffer, tail pointer */
	size_t in_npend;		/* pending bytes in RX ring */
	int in_nwait;			/* bytes the user waits for */
	rtdm_event_t in_event;		/* raised to unblock reader */
	char in_buf[IN_BUFFER_SIZE];	/* RX ring buffer */
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	volatile unsigned long in_lock;	/* single-reader lock */
	uint64_t *in_history;		/* RX timestamp buffer */

	int out_head;			/* TX ring buffer, head pointer */
	int out_tail;			/* TX ring buffer, tail pointer */
	size_t out_npend;		/* pending bytes in TX ring */
	rtdm_event_t out_event;		/* raised to unblock writer */
	char out_buf[OUT_BUFFER_SIZE];	/* TX ring buffer */
	rtdm_mutex_t out_lock;		/* single-writer mutex */

	uint64_t last_timestamp;	/* timestamp of last event */
	int ioc_events;			/* recorded events */
	rtdm_event_t ioc_event;		/* raised to unblock event waiter */
	volatile unsigned long ioc_event_lock;	/* single-waiter lock */

	int ier_status;			/* IER cache */
	int mcr_status;			/* MCR cache */
	int status;			/* cache for LSR + soft-states */
	int saved_errors;		/* error cache for RTIOC_GET_STATUS */

	/*
	 * The port structure holds all the information about the UART
	 * port like base address, and so on.
	 */
	struct rt_imx_uart_port *port;
};

static const struct rtser_config default_config = {
	.config_mask = 0xFFFF,
	.baud_rate = RTSER_DEF_BAUD,
	.parity = RTSER_DEF_PARITY,
	.data_bits = RTSER_DEF_BITS,
	.stop_bits = RTSER_DEF_STOPB,
	.handshake = RTSER_DEF_HAND,
	.fifo_depth = RTSER_DEF_FIFO_DEPTH,
	.rx_timeout = RTSER_DEF_TIMEOUT,
	.tx_timeout = RTSER_DEF_TIMEOUT,
	.event_timeout = RTSER_DEF_TIMEOUT,
	.timestamp_history = RTSER_DEF_TIMESTAMP_HISTORY,
	.event_mask = RTSER_DEF_EVENT_MASK,
};

static void rt_imx_uart_stop_tx(struct rt_imx_uart_ctx *ctx)
{
	unsigned long temp;

	temp = readl(ctx->port->membase + UCR1);
	writel(temp & ~UCR1_TXMPTYEN, ctx->port->membase + UCR1);
}

static void rt_imx_uart_start_tx(struct rt_imx_uart_ctx *ctx)
{
	unsigned long temp;

	temp = readl(ctx->port->membase + UCR1);
	writel(temp | UCR1_TXMPTYEN, ctx->port->membase + UCR1);
}

static void rt_imx_uart_enable_ms(struct rt_imx_uart_ctx *ctx)
{
	unsigned long ucr3;

	/*
	 * RTS interrupt is enabled only if we are using interrupt-driven
	 * software controlled hardware flow control
	 */
	if (!ctx->port->use_hwflow) {
		unsigned long ucr1 = readl(ctx->port->membase + UCR1);

		ucr1 |= UCR1_RTSDEN;
		writel(ucr1, ctx->port->membase + UCR1);
	}
	ucr3 = readl(ctx->port->membase + UCR3);
	ucr3 |= UCR3_DTREN;
	if (ctx->port->use_dcedte) /* DTE mode */
		ucr3 |= UCR3_DCD | UCR3_RI;
	writel(ucr3, ctx->port->membase + UCR3);
}

static int rt_imx_uart_rx_chars(struct rt_imx_uart_ctx *ctx,
				uint64_t *timestamp)
{
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	unsigned int rx, temp;
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	int rbytes = 0;
	int lsr = 0;

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	while (readl(ctx->port->membase + USR2) & USR2_RDR) {
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		rx = readl(ctx->port->membase + URXD0);
		temp = readl(ctx->port->membase + USR2);
		if (temp & USR2_BRCD) {
			writel(USR2_BRCD, ctx->port->membase + USR2);
			lsr |= RTSER_LSR_BREAK_IND;
		}

		if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR)) {
			if (rx & URXD_PRERR)
				lsr |= RTSER_LSR_PARITY_ERR;
			else if (rx & URXD_FRMERR)
				lsr |= RTSER_LSR_FRAMING_ERR;
			if (rx & URXD_OVRRUN)
				lsr |= RTSER_LSR_OVERRUN_ERR;
		}

		/* save received character */
		ctx->in_buf[ctx->in_tail] = rx & 0xff;
		if (ctx->in_history)
			ctx->in_history[ctx->in_tail] = *timestamp;
		ctx->in_tail = (ctx->in_tail + 1) & (IN_BUFFER_SIZE - 1);

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		if (unlikely(ctx->in_npend >= IN_BUFFER_SIZE))
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			lsr |= RTSER_SOFT_OVERRUN_ERR;
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		else
			ctx->in_npend++;
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		rbytes++;
	}

	/* save new errors */
	ctx->status |= lsr;

	return rbytes;
}

static void rt_imx_uart_tx_chars(struct rt_imx_uart_ctx *ctx)
{
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	int ch;
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	unsigned int uts_reg = ctx->port->devdata->uts_reg;
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	while (ctx->out_npend > 0 &&
	       !(readl(ctx->port->membase + uts_reg) & UTS_TXFULL)) {
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		ch = ctx->out_buf[ctx->out_head++];
		writel(ch, ctx->port->membase + URTX0);
		ctx->out_head &= (OUT_BUFFER_SIZE - 1);
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		ctx->out_npend--;
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	}
}

static int rt_imx_uart_modem_status(struct rt_imx_uart_ctx *ctx,
				     unsigned int usr1,
				     unsigned int usr2)
{
	int events = 0;

	/* Clear the status bits that triggered the interrupt */
	writel(usr1, ctx->port->membase + USR1);
	writel(usr2, ctx->port->membase + USR2);

	if (ctx->port->use_dcedte) { /* DTE mode */
		if (usr2 & USR2_DCDDELT)
			events |= !(usr2 & USR2_DCDIN) ?
				RTSER_EVENT_MODEMHI : RTSER_EVENT_MODEMLO;
	}
	if (!ctx->port->use_hwflow && (usr1 & USR1_RTSD)) {
		events |= (usr1 & USR1_RTSS) ?
			RTSER_EVENT_MODEMHI : RTSER_EVENT_MODEMLO;
	}

	return events;
}

static int rt_imx_uart_int(rtdm_irq_t *irq_context)
{
	uint64_t timestamp = rtdm_clock_read();
	struct rt_imx_uart_ctx *ctx;
	unsigned int usr1, usr2, ucr1;
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	int rbytes = 0, events = 0;
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	int ret = RTDM_IRQ_NONE;

	ctx = rtdm_irq_get_arg(irq_context, struct rt_imx_uart_ctx);

	rtdm_lock_get(&ctx->lock);

	usr1 = readl(ctx->port->membase + USR1);
	usr2 = readl(ctx->port->membase + USR2);
	ucr1 = readl(ctx->port->membase + UCR1);

	/*
	 * Read if there is data available
	 */
	if (usr1 & USR1_RRDY) {
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		if (likely(ucr1 & UCR1_RRDYEN)) {
			rbytes = rt_imx_uart_rx_chars(ctx, &timestamp);
			events |= RTSER_EVENT_RXPEND;
		}
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		ret = RTDM_IRQ_HANDLED;
	}

	/*
	 * Send data if there is data to be sent
	 */
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	if (usr1 & USR1_TRDY) {
		if (likely(ucr1 & UCR1_TXMPTYEN))
			rt_imx_uart_tx_chars(ctx);
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		ret = RTDM_IRQ_HANDLED;
	}

	/*
	 * Handle modem status events
	 */
	if ((usr1 & (USR1_RTSD | USR1_DTRD)) ||
	    (usr2 & (USR2_DCDDELT | USR2_RIDELT))) {
		events |= rt_imx_uart_modem_status(ctx, usr1, usr2);
		ret = RTDM_IRQ_HANDLED;
	}

	if (ctx->in_nwait > 0) {
		if ((ctx->in_nwait <= rbytes) || ctx->status) {
			ctx->in_nwait = 0;
			rtdm_event_signal(&ctx->in_event);
		} else {
			ctx->in_nwait -= rbytes;
		}
	}

	if (ctx->status) {
		events |= RTSER_EVENT_ERRPEND;
#ifdef FIXME
		ctx->ier_status &= ~IER_STAT;
#endif
	}

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	if (events & ctx->config.event_mask) {
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		int old_events = ctx->ioc_events;

		ctx->last_timestamp = timestamp;
		ctx->ioc_events = events;

		if (!old_events)
			rtdm_event_signal(&ctx->ioc_event);
	}

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	if ((ctx->ier_status & IER_TX) && (ctx->out_npend == 0)) {
533 534 535 536 537 538 539 540
		rt_imx_uart_stop_tx(ctx);
		ctx->ier_status &= ~IER_TX;
		rtdm_event_signal(&ctx->out_event);
	}

	rtdm_lock_put(&ctx->lock);

	if (ret != RTDM_IRQ_HANDLED)
541
		pr_warn("%s: unhandled interrupt\n", __func__);
542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575
	return ret;
}

static unsigned int rt_imx_uart_get_msr(struct rt_imx_uart_ctx *ctx)
{
	unsigned long usr1 = readl(ctx->port->membase + USR1);
	unsigned long usr2 = readl(ctx->port->membase + USR2);
	unsigned int msr = 0;

	if (usr1 & USR1_RTSD)
		msr |= RTSER_MSR_DCTS;
	if (usr1 & USR1_DTRD)
		msr |= RTSER_MSR_DDSR;
	if (usr2 & USR2_RIDELT)
		msr |= RTSER_MSR_TERI;
	if (usr2 & USR2_DCDDELT)
		msr |= RTSER_MSR_DDCD;

	if (usr1 & USR1_RTSS)
		msr |= RTSER_MSR_CTS;

	if (ctx->port->use_dcedte) { /* DTE mode */
		if (!(usr2 & USR2_DCDIN))
			msr |= RTSER_MSR_DCD;
		if (!(usr2 & USR2_RIIN))
			msr |= RTSER_MSR_RI;
	}

	return msr;
}

static void rt_imx_uart_set_mcr(struct rt_imx_uart_ctx *ctx,
				unsigned int mcr)
{
576
	unsigned int uts_reg = ctx->port->devdata->uts_reg;
577 578
	unsigned long ucr2 = readl(ctx->port->membase + UCR2);
	unsigned long ucr3 = readl(ctx->port->membase + UCR3);
579
	unsigned long uts = readl(ctx->port->membase + uts_reg);
580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606

	if (mcr & RTSER_MCR_RTS) {
		/*
		 * Return to hardware-driven hardware flow control if the
		 * option is enabled
		 */
		if (ctx->port->use_hwflow) {
			ucr2 |= UCR2_CTSC;
		} else {
			ucr2 |= UCR2_CTS;
			ucr2 &= ~UCR2_CTSC;
		}
	} else {
		ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
	}
	writel(ucr2, ctx->port->membase + UCR2);

	if (mcr & RTSER_MCR_DTR)
		ucr3 |= UCR3_DSR;
	else
		ucr3 &= ~UCR3_DSR;
	writel(ucr3, ctx->port->membase + UCR3);

	if (mcr & RTSER_MCR_LOOP)
		uts |= UTS_LOOP;
	else
		uts &= ~UTS_LOOP;
607
	writel(uts, ctx->port->membase + uts_reg);
608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630
}

static void rt_imx_uart_break_ctl(struct rt_imx_uart_ctx *ctx,
				  int break_state)
{
	unsigned long ucr1 = readl(ctx->port->membase + UCR1);

	if (break_state == RTSER_BREAK_SET)
		ucr1 |= UCR1_SNDBRK;
	else
		ucr1 &= ~UCR1_SNDBRK;
	writel(ucr1, ctx->port->membase + UCR1);
}

static int rt_imx_uart_set_config(struct rt_imx_uart_ctx *ctx,
				  const struct rtser_config *config,
				  uint64_t **in_history_ptr)
{
	rtdm_lockctx_t lock_ctx;
	int err = 0;

	rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);

631
	if (config->config_mask & RTSER_SET_BAUD)
632
		ctx->config.baud_rate = config->baud_rate;
633
	if (config->config_mask & RTSER_SET_DATA_BITS)
634
		ctx->config.data_bits = config->data_bits & DATA_BITS_MASK;
635
	if (config->config_mask & RTSER_SET_PARITY)
636
		ctx->config.parity = config->parity & PARITY_MASK;
637
	if (config->config_mask & RTSER_SET_STOP_BITS)
638 639 640
		ctx->config.stop_bits = config->stop_bits & STOP_BITS_MASK;

	/* Timeout manipulation is not atomic. The user is supposed to take
641 642
	 * care not to use and change timeouts at the same time.
	 */
643
	if (config->config_mask & RTSER_SET_TIMEOUT_RX)
644
		ctx->config.rx_timeout = config->rx_timeout;
645
	if (config->config_mask & RTSER_SET_TIMEOUT_TX)
646
		ctx->config.tx_timeout = config->tx_timeout;
647
	if (config->config_mask & RTSER_SET_TIMEOUT_EVENT)
648 649
		ctx->config.event_timeout = config->event_timeout;

650 651
	if (config->config_mask & RTSER_SET_TIMESTAMP_HISTORY) {
		if (config->timestamp_history & RTSER_RX_TIMESTAMP_HISTORY) {
652 653 654 655 656 657 658 659 660 661 662 663
			if (!ctx->in_history) {
				ctx->in_history = *in_history_ptr;
				*in_history_ptr = NULL;
				if (!ctx->in_history)
					err = -ENOMEM;
			}
		} else {
			*in_history_ptr = ctx->in_history;
			ctx->in_history = NULL;
		}
	}

664
	if (config->config_mask & RTSER_SET_EVENT_MASK) {
665 666 667
		ctx->config.event_mask = config->event_mask & EVENT_MASK;
		ctx->ioc_events = 0;

668
		if ((config->event_mask & RTSER_EVENT_RXPEND) &&
669 670 671
		    (ctx->in_npend > 0))
			ctx->ioc_events |= RTSER_EVENT_RXPEND;

672
		if ((config->event_mask & RTSER_EVENT_ERRPEND)
673 674 675 676
		    && ctx->status)
			ctx->ioc_events |= RTSER_EVENT_ERRPEND;
	}

677
	if (config->config_mask & RTSER_SET_HANDSHAKE) {
678 679 680 681 682 683 684 685 686 687 688 689 690 691
		ctx->config.handshake = config->handshake;

		switch (ctx->config.handshake) {
		case RTSER_RTSCTS_HAND:
			/* ...? */

		default:	/* RTSER_NO_HAND */
			ctx->mcr_status = RTSER_MCR_RTS | RTSER_MCR_OUT1;
			break;
		}
		rt_imx_uart_set_mcr(ctx, ctx->mcr_status);
	}

	/* configure hardware with new parameters */
692 693 694 695 696 697
	if (config->config_mask & (RTSER_SET_BAUD |
				   RTSER_SET_PARITY |
				   RTSER_SET_DATA_BITS |
				   RTSER_SET_STOP_BITS |
				   RTSER_SET_EVENT_MASK |
				   RTSER_SET_HANDSHAKE)) {
698
		struct rt_imx_uart_port *port = ctx->port;
699
		unsigned int ucr2, old_ucr1, old_txrxen, old_ucr2;
700 701 702 703 704 705
		unsigned int baud = ctx->config.baud_rate;
		unsigned int div, ufcr;
		unsigned long num, denom;
		uint64_t tdiv64;

		if (ctx->config.data_bits == RTSER_8_BITS)
706
			ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
707
		else
708
			ucr2 = UCR2_SRST | UCR2_IRTS;
709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732

		if (ctx->config.handshake == RTSER_RTSCTS_HAND) {
			if (port->have_rtscts) {
				ucr2 &= ~UCR2_IRTS;
				ucr2 |= UCR2_CTSC;
			}
		}

		if (ctx->config.stop_bits == RTSER_2_STOPB)
			ucr2 |= UCR2_STPB;
		if (ctx->config.parity == RTSER_ODD_PARITY ||
		    ctx->config.parity == RTSER_EVEN_PARITY) {
			ucr2 |= UCR2_PREN;
			if (ctx->config.parity == RTSER_ODD_PARITY)
				ucr2 |= UCR2_PROE;
		}

		/*
		 * disable interrupts and drain transmitter
		 */
		old_ucr1 = readl(port->membase + UCR1);
		old_ucr1 &= ~UCR1_RTSDEN; /* reset in  rt_imx_uart_enable_ms()*/
		writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN),
		       port->membase + UCR1);
733 734
		old_ucr2 = readl(port->membase + USR2);
		writel(old_ucr2 & ~UCR2_ATEN, port->membase + USR2);
735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776
		while (!(readl(port->membase + USR2) & USR2_TXDC))
			barrier();

		/* then, disable everything */
		old_txrxen = readl(port->membase + UCR2);
		writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
		       port->membase + UCR2);
		old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
		div = port->uartclk / (baud * 16);
		if (div > 7)
			div = 7;
		if (!div)
			div = 1;

		rational_best_approximation(16 * div * baud, port->uartclk,
					    1 << 16, 1 << 16, &num, &denom);

		tdiv64 = port->uartclk;
		tdiv64 *= num;
		do_div(tdiv64, denom * 16 * div);

		num -= 1;
		denom -= 1;

		ufcr = readl(port->membase + UFCR);
		ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);

		if (port->use_dcedte)
			ufcr |= UFCR_DCEDTE;

		writel(ufcr, port->membase + UFCR);

		writel(num, port->membase + UBIR);
		writel(denom, port->membase + UBMR);

		writel(port->uartclk / div / 1000, port->membase + MX2_ONEMS);

		writel(old_ucr1, port->membase + UCR1);

		/* set the parity, stop bits and data size */
		writel(ucr2 | old_txrxen, port->membase + UCR2);

777 778
		if (config->event_mask &
		    (RTSER_EVENT_MODEMHI | RTSER_EVENT_MODEMLO))
779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809
			rt_imx_uart_enable_ms(ctx);

		ctx->status = 0;
		ctx->ioc_events &= ~RTSER_EVENT_ERRPEND;
	}

	rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);

	return err;
}

void rt_imx_uart_cleanup_ctx(struct rt_imx_uart_ctx *ctx)
{
	rtdm_event_destroy(&ctx->in_event);
	rtdm_event_destroy(&ctx->out_event);
	rtdm_event_destroy(&ctx->ioc_event);
	rtdm_mutex_destroy(&ctx->out_lock);
}

#define TXTL 2 /* reset default */
#define RXTL 1 /* reset default */

static int rt_imx_uart_setup_ufcr(struct rt_imx_uart_port *port)
{
	unsigned int val;
	unsigned int ufcr_rfdiv;

	/* set receiver / transmitter trigger level.
	 * RFDIV is set such way to satisfy requested uartclk value
	 */
	val = TXTL << 10 | RXTL;
810
	ufcr_rfdiv = (clk_get_rate(port->clk_per) + port->uartclk / 2) /
811 812 813 814 815 816 817 818 819 820 821 822 823 824 825
		port->uartclk;

	if (!ufcr_rfdiv)
		ufcr_rfdiv = 1;

	val |= UFCR_RFDIV_REG(ufcr_rfdiv);

	writel(val, port->membase + UFCR);

	return 0;
}

/* half the RX buffer size */
#define CTSTL 16

826 827 828 829 830 831 832 833 834 835 836 837 838 839 840
static void uart_reset(struct rt_imx_uart_port *port)
{
	unsigned int uts_reg = port->devdata->uts_reg;
	int n = 100;
	u32 temp;

	/* Reset fifo's and state machines */
	temp = readl(port->membase + UCR2);
	temp &= ~UCR2_SRST;
	writel(temp, port->membase + UCR2);
	n = 100;
	while (!(readl(port->membase + uts_reg) & UTS_SOFTRST) && --n > 0)
		udelay(1);
}

841
static int rt_imx_uart_open(struct rtdm_fd *fd, int oflags)
842 843 844 845 846 847 848
{
	struct rt_imx_uart_ctx *ctx;
	struct rt_imx_uart_port *port;
	rtdm_lockctx_t lock_ctx;
	unsigned long temp;
	uint64_t *dummy;

849 850
	ctx = rtdm_fd_to_private(fd);
	ctx->port = (struct rt_imx_uart_port *)rtdm_fd_device(fd)->device_data;
851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887

	port = ctx->port;

	/* IPC initialisation - cannot fail with used parameters */
	rtdm_lock_init(&ctx->lock);
	rtdm_event_init(&ctx->in_event, 0);
	rtdm_event_init(&ctx->out_event, 0);
	rtdm_event_init(&ctx->ioc_event, 0);
	rtdm_mutex_init(&ctx->out_lock);

	ctx->in_head = 0;
	ctx->in_tail = 0;
	ctx->in_npend = 0;
	ctx->in_nwait = 0;
	ctx->in_lock = 0;
	ctx->in_history = NULL;

	ctx->out_head = 0;
	ctx->out_tail = 0;
	ctx->out_npend = 0;

	ctx->ioc_events = 0;
	ctx->ioc_event_lock = 0;
	ctx->status = 0;
	ctx->saved_errors = 0;

	/*
	 * disable the DREN bit (Data Ready interrupt enable) before
	 * requesting IRQs
	 */
	temp = readl(port->membase + UCR4);

	/* set the trigger level for CTS */
	temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
	temp |= CTSTL << UCR4_CTSTL_SHF;
	writel(temp & ~UCR4_DREN, port->membase + UCR4);

888
	uart_reset(port);
889 890 891 892 893 894

	rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);

	/*
	 * Finally, clear status and enable interrupts
	 */
895 896
	writel(USR1_RTSD | USR1_DTRD, port->membase + USR1);
	writel(USR2_ORE, port->membase + USR2);
897

898 899 900 901
	temp = readl(port->membase + UCR1) & ~UCR1_RRDYEN;
	temp |= UCR1_UARTEN;
	if (port->have_rtscts)
		temp |= UCR1_RTSDEN;
902 903
	writel(temp, port->membase + UCR1);

904 905 906 907 908
	temp = readl(port->membase + UCR4);
	temp |= UCR4_OREN;
	writel(temp, port->membase + UCR4);

	temp = readl(port->membase + UCR2) & ~(UCR2_ATEN|UCR2_RTSEN);
909
	temp |= (UCR2_RXEN | UCR2_TXEN);
910 911
	if (!port->have_rtscts)
		temp |= UCR2_IRTS;
912 913 914 915 916 917
	writel(temp, port->membase + UCR2);

	temp = readl(port->membase + UCR3);
	temp |= MX2_UCR3_RXDMUXSEL;
	writel(temp, port->membase + UCR3);

918 919 920 921 922 923 924 925
	temp = readl(port->membase + UCR1);
	temp |= UCR1_RRDYEN;
	writel(temp, port->membase + UCR1);

	temp = readl(port->membase + UCR2);
	temp |= UCR2_ATEN;
	writel(temp, port->membase + UCR2);

926 927
	rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);

928 929 930 931 932 933 934
	rt_imx_uart_set_config(ctx, &default_config, &dummy);

	rt_imx_uart_setup_ufcr(port);

	return rtdm_irq_request(&ctx->irq_handle,
				port->irq, rt_imx_uart_int, 0,
				rtdm_fd_device(fd)->name, ctx);
935 936
}

937
void rt_imx_uart_close(struct rtdm_fd *fd)
938
{
939
	struct rt_imx_uart_port *port;
940 941 942 943
	struct rt_imx_uart_ctx *ctx;
	rtdm_lockctx_t lock_ctx;
	unsigned long temp;

944
	ctx = rtdm_fd_to_private(fd);
945
	port = ctx->port;
946 947 948

	rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);

949 950 951
	temp = readl(port->membase + UCR2);
	temp &= ~(UCR2_ATEN|UCR2_RTSEN|UCR2_RXEN|UCR2_TXEN|UCR2_IRTS);
	writel(temp, port->membase + UCR2);
952
	/*
953 954
	 * Disable all interrupts, port and break condition, then
	 * reset.
955
	 */
956
	temp = readl(port->membase + UCR1);
957
	temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
958
	writel(temp, port->membase + UCR1);
959 960 961 962 963

	rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);

	rtdm_irq_free(&ctx->irq_handle);

964 965 966 967
	uart_reset(port);

	rt_imx_uart_cleanup_ctx(ctx);
	kfree(ctx->in_history);
968 969
}

970
static int rt_imx_uart_ioctl(struct rtdm_fd *fd,
971 972 973 974 975 976
			     unsigned int request, void *arg)
{
	rtdm_lockctx_t lock_ctx;
	struct rt_imx_uart_ctx *ctx;
	int err = 0;

977
	ctx = rtdm_fd_to_private(fd);
978 979 980

	switch (request) {
	case RTSER_RTIOC_GET_CONFIG:
981
		if (rtdm_fd_is_user(fd))
982
			err =
983
			    rtdm_safe_copy_to_user(fd, arg,
984 985 986 987 988 989 990 991 992 993 994 995
						   &ctx->config,
						   sizeof(struct rtser_config));
		else
			memcpy(arg, &ctx->config,
			       sizeof(struct rtser_config));
		break;

	case RTSER_RTIOC_SET_CONFIG: {
		struct rtser_config *config;
		struct rtser_config config_buf;
		uint64_t *hist_buf = NULL;

996 997 998 999 1000 1001 1002
		/*
		 * We may call regular kernel services ahead, ask for
		 * re-entering secondary mode if need be.
		 */
		if (rtdm_in_rt_context())
			return -ENOSYS;

1003 1004
		config = (struct rtser_config *)arg;

1005
		if (rtdm_fd_is_user(fd)) {
1006
			err =
1007
			    rtdm_safe_copy_from_user(fd, &config_buf,
1008 1009 1010 1011 1012 1013 1014 1015 1016
						     arg,
						     sizeof(struct
							    rtser_config));
			if (err)
				return err;

			config = &config_buf;
		}

1017
		if ((config->config_mask & RTSER_SET_BAUD) &&
1018
		    (config->baud_rate > clk_get_rate(ctx->port->clk_per) / 16 ||
1019 1020 1021 1022
		     config->baud_rate <= 0))
			/* invalid baudrate for this port */
			return -EINVAL;

1023
		if (config->config_mask & RTSER_SET_TIMESTAMP_HISTORY) {
1024 1025
			if (config->timestamp_history &
						RTSER_RX_TIMESTAMP_HISTORY)
1026 1027 1028 1029 1030 1031 1032
				hist_buf = kmalloc(IN_BUFFER_SIZE *
						   sizeof(nanosecs_abs_t),
						   GFP_KERNEL);
		}

		rt_imx_uart_set_config(ctx, config, &hist_buf);

1033 1034
		if (hist_buf)
			kfree(hist_buf);
1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051
		break;
	}

	case RTSER_RTIOC_GET_STATUS: {
		int status, msr;

		rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);

		status = ctx->saved_errors | ctx->status;
		ctx->status = 0;
		ctx->saved_errors = 0;
		ctx->ioc_events &= ~RTSER_EVENT_ERRPEND;

		msr = rt_imx_uart_get_msr(ctx);

		rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);

1052
		if (rtdm_fd_is_user(fd)) {
1053 1054 1055 1056 1057 1058
			struct rtser_status status_buf;


			status_buf.line_status = status;
			status_buf.modem_status = msr;
			err =
1059
			    rtdm_safe_copy_to_user(fd, arg,
1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070
						   &status_buf,
						   sizeof(struct
							  rtser_status));
		} else {
			((struct rtser_status *)arg)->line_status = 0;
			((struct rtser_status *)arg)->modem_status = msr;
		}
		break;
	}

	case RTSER_RTIOC_GET_CONTROL:
1071
		if (rtdm_fd_is_user(fd))
1072
			err =
1073
			    rtdm_safe_copy_to_user(fd, arg,
1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107
						   &ctx->mcr_status,
						   sizeof(int));
		else
			*(int *)arg = ctx->mcr_status;

		break;

	case RTSER_RTIOC_SET_CONTROL: {
		int new_mcr = (long)arg;

		rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);
		ctx->mcr_status = new_mcr;
		rt_imx_uart_set_mcr(ctx, new_mcr);
		rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);
		break;
	}

	case RTSER_RTIOC_WAIT_EVENT: {
		struct rtser_event ev = { .rxpend_timestamp = 0 };
		rtdm_toseq_t timeout_seq;

		if (!rtdm_in_rt_context())
			return -ENOSYS;

		/* Only one waiter allowed, stop any further attempts here. */
		if (test_and_set_bit(0, &ctx->ioc_event_lock))
			return -EBUSY;

		rtdm_toseq_init(&timeout_seq, ctx->config.event_timeout);

		rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);

		while (!ctx->ioc_events) {
			/* Only enable error interrupt
1108 1109
			 * when the user waits for it.
			 */
1110
			if (ctx->config.event_mask & RTSER_EVENT_ERRPEND) {
1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144
				ctx->ier_status |= IER_STAT;
#ifdef FIXME
				rt_imx_uart_reg_out(mode, base, IER,
						 ctx->ier_status);
#endif
			}

			rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);

			err = rtdm_event_timedwait(&ctx->ioc_event,
						   ctx->config.event_timeout,
						   &timeout_seq);
			if (err) {
				/* Device has been closed? */
				if (err == -EIDRM)
					err = -EBADF;
				goto wait_unlock_out;
			}

			rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);
		}

		ev.events = ctx->ioc_events;
		ctx->ioc_events &=
		    ~(RTSER_EVENT_MODEMHI | RTSER_EVENT_MODEMLO);

		ev.last_timestamp = ctx->last_timestamp;
		ev.rx_pending = ctx->in_npend;

		if (ctx->in_history)
			ev.rxpend_timestamp = ctx->in_history[ctx->in_head];

		rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);

1145
		if (rtdm_fd_is_user(fd))
1146
			err =
1147
			    rtdm_safe_copy_to_user(fd, arg, &ev,
1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201
						   sizeof(struct
							  rtser_event));
			else
				memcpy(arg, &ev, sizeof(struct rtser_event));

wait_unlock_out:
		/* release the simple event waiter lock */
		clear_bit(0, &ctx->ioc_event_lock);
		break;
	}

	case RTSER_RTIOC_BREAK_CTL: {
		rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);
		rt_imx_uart_break_ctl(ctx, (int)arg);
		rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);
		break;
	}

#ifdef FIXME
	case RTIOC_PURGE: {
		int fcr = 0;

		rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);
		if ((long)arg & RTDM_PURGE_RX_BUFFER) {
			ctx->in_head = 0;
			ctx->in_tail = 0;
			ctx->in_npend = 0;
			ctx->status = 0;
			fcr |= FCR_FIFO | FCR_RESET_RX;
			rt_imx_uart_reg_in(mode, base, RHR);
		}
		if ((long)arg & RTDM_PURGE_TX_BUFFER) {
			ctx->out_head = 0;
			ctx->out_tail = 0;
			ctx->out_npend = 0;
			fcr |= FCR_FIFO | FCR_RESET_TX;
		}
		if (fcr) {
			rt_imx_uart_reg_out(mode, base, FCR, fcr);
			rt_imx_uart_reg_out(mode, base, FCR,
					 FCR_FIFO | ctx->config.fifo_depth);
		}
		rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);
		break;
	}
#endif

	default:
		err = -ENOTTY;
	}

	return err;
}

1202
ssize_t rt_imx_uart_read(struct rtdm_fd *fd, void *buf, size_t nbyte)
1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218
{
	struct rt_imx_uart_ctx *ctx;
	rtdm_lockctx_t lock_ctx;
	size_t read = 0;
	int pending;
	int block;
	int subblock;
	int in_pos;
	char *out_pos = (char *)buf;
	rtdm_toseq_t timeout_seq;
	ssize_t ret = -EAGAIN;	/* for non-blocking read */
	int nonblocking;

	if (nbyte == 0)
		return 0;

1219
	if (rtdm_fd_is_user(fd) && !rtdm_rw_user_ok(fd, buf, nbyte))
1220 1221
		return -EFAULT;

1222
	ctx = rtdm_fd_to_private(fd);
1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236

	rtdm_toseq_init(&timeout_seq, ctx->config.rx_timeout);

	/* non-blocking is handled separately here */
	nonblocking = (ctx->config.rx_timeout < 0);

	/* only one reader allowed, stop any further attempts here */
	if (test_and_set_bit(0, &ctx->in_lock))
		return -EBUSY;

	rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);

	while (1) {
		if (ctx->status) {
1237
			if (ctx->status & RTSER_LSR_BREAK_IND)
1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258
				ret = -EPIPE;
			else
				ret = -EIO;
			ctx->saved_errors = ctx->status &
			    (RTSER_LSR_OVERRUN_ERR | RTSER_LSR_PARITY_ERR |
			     RTSER_LSR_FRAMING_ERR | RTSER_SOFT_OVERRUN_ERR);
			ctx->status = 0;
			break;
		}

		pending = ctx->in_npend;

		if (pending > 0) {
			block = subblock = (pending <= nbyte) ? pending : nbyte;
			in_pos = ctx->in_head;

			rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);

			/* Do we have to wrap around the buffer end? */
			if (in_pos + subblock > IN_BUFFER_SIZE) {
				/* Treat the block between head and buffer end
1259 1260
				 * separately.
				 */
1261 1262
				subblock = IN_BUFFER_SIZE - in_pos;

1263
				if (rtdm_fd_is_user(fd)) {
1264
					if (rtdm_copy_to_user
1265
					    (fd, out_pos,
1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281
					     &ctx->in_buf[in_pos],
					     subblock) != 0) {
						ret = -EFAULT;
						goto break_unlocked;
					}
				} else
					memcpy(out_pos, &ctx->in_buf[in_pos],
					       subblock);

				read += subblock;
				out_pos += subblock;

				subblock = block - subblock;
				in_pos = 0;
			}

1282 1283
			if (rtdm_fd_is_user(fd)) {
				if (rtdm_copy_to_user(fd, out_pos,
1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311
						      &ctx->in_buf[in_pos],
						      subblock) != 0) {
					ret = -EFAULT;
					goto break_unlocked;
				}
			} else
				memcpy(out_pos, &ctx->in_buf[in_pos], subblock);

			read += subblock;
			out_pos += subblock;
			nbyte -= block;

			rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);

			ctx->in_head =
			    (ctx->in_head + block) & (IN_BUFFER_SIZE - 1);
			ctx->in_npend -= block;
			if (ctx->in_npend == 0)
				ctx->ioc_events &= ~RTSER_EVENT_RXPEND;

			if (nbyte == 0)
				break; /* All requested bytes read. */

			continue;
		}

		if (nonblocking)
			/* ret was set to EAGAIN in case of a real
1312 1313 1314
			 * non-blocking call or contains the error
			 * returned by rtdm_event_wait[_until]
			 */
1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326
			break;

		ctx->in_nwait = nbyte;

		rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);

		ret = rtdm_event_timedwait(&ctx->in_event,
					   ctx->config.rx_timeout,
					   &timeout_seq);
		if (ret < 0) {
			if (ret == -EIDRM) {
				/* Device has been closed -
1327 1328
				 * return immediately.
				 */
1329 1330 1331 1332 1333 1334 1335 1336
				return -EBADF;
			}

			rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);

			nonblocking = 1;
			if (ctx->in_npend > 0) {
				/* Final turn: collect pending bytes
1337 1338
				 * before exit.
				 */
1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355
				continue;
			}

			ctx->in_nwait = 0;
			break;
		}

		rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);
	}

	rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);

break_unlocked:
	/* Release the simple reader lock, */
	clear_bit(0, &ctx->in_lock);

	if ((read > 0) && ((ret == 0) || (ret == -EAGAIN) ||
1356
			   (ret == -ETIMEDOUT)))
1357 1358 1359 1360 1361
		ret = read;

	return ret;
}

1362 1363
static ssize_t rt_imx_uart_write(struct rtdm_fd *fd, const void *buf,
				size_t nbyte)
1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378
{
	struct rt_imx_uart_ctx *ctx;
	rtdm_lockctx_t lock_ctx;
	size_t written = 0;
	int free;
	int block;
	int subblock;
	int out_pos;
	char *in_pos = (char *)buf;
	rtdm_toseq_t timeout_seq;
	ssize_t ret;

	if (nbyte == 0)
		return 0;

1379
	if (rtdm_fd_is_user(fd) && !rtdm_read_user_ok(fd, buf, nbyte))
1380 1381
		return -EFAULT;

1382
	ctx = rtdm_fd_to_private(fd);
1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405

	rtdm_toseq_init(&timeout_seq, ctx->config.rx_timeout);

	/* Make write operation atomic. */
	ret = rtdm_mutex_timedlock(&ctx->out_lock, ctx->config.rx_timeout,
				   &timeout_seq);
	if (ret)
		return ret;

	while (nbyte > 0) {
		rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);

		free = OUT_BUFFER_SIZE - ctx->out_npend;

		if (free > 0) {
			block = subblock = (nbyte <= free) ? nbyte : free;
			out_pos = ctx->out_tail;

			rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);

			/* Do we have to wrap around the buffer end? */
			if (out_pos + subblock > OUT_BUFFER_SIZE) {
				/* Treat the block between head and buffer
1406 1407
				 * end separately.
				 */
1408 1409
				subblock = OUT_BUFFER_SIZE - out_pos;

1410
				if (rtdm_fd_is_user(fd)) {
1411
					if (rtdm_copy_from_user
1412
					    (fd,
1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428
					     &ctx->out_buf[out_pos],
					     in_pos, subblock) != 0) {
						ret = -EFAULT;
						break;
					}
				} else
					memcpy(&ctx->out_buf[out_pos], in_pos,
					       subblock);

				written += subblock;
				in_pos += subblock;

				subblock = block - subblock;
				out_pos = 0;
			}

1429
			if (rtdm_fd_is_user(fd)) {
1430
				if (rtdm_copy_from_user
1431
				    (fd, &ctx->out_buf[out_pos],
1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463
				     in_pos, subblock) != 0) {
					ret = -EFAULT;
					break;
				}
			} else
				memcpy(&ctx->out_buf[out_pos], in_pos, block);

			written += subblock;
			in_pos += subblock;
			nbyte -= block;

			rtdm_lock_get_irqsave(&ctx->lock, lock_ctx);

			ctx->out_tail =
			    (ctx->out_tail + block) & (OUT_BUFFER_SIZE - 1);
			ctx->out_npend += block;

			ctx->ier_status |= IER_TX;
			rt_imx_uart_start_tx(ctx);

			rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);
			continue;
		}

		rtdm_lock_put_irqrestore(&ctx->lock, lock_ctx);

		ret = rtdm_event_timedwait(&ctx->out_event,
					   ctx->config.tx_timeout,
					   &timeout_seq);
		if (ret < 0) {
			if (ret == -EIDRM) {
				/* Device has been closed -
1464 1465
				 * return immediately.
				 */
1466
				ret = -EBADF;
1467 1468 1469 1470 1471 1472 1473 1474
			}
			break;
		}
	}

	rtdm_mutex_unlock(&ctx->out_lock);

	if ((written > 0) && ((ret == 0) || (ret == -EAGAIN) ||
1475
			      (ret == -ETIMEDOUT)))
1476 1477 1478 1479 1480
		ret = written;

	return ret;
}

1481
static struct rtdm_driver imx_uart_driver = {
1482 1483 1484 1485 1486
	.profile_info		= RTDM_PROFILE_INFO(imx_uart,
						    RTDM_CLASS_SERIAL,
						    RTDM_SUBCLASS_16550A,
						    RTSER_PROFILE_VER),
	.device_count		= RT_IMX_UART_MAX,
1487 1488 1489
	.device_flags		= RTDM_NAMED_DEVICE | RTDM_EXCLUSIVE,
	.context_size		= sizeof(struct rt_imx_uart_ctx),
	.ops = {
1490
		.open		= rt_imx_uart_open,
1491
		.close		= rt_imx_uart_close,
1492 1493 1494 1495 1496 1497 1498
		.ioctl_rt	= rt_imx_uart_ioctl,
		.ioctl_nrt	= rt_imx_uart_ioctl,
		.read_rt	= rt_imx_uart_read,
		.write_rt	= rt_imx_uart_write,
	},
};

1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525

#ifdef CONFIG_OF

/*
 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
 * could successfully get all information from dt or a negative errno.
 */
static int rt_imx_uart_probe_dt(struct rt_imx_uart_port *port,
				struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	const struct of_device_id *of_id =
			of_match_device(rt_imx_uart_dt_ids, &pdev->dev);
	int ret;

	if (!np)
		/* no device tree device */
		return 1;

	ret = of_alias_get_id(np, "serial");
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
		return ret;
	}

	pdev->id = ret;

1526 1527
	if (of_get_property(np, "uart-has-rtscts", NULL) ||
	    of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560
		port->have_rtscts = 1;
	if (of_get_property(np, "fsl,irda-mode", NULL))
		dev_warn(&pdev->dev, "IRDA not yet supported\n");

	if (of_get_property(np, "fsl,dte-mode", NULL))
		port->use_dcedte = 1;

	port->devdata = of_id->data;

	return 0;
}
#else
static inline int rt_imx_uart_probe_dt(struct rt_imx_uart_port *port,
				       struct platform_device *pdev)
{
	return 1;
}
#endif

static void rt_imx_uart_probe_pdata(struct rt_imx_uart_port *port,
				    struct platform_device *pdev)
{
	struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);

	port->devdata = (struct imx_uart_data  *) pdev->id_entry->driver_data;

	if (!pdata)
		return;

	if (pdata->flags & IMXUART_HAVE_RTSCTS)
		port->have_rtscts = 1;
}

1561 1562 1563 1564 1565
static int rt_imx_uart_probe(struct platform_device *pdev)
{
	struct rtdm_device *dev;
	struct rt_imx_uart_port *port;
	struct resource *res;
1566
	int ret;
1567

1568
	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1569 1570 1571
	if (!port)
		return -ENOMEM;

1572 1573 1574 1575 1576 1577
	ret = rt_imx_uart_probe_dt(port, pdev);
	if (ret > 0)
		rt_imx_uart_probe_pdata(port, pdev);
	else if (ret < 0)
		return ret;

1578
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1579 1580
	if (!res)
		return -ENODEV;