Commit ab2a63b5 authored by Marek Vasut's avatar Marek Vasut

mxssb: Add support for generating DCD block

This patch adds support for generating DCD blocks. The DCD blocks can be
used to write values to memory or preconfigure the hardware or CPU.
Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
parent b04b919d
......@@ -35,7 +35,8 @@ These semantics and rules will be outlined now.
- Each line of the configuration file contains exactly one instruction.
- Every numeric value must be encoded in hexadecimal and in format 0xabcdef12 .
- The configuration file is a concatenation of blocks called "sections".
- The configuration file is a concatenation of blocks called "sections" and
optionally "DCD blocks" (see below).
- Each "section" is started by the "SECTION" instruction.
- The "SECTION" instruction has the following semantics:
......@@ -69,6 +70,11 @@ These semantics and rules will be outlined now.
of u32_IVT_entry_point.
- i.MX28-specific instruction!
LOAD DCD u32_address u32_DCD_block_ID
- Loads the DCD block with ID "u32_DCD_block_ID" onto address
"u32_address" and executes the contents of this DCD block
- i.MX28-specific instruction!
FILL u32_address u32_pattern u32_length
- Starts to write memory from addres "u32_address" with a pattern
specified by "u32_pattern". Writes exactly "u32_length" bytes of the
......@@ -96,6 +102,31 @@ These semantics and rules will be outlined now.
i.MX28, string_mode = USB/I2C/SPI2_FLASH/SPI3_FLASH/NAND_BCH
JTAG/SPI2_EEPROM/SD_SSP0/SD_SSP1
- An optional "DCD" blocks can be added at the begining of the configuration
file. Note that the DCD is only supported on i.MX28.
- The DCD blocks must be inserted before the first "section" in the
configuration file.
- The DCD block has the following semantics:
DCD u32_DCD_block_ID
- u32_DCD_block_ID :: The ID number of the DCD block, must match
the ID number used by "LOAD DCD" instruction.
- The DCD block must be followed by one of the following instructions. All
of the instructions operate either on 1, 2 or 4 bytes. This is selected by
the 'n' suffix of the instruction:
WRITE.n u32_address u32_value
- Write the "u32_value" to the "u32_address" address.
ORR.n u32_address u32_value
- Read the "u32_address", perform a bitwise-OR with the "u32_value" and
write the result back to "u32_address".
ANDC.n u32_address u32_value
- Read the "u32_address", perform a bitwise-AND with the complement of
"u32_value" and write the result back to "u32_address".
- If the verbose output from the BootROM is enabled by passing the "-v" option
to MXSSB, the BootROM will produce a letter on the Debug UART for each
instruction it started processing. Here is a mapping between the above
......
This diff is collapsed.
......@@ -87,6 +87,8 @@ struct sb_ivt_header {
};
#define SB_HAB_IVT_TAG 0xd1UL
#define SB_HAB_DCD_TAG 0xd2UL
#define SB_HAB_VERSION 0x40UL
/*
......
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