Commit f5c5ef4a authored by wdenk's avatar wdenk

Add support for TQM8560 board

parent 3dd7f0f0
......@@ -2,6 +2,8 @@
Changes for U-Boot 1.1.3:
======================================================================
* Add support for TQM8560 board
* Add FEC support for TQM8540 board.
Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC
......
......@@ -1211,6 +1211,9 @@ stxgp3_config: unconfig
TQM8540_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx tqm8540
TQM8560_config: unconfig
@./mkconfig $(@:_config=) ppc mpc85xx tqm8560
#########################################################################
## 74xx/7xx Systems
#########################################################################
......
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o
SOBJS := init.o
#SOBJS :=
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################
# Copyright 2004 Freescale Semiconductor.
# Modified by Xianghua Xiao, X.Xiao@motorola.com
# (C) Copyright 2002,Motorola Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# tqm8560 board
# default CCARBAR is at 0xff700000
# assume U-Boot is less than 256k
#
TEXT_BASE = 0xfffc0000
/*
* Copyright 2004 Freescale Semiconductor.
* Copyright (C) 2002,2003, Motorola Inc.
* Xianghua Xiao <X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <config.h>
#include <mpc85xx.h>
/*
* TLB0 and TLB1 Entries
*
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
* these TLB entries are established.
*
* The TLB entries for DDR are dynamically setup in spd_sdram()
* and use TLB1 Entries 8 through 15 as needed according to the
* size of DDR memory.
*
* MAS0: tlbsel, esel, nv
* MAS1: valid, iprot, tid, ts, tsize
* MAS2: epn, sharen, x0, x1, w, i, m, g, e
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
*/
#define entry_start \
mflr r1 ; \
bl 0f ;
#define entry_end \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
.section .bootpg, "ax"
.globl tlb1_entry
tlb1_entry:
entry_start
/*
* Number of TLB0 and TLB1 entries in the following table
*/
.long 13
/*
* TLB0 16K Cacheable, non-guarded
* 0xd001_0000 16K Temporary Global data for initialization
*
* Use four 4K TLB0 entries. These entries must be cacheable
* as they provide the bootstrap memory before the memory
* controler and real memory have been configured.
*
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
* and must not collide with other TLB0 entries.
*/
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 0, 1: 32M Non-cacheable, guarded
* 0xfe000000 32M FLASH
* Out of reset this entry is only 4K.
*/
.long TLB1_MAS0(1, 1, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 0, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 2: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
.long TLB1_MAS0(1, 2, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 3: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
.long TLB1_MAS0(1, 3, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 4: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
.long TLB1_MAS0(1, 4, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
* TLB 5: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
.long TLB1_MAS0(1, 5, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
0,0,0,0,0,1,0,1,0,1)
/*
* TLB 6: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 16M PCI1 IO
*/
.long TLB1_MAS0(1, 6, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
#if !defined(CONFIG_SPD_EEPROM)
/*
* TLB 7: 256M DDR
* 0x00000000 256M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
.long TLB1_MAS0(1, 7, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(1, 8, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
#endif
entry_end
/*
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xf800_0000 0xf80f_ffff BCSR 1M
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
#else
#define LAWBAR0 0
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#endif
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
/*
* Rapid IO at 0xc000_0000 for 512 M
*/
#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
.section .bootpg, "ax"
.globl law_entry
law_entry:
entry_start
.long 0x05
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
.long LAWBAR4,LAWAR4
entry_end
This diff is collapsed.
/*
* (C) Copyright 2002,2003, Motorola,Inc.
* Xianghua Xiao, X.Xiao@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/mpc85xx/start.o (.bootpg)
board/tqm8560/init.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/mpc85xx/start.o (.text)
board/tqm8560/init.o (.text)
cpu/mpc85xx/traps.o (.text)
cpu/mpc85xx/interrupts.o (.text)
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
......@@ -47,7 +47,6 @@
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
/*
* sysclk for MPC85xx
*
......@@ -66,7 +65,6 @@
#define CONFIG_SYS_CLK_FREQ 33000000
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
......@@ -80,16 +78,14 @@
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
#define CFG_MEMTEST_END 0x10000000
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
/*
* DDR Setup
*/
......@@ -116,7 +112,6 @@
#define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
#endif
/*
* Flash on the Local Bus
*/
......@@ -339,8 +334,8 @@
#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
ADD_PCI_CMD | \
CFG_CMD_PING | \
CFG_CMD_I2C )
CFG_CMD_I2C | \
CFG_CMD_PING )
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
......
This diff is collapsed.
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