Commit 6402887a authored by Tom Rini's avatar Tom Rini

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh

- Assorted pinctrl updates
parents 12e39630 46f3282b
......@@ -8,6 +8,7 @@ config R8A774A1
config R8A774B1
bool "Renesas SoC R8A774B1"
imply CLK_R8A774B1
imply PINCTRL_PFC_R8A774B1
config R8A774C0
bool "Renesas SoC R8A774C0"
......@@ -16,6 +17,7 @@ config R8A774C0
config R8A774E1
bool "Renesas SoC R8A774E1"
imply CLK_R8A774E1
imply PINCTRL_PFC_R8A774E1
config R8A7795
bool "Renesas SoC R8A7795"
......
......@@ -67,6 +67,26 @@ config PINCTRL_PFC_R8A774A1
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A774B1
bool "Renesas RZ/G2 R8A774B1 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RZ/G2N R8A774B1 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A774E1
bool "Renesas RZ/G2 R8A774E1 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A7795
bool "Renesas RCar Gen3 R8A7795 pin control driver"
depends on PINCTRL_PFC
......
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
......
This diff is collapsed.
......@@ -1841,6 +1841,7 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
/* - DRIF0 --------------------------------------------------------------- */
static const unsigned int drif0_ctrl_a_pins[] = {
/* CLK, SYNC */
......@@ -2055,6 +2056,7 @@ static const unsigned int drif3_data1_b_pins[] = {
static const unsigned int drif3_data1_b_mux[] = {
RIF3_D1_B_MARK,
};
#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
/* - DU --------------------------------------------------------------------- */
static const unsigned int du_rgb666_pins[] = {
......@@ -4113,7 +4115,9 @@ static const unsigned int vin5_clk_mux[] = {
static const struct {
struct sh_pfc_pin_group common[312];
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
struct sh_pfc_pin_group automotive[30];
#endif
} pinmux_groups = {
.common = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
......@@ -4429,6 +4433,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin5_clkenb),
SH_PFC_PIN_GROUP(vin5_clk),
},
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
.automotive = {
SH_PFC_PIN_GROUP(drif0_ctrl_a),
SH_PFC_PIN_GROUP(drif0_data0_a),
......@@ -4461,6 +4466,7 @@ static const struct {
SH_PFC_PIN_GROUP(drif3_data0_b),
SH_PFC_PIN_GROUP(drif3_data1_b),
}
#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
};
static const char * const audio_clk_groups[] = {
......@@ -4519,6 +4525,7 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
static const char * const drif0_groups[] = {
"drif0_ctrl_a",
"drif0_data0_a",
......@@ -4560,6 +4567,7 @@ static const char * const drif3_groups[] = {
"drif3_data0_b",
"drif3_data1_b",
};
#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
static const char * const du_groups[] = {
"du_rgb666",
......@@ -4966,7 +4974,9 @@ static const char * const vin5_groups[] = {
static const struct {
struct sh_pfc_function common[49];
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
struct sh_pfc_function automotive[4];
#endif
} pinmux_functions = {
.common = {
SH_PFC_FUNCTION(audio_clk),
......@@ -5019,12 +5029,14 @@ static const struct {
SH_PFC_FUNCTION(vin4),
SH_PFC_FUNCTION(vin5),
},
#if defined(CONFIG_PINCTRL_PFC_R8A7796)
.automotive = {
SH_PFC_FUNCTION(drif0),
SH_PFC_FUNCTION(drif1),
SH_PFC_FUNCTION(drif2),
SH_PFC_FUNCTION(drif3),
}
#endif /* CONFIG_PINCTRL_PFC_R8A7796 */
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
......
This diff is collapsed.
......@@ -33,6 +33,8 @@ enum sh_pfc_model {
SH_PFC_R8A7795,
SH_PFC_R8A7796,
SH_PFC_R8A774A1,
SH_PFC_R8A774B1,
SH_PFC_R8A774E1,
SH_PFC_R8A77965,
SH_PFC_R8A77970,
SH_PFC_R8A77980,
......@@ -48,10 +50,6 @@ struct sh_pfc_pinctrl {
struct sh_pfc *pfc;
struct sh_pfc_pin_config *configs;
const char *func_prop_name;
const char *groups_prop_name;
const char *pins_prop_name;
};
struct sh_pfc_pin_range {
......@@ -858,6 +856,14 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
if (model == SH_PFC_R8A774A1)
priv->pfc.info = &r8a774a1_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A774B1
if (model == SH_PFC_R8A774B1)
priv->pfc.info = &r8a774b1_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
if (model == SH_PFC_R8A774E1)
priv->pfc.info = &r8a774e1_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77965
if (model == SH_PFC_R8A77965)
priv->pfc.info = &r8a77965_pinmux_info;
......@@ -935,6 +941,18 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = {
.data = SH_PFC_R8A774A1,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A774B1
{
.compatible = "renesas,pfc-r8a774b1",
.data = SH_PFC_R8A774B1,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A774E1
{
.compatible = "renesas,pfc-r8a774e1",
.data = SH_PFC_R8A774E1,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77965
{
.compatible = "renesas,pfc-r8a77965",
......
......@@ -294,6 +294,8 @@ sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *bit);
extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
......
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