Commit 6760cef3 authored by Tom Rini's avatar Tom Rini

Merge branch '2019-05-24-master-imports'

- Import Angelo's series to add basic DT support to m68k
parents 40920bde 196afe62
......@@ -28,6 +28,7 @@ config M68K
select HAVE_PRIVATE_LIBGCC
select SYS_BOOT_GET_CMDLINE
select SYS_BOOT_GET_KBD
select SUPPORT_OF_CONTROL
config MICROBLAZE
bool "MicroBlaze architecture"
......
......@@ -6,36 +6,69 @@ config SYS_ARCH
# processor family
config MCF520x
select OF_CONTROL
select DM
select DM_SERIAL
bool
config MCF52x2
select OF_CONTROL
select DM
select DM_SERIAL
bool
config MCF523x
select OF_CONTROL
select DM
select DM_SERIAL
bool
config MCF530x
select OF_CONTROL
select DM
select DM_SERIAL
bool
config MCF5301x
select OF_CONTROL
select DM
select DM_SERIAL
bool
config MCF532x
select OF_CONTROL
select DM
select DM_SERIAL
bool
config MCF537x
select OF_CONTROL
select DM
select DM_SERIAL
bool
config MCF5441x
select OF_CONTROL
select DM
select DM_SERIAL
bool
config MCF5445x
select OF_CONTROL
select DM
select DM_SERIAL
bool
config MCF5227x
select OF_CONTROL
select DM
select DM_SERIAL
bool
config MCF547x_8x
select OF_CONTROL
select DM
select DM_SERIAL
bool
# processor type
......
......@@ -6,4 +6,4 @@
# ccflags-y += -DET_DEBUG
extra-y = start.o
obj-y = cpu.o speed.o cpu_init.o interrupts.o
obj-y = cpu.o speed.o cpu_init.o interrupts.o dspi.o
......@@ -16,6 +16,15 @@
#include <asm/rtc.h>
#include <linux/compiler.h>
void cfspi_port_conf(void)
{
gpio_t *gpio = (gpio_t *)MMAP_GPIO;
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
}
/*
* Breath some life into the CPU...
*
......@@ -93,6 +102,8 @@ void cpu_init_f(void)
#endif
icache_enable();
cfspi_port_conf();
}
/*
......@@ -137,57 +148,3 @@ void uart_port_conf(int port)
break;
}
}
#ifdef CONFIG_CF_DSPI
void cfspi_port_conf(void)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
}
int cfspi_claim_bus(uint bus, uint cs)
{
dspi_t *dspi = (dspi_t *) MMAP_DSPI;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
return -1;
/* Clear FIFO and resume transfer */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 2:
clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
break;
}
return 0;
}
void cfspi_release_bus(uint bus, uint cs)
{
dspi_t *dspi = (dspi_t *) MMAP_DSPI;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Clear FIFO */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 2:
clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
break;
}
}
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019
* Angelo Dureghello <angleo@sysam.it>
*
* CPU specific dspi routines
*/
#include <common.h>
#include <asm/immap.h>
#include <asm/io.h>
#ifdef CONFIG_CF_DSPI
void dspi_chip_select(int cs)
{
struct gpio *gpio = (struct gpio *)MMAP_GPIO;
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 2:
clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
break;
}
}
void dspi_chip_unselect(int cs)
{
struct gpio *gpio = (struct gpio *)MMAP_GPIO;
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 2:
clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
break;
}
}
#endif /* CONFIG_CF_DSPI */
......@@ -378,7 +378,8 @@ _start:
clr.l %sp@-
/* run low-level board init code (from flash) */
bsr board_init_f
move.l #board_init_f, %a1
jsr (%a1)
/* board_init_f() does not return */
......
......@@ -6,4 +6,4 @@
# ccflags-y += -DET_DEBUG
extra-y = start.o
obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o
obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o dspi.o
......@@ -66,6 +66,32 @@ void init_fbcs(void)
#endif
}
#ifdef CONFIG_CF_DSPI
void cfspi_port_conf(void)
{
gpio_t *gpio = (gpio_t *)MMAP_GPIO;
#ifdef CONFIG_MCF5445x
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN |
GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
#endif
#ifdef CONFIG_MCF5441x
pm_t *pm = (pm_t *)MMAP_PM;
out_8(&gpio->par_dspi0,
GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
GPIO_PAR_DSPI0_SCK_DSPI0SCK);
out_8(&gpio->srcr_dspiow, 3);
/* DSPI0 */
out_8(&pm->pmcr0, 23);
#endif
}
#endif
/*
* Breath some life into the CPU...
*
......@@ -204,6 +230,10 @@ void cpu_init_f(void)
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
#ifdef CONFIG_CF_SPI
cfspi_port_conf();
#endif
#ifdef CONFIG_SYS_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
......@@ -433,115 +463,3 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
}
#endif
#ifdef CONFIG_CF_DSPI
void cfspi_port_conf(void)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
#ifdef CONFIG_MCF5445x
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN |
GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
#endif
#ifdef CONFIG_MCF5441x
pm_t *pm = (pm_t *) MMAP_PM;
out_8(&gpio->par_dspi0,
GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
GPIO_PAR_DSPI0_SCK_DSPI0SCK);
out_8(&gpio->srcr_dspiow, 3);
/* DSPI0 */
out_8(&pm->pmcr0, 23);
#endif
}
int cfspi_claim_bus(uint bus, uint cs)
{
dspi_t *dspi = (dspi_t *) MMAP_DSPI;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
return -1;
/* Clear FIFO and resume transfer */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 1:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
break;
case 2:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
break;
case 3:
clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
break;
case 5:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
#endif
#ifdef CONFIG_MCF5441x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
break;
case 1:
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
break;
}
#endif
return 0;
}
void cfspi_release_bus(uint bus, uint cs)
{
dspi_t *dspi = (dspi_t *) MMAP_DSPI;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Clear FIFO */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 1:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
break;
case 2:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
break;
case 3:
clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
break;
case 5:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
#endif
#ifdef CONFIG_MCF5441x
if (cs == 1)
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
#endif
}
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019
* Angelo Dureghello <angleo@sysam.it>
*
* CPU specific dspi routines
*/
#include <common.h>
#include <asm/immap.h>
#include <asm/io.h>
#ifdef CONFIG_CF_DSPI
void dspi_chip_select(int cs)
{
struct gpio *gpio = (struct gpio *)MMAP_GPIO;
#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 1:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
break;
case 2:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
break;
case 3:
clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
break;
case 5:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
#endif
#ifdef CONFIG_MCF5441x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi0,
~GPIO_PAR_DSPI0_PCS0_MASK);
setbits_8(&gpio->par_dspi0,
GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
break;
case 1:
clrbits_8(&gpio->par_dspiow,
GPIO_PAR_DSPIOW_DSPI0PSC1);
setbits_8(&gpio->par_dspiow,
GPIO_PAR_DSPIOW_DSPI0PSC1);
break;
}
#endif
}
void dspi_chip_unselect(int cs)
{
struct gpio *gpio = (struct gpio *)MMAP_GPIO;
#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 1:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
break;
case 2:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
break;
case 3:
clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
break;
case 5:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
#endif
#ifdef CONFIG_MCF5441x
if (cs == 1)
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
#endif
}
#endif /* CONFIG_CF_DSPI */
......@@ -131,7 +131,8 @@ _start:
* then (and always) gd struct space will be reserved
*/
move.l %sp, -(%sp)
bsr board_init_f_alloc_reserve
move.l #board_init_f_alloc_reserve, %a1
jsr (%a1)
/* update stack and frame-pointers */
move.l %d0, %sp
......@@ -139,7 +140,8 @@ _start:
/* initialize reserved area */
move.l %d0, -(%sp)
bsr board_init_f_init_reserve
move.l #board_init_f_init_reserve, %a1
jsr (%a1)
/* run low-level CPU init code (from flash) */
jbsr cpu_init_f
......
......@@ -68,13 +68,15 @@ SECTIONS
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
. = ALIGN(4);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
. = ALIGN(4);
__init_end = .;
_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf5208.dtsi"
/ {
model = "Freescale M5208EVBE";
compatible = "fsl,M5208EVBE";
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
};
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf5227x.dtsi"
/ {
model = "Freescale M52277EVB";
compatible = "fsl,M52277EVB";
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&dspi0 {
status = "okay";
};
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf5227x.dtsi"
/ {
model = "Freescale M52277_stmicro";
compatible = "fsl,M52277_stmicro";
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
u-boot,dm-pre-reloc;
status = "okay";
};
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
*/
/dts-v1/;
/include/ "mcf523x.dtsi"
/ {
model = "Freescale M5235EVB";
compatible = "fsl,M5235EVB";
chosen {
stdout-path = "serial0:115200n8";
};