Commit afe9e1f1 authored by Tom Rini's avatar Tom Rini

Merge git://git.denx.de/u-boot-mpc85xx

- Enable DM for SATA, SDHC, USB in T2080QDS
parents 6760cef3 02dc1599
......@@ -352,7 +352,6 @@ config TARGET_T2080QDS
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
imply CMD_SATA
config TARGET_T2080RDB
bool "Support T2080RDB"
......@@ -361,6 +360,7 @@ config TARGET_T2080RDB
select SUPPORT_SPL
select PHYS_64BIT
imply CMD_SATA
imply FSL_SATA
imply PANIC_HANG
config TARGET_T2081QDS
......@@ -1081,10 +1081,8 @@ config ARCH_T2080
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
imply CMD_NAND
imply CMD_REGINFO
imply FSL_SATA
config ARCH_T2081
bool
......
......@@ -58,5 +58,50 @@
device_type = "open-pic";
clock-frequency = <0x0>;
};
esdhc: esdhc@114000 {
compatible = "fsl,esdhc";
reg = <0x114000 0x1000>;
interrupts = <48 2 0 0>;
clock-frequency = <0>;
sdhci,auto-cmd12;
bus-width = <4>;
voltage-ranges = <1800 1800 3300 3300>;
};
usb0: usb@210000 {
compatible = "fsl-usb2-mph";
reg = <0x210000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <44 0x2 0 0>;
phy_type = "utmi";
};
usb1: usb@211000 {
compatible = "fsl-usb2-dr";
reg = <0x211000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <45 0x2 0 0>;
dr_mode = "host";
phy_type = "utmi";
};
sata0: sata@220000 {
compatible = "fsl,pq-sata-v2";
reg = <0x220000 0x1000>;
interrupts = <68 0x2 0 0>;
sata-number = <0x0>;
sata-fpdma = <0x0>;
};
sata1: sata@221000 {
compatible = "fsl,pq-sata-v2";
reg = <0x221000 0x1000>;
interrupts = <69 0x2 0 0>;
sata-number = <0x0>;
sata-fpdma = <0x0>;
};
};
};
......@@ -7,6 +7,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
......@@ -39,7 +40,10 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
......@@ -57,8 +61,11 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
......@@ -8,6 +8,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
......@@ -39,7 +40,10 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
......@@ -56,8 +60,11 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
......@@ -3,6 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
......@@ -26,7 +28,11 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_DM=y
CONFIG_FSL_AHCI=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
......@@ -43,12 +49,14 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y
......@@ -9,6 +9,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
......@@ -40,7 +41,10 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
......@@ -57,8 +61,11 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
......@@ -2,6 +2,8 @@ CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
......@@ -22,8 +24,13 @@ CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_REMOTE=y
CONFIG_DM=y
CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
......@@ -35,9 +42,11 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
......@@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
......@@ -28,7 +29,10 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),9
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
CONFIG_FSL_AHCI=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
......@@ -45,8 +49,11 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
......@@ -59,6 +59,16 @@ config DWC_AHCI
Enable this driver to support Sata devices through
Synopsys DWC AHCI module.
config FSL_AHCI
bool "Enable Freescale AHCI driver support"
select SCSI_AHCI
depends on AHCI
depends on DM_SCSI
help
Enable this driver to support Sata devices found in
some Freescale PowerPC SoCs.
config DWC_AHSATA
bool "Enable DWC AHSATA driver support"
select LIBATA
......
......@@ -4,6 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o
obj-$(CONFIG_FSL_AHCI) += fsl_ahci.o
obj-$(CONFIG_AHCI) += ahci-uclass.o
obj-$(CONFIG_AHCI_PCI) += ahci-pci.o
obj-$(CONFIG_SCSI_AHCI) += ahci.o
......
This diff is collapsed.
......@@ -312,6 +312,7 @@ typedef struct fsl_sata {
int wcache;
int flush;
int flush_ext;
u32 dma_flag;
} fsl_sata_t;
#define READ_CMD 0
......
......@@ -1435,7 +1435,9 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
#endif
#if CONFIG_IS_ENABLED(DM_MMC)
#ifndef CONFIG_PPC
#include <asm/arch/clock.h>
#endif
__weak void init_clk_usdhc(u32 index)
{
}
......@@ -1460,8 +1462,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
#ifdef CONFIG_PPC
priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
#else
priv->esdhc_regs = (struct fsl_esdhc *)addr;
#endif
priv->dev = dev;
priv->mode = -1;
if (data) {
......@@ -1568,7 +1573,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->sdhc_clk = clk_get_rate(&priv->per_clk);
} else {
#ifndef CONFIG_PPC
priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
#else
priv->sdhc_clk = gd->arch.sdhc_clk;
#endif
if (priv->sdhc_clk <= 0) {
dev_err(dev, "Unable to get clk for %s\n", dev->name);
return -EINVAL;
......
......@@ -75,8 +75,12 @@ static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
struct usb_ehci *ehci = NULL;
struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
ehci);
#ifdef CONFIG_PPC
ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
#else
ehci = (struct usb_ehci *)priv->hcd_base;
#endif
if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
return -ENXIO;
......@@ -103,7 +107,11 @@ static int ehci_fsl_probe(struct udevice *dev)
debug("Can't get the EHCI register base address\n");
return -ENXIO;
}
#ifdef CONFIG_PPC
ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
#else
ehci = (struct usb_ehci *)priv->hcd_base;
#endif
hccr = (struct ehci_hccr *)(&ehci->caplength);
hcor = (struct ehci_hcor *)
((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
......
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