Commit c18b1036 authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-sh

- Gen3 PCIe driver + enablement on Salvator-X platforms.
- Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon.
- SDHI HS400 fixes ported from latest BSP and datasheet.
parents 696f02d9 b5900a58
......@@ -155,6 +155,7 @@ config SYS_MALLOC_LEN
config SPL_SYS_MALLOC_F_LEN
hex "Size of malloc() pool in SPL before relocation"
depends on SYS_MALLOC_F
default 0x2800 if RCAR_GEN3
default SYS_MALLOC_F_LEN
help
Before relocation, memory is very limited on many platforms. Still,
......
......@@ -1117,6 +1117,9 @@ OBJCOPYFLAGS_u-boot-spl.srec = $(OBJCOPYFLAGS_u-boot.srec)
spl/u-boot-spl.srec: spl/u-boot-spl FORCE
$(call if_changed,objcopy)
%.scif: %.srec
$(Q)$(MAKE) $(build)=arch/arm/mach-rmobile $@
OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec)
......
......@@ -16,11 +16,22 @@ config RCAR_GEN3
select PINCTRL
select PINCONF
select PINCTRL_PFC
select SUPPORT_SPL
imply CMD_FS_UUID
imply CMD_GPT
imply CMD_UUID
imply CMD_MMC_SWRITE if MMC
imply SUPPORT_EMMC_RPMB if MMC
imply SPL
imply SPL_BOARD_INIT
imply SPL_GZIP
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_SERIAL_SUPPORT
imply SPL_SYS_MALLOC_SIMPLE
imply SPL_TINY_MEMSET
imply SPL_YMODEM_SUPPORT
imply USE_TINY_PRINTF
config RZA1
prompt "Renesas ARM SoCs RZ/A1 (32bit)"
......
......@@ -13,3 +13,76 @@ obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
OBJCOPYFLAGS_u-boot-spl.srec := -O srec
quiet_cmd_objcopy = OBJCOPY $@
cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \
$(OBJCOPYFLAGS_$(@F)) $< $@
spl/u-boot-spl.srec: spl/u-boot-spl FORCE
$(call if_changed,objcopy)
ifneq ($(CONFIG_R8A77990)$(CONFIG_R8A77995),)
#
# The first 6 generate statements generate the R-Car Gen3 SCIF loader header.
# The subsequent generate statements represent the following chunk of assembler
# code, which copies the loaded data from 0xe6304030 to 0xe6318000. This is to
# work around a limitation of the D3/E3 BootROM, which does not permit loading
# to 0xe6318000 directly.
#
# mov x0, #0xe6000000
# orr x0, x0, #0x00300000
# orr x1, x0, #0x00004000
# orr x1, x1, #0x00000030
#
# orr x2, x0, #0x00018000
# mov x0, x2
# mov x3, #0x7000
#1: ldp x4, x5, [x1], #16
#
# stp x4, x5, [x2], #16
# subs x3, x3, #16
# b.ge 1b
# br x0
#
quiet_cmd_srec_cat = SRECCAT $@
cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
-offset -0x13fd0 \
-Output_Block_Size 16 \
-generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \
-generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \
-generate 0xe63005d4 0xe63005d8 -l-e-constant 0xe6304000 4 \
-generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \
-generate 0xe6301154 0xe6301158 -l-e-constant 0xe6304000 4 \
-generate 0xe6301264 0xe6301268 -l-e-constant $2 4 \
-generate 0xe6304000 0xe6304004 -l-e-constant 0xd2bcc000 4 \
-generate 0xe6304004 0xe6304008 -l-e-constant 0xb26c0400 4 \
-generate 0xe6304008 0xe630400c -l-e-constant 0xb2720001 4 \
-generate 0xe630400c 0xe6304010 -l-e-constant 0xb27c0421 4 \
-generate 0xe6304010 0xe6304014 -l-e-constant 0xb2710402 4 \
-generate 0xe6304014 0xe6304018 -l-e-constant 0xaa0203e0 4 \
-generate 0xe6304018 0xe630401c -l-e-constant 0xd28e0003 4 \
-generate 0xe630401c 0xe6304020 -l-e-constant 0xa8c11424 4 \
-generate 0xe6304020 0xe6304024 -l-e-constant 0xa8811444 4 \
-generate 0xe6304024 0xe6304028 -l-e-constant 0xf1004063 4 \
-generate 0xe6304028 0xe630402c -l-e-constant 0x54ffffaa 4 \
-generate 0xe630402c 0xe6304030 -l-e-constant 0xd61f0000 4
else
quiet_cmd_srec_cat = SRECCAT $@
cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
-Output_Block_Size 16 \
-generate 0xe6300400 0xe6300404 -l-e-constant 0x0 4 \
-generate 0xe630048c 0xe6300490 -l-e-constant 0x0 4 \
-generate 0xe63005d4 0xe63005d8 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \
-generate 0xe63006e4 0xe63006e8 -l-e-constant $2 4 \
-generate 0xe6301154 0xe6301158 -l-e-constant $(CONFIG_SPL_TEXT_BASE) 4 \
-generate 0xe6301264 0xe6301268 -l-e-constant $2 4
endif
spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin
$(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}'))
# if srec_cat is present build u-boot-spl.scif by default
has_srec_cat = $(call try-run,srec_cat -VERSion,y,n)
ALL-$(has_srec_cat) += u-boot-spl.scif
CLEAN_FILES += u-boot-spl.scif
......@@ -6,4 +6,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := draak.o
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := draak.o ../rcar-common/common.o
endif
......@@ -70,21 +70,6 @@ int board_init(void)
return 0;
}
int dram_init(void)
{
if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
return 0;
}
int dram_init_banksize(void)
{
fdtdec_setup_memory_banksize();
return 0;
}
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
......
......@@ -6,4 +6,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := eagle.o
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := eagle.o ../rcar-common/common.o
endif
......@@ -67,21 +67,6 @@ int board_init(void)
return 0;
}
int dram_init(void)
{
if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
return 0;
}
int dram_init_banksize(void)
{
fdtdec_setup_memory_banksize();
return 0;
}
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
......
......@@ -6,4 +6,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := ebisu.o
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ebisu.o ../rcar-common/common.o
endif
......@@ -43,41 +43,6 @@ int board_init(void)
return 0;
}
/*
* If the firmware passed a device tree use it for U-Boot DRAM setup.
*/
extern u64 rcar_atf_boot_args[];
int dram_init(void)
{
const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
const void *blob;
/* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
blob = atf_fdt_blob;
else
blob = gd->fdt_blob;
return fdtdec_setup_mem_size_base_fdt(blob);
}
int dram_init_banksize(void)
{
const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
const void *blob;
/* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
blob = atf_fdt_blob;
else
blob = gd->fdt_blob;
fdtdec_setup_memory_banksize_fdt(blob);
return 0;
}
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
......
......@@ -9,3 +9,41 @@
#include <common.h>
#include <asm/arch/rmobile.h>
#ifdef CONFIG_RCAR_GEN3
DECLARE_GLOBAL_DATA_PTR;
/* If the firmware passed a device tree use it for U-Boot DRAM setup. */
extern u64 rcar_atf_boot_args[];
int dram_init(void)
{
const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
const void *blob;
/* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
blob = atf_fdt_blob;
else
blob = gd->fdt_blob;
return fdtdec_setup_mem_size_base_fdt(blob);
}
int dram_init_banksize(void)
{
const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
const void *blob;
/* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
blob = atf_fdt_blob;
else
blob = gd->fdt_blob;
fdtdec_setup_memory_banksize_fdt(blob);
return 0;
}
#endif
// SPDX-License-Identifier: GPL-2.0
/*
* R-Car Gen3 recovery SPL
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <asm/io.h>
#include <spl.h>
#define RCAR_CNTC_BASE 0xE6080000
#define CNTCR_EN BIT(0)
void board_init_f(ulong dummy)
{
writel(CNTCR_EN, RCAR_CNTC_BASE);
timer_init();
}
void spl_board_init(void)
{
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
}
u32 spl_boot_device(void)
{
return BOOT_DEVICE_UART;
}
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
debug("image entry point: 0x%lx\n", spl_image->entry_point);
if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) {
typedef void (*image_entry_arg_t)(int, int, int, int)
__attribute__ ((noreturn));
image_entry_arg_t image_entry =
(image_entry_arg_t)(uintptr_t) spl_image->entry_point;
image_entry(IH_MAGIC, CONFIG_SPL_TEXT_BASE, 0, 0);
} else {
typedef void __noreturn (*image_entry_noargs_t)(void);
image_entry_noargs_t image_entry =
(image_entry_noargs_t)spl_image->entry_point;
image_entry();
}
}
void s_init(void)
{
}
void reset_cpu(ulong addr)
{
}
......@@ -6,4 +6,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := salvator-x.o
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := salvator-x.o ../rcar-common/common.o
endif
......@@ -69,41 +69,6 @@ int board_init(void)
return 0;
}
/*
* If the firmware passed a device tree use it for U-Boot DRAM setup.
*/
extern u64 rcar_atf_boot_args[];
int dram_init(void)
{
const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
const void *blob;
/* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
blob = atf_fdt_blob;
else
blob = gd->fdt_blob;
return fdtdec_setup_mem_size_base_fdt(blob);
}
int dram_init_banksize(void)
{
const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
const void *blob;
/* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
blob = atf_fdt_blob;
else
blob = gd->fdt_blob;
fdtdec_setup_memory_banksize_fdt(blob);
return 0;
}
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
......
......@@ -6,4 +6,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := ulcb.o cpld.o
ifdef CONFIG_SPL_BUILD
obj-y := ../rcar-common/gen3-spl.o
else
obj-y := ulcb.o cpld.o ../rcar-common/common.o
endif
......@@ -68,41 +68,6 @@ int board_init(void)
return 0;
}
/*
* If the firmware passed a device tree use it for U-Boot DRAM setup.
*/
extern u64 rcar_atf_boot_args[];
int dram_init(void)
{
const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
const void *blob;
/* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
blob = atf_fdt_blob;
else
blob = gd->fdt_blob;
return fdtdec_setup_mem_size_base_fdt(blob);
}
int dram_init_banksize(void)
{
const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
const void *blob;
/* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
blob = atf_fdt_blob;
else
blob = gd->fdt_blob;
fdtdec_setup_memory_banksize_fdt(blob);
return 0;
}
#ifdef CONFIG_MULTI_DTB_FIT
int board_fit_config_name_match(const char *name)
{
......
......@@ -11,11 +11,13 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
......@@ -48,6 +50,9 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_RCAR_GEN3=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
......
......@@ -12,6 +12,7 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
......
......@@ -12,11 +12,13 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77965-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
......@@ -49,6 +51,9 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_RCAR_GEN3=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
......
......@@ -12,6 +12,7 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77965-m3nulcb.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
......
......@@ -12,11 +12,13 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
......@@ -49,6 +51,9 @@ CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_RCAR_GEN3=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
......
......@@ -12,6 +12,7 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_TEXT_BASE=0xe6338000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
......
......@@ -12,6 +12,7 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
......
......@@ -12,6 +12,7 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
......
......@@ -12,6 +12,7 @@ CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.2
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
......
......@@ -23,24 +23,126 @@
/* SCC registers */
#define RENESAS_SDHI_SCC_DTCNTL 0x800
#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
#define RENESAS_SDHI_SCC_TAPSET 0x804
#define RENESAS_SDHI_SCC_DT2FF 0x808
#define RENESAS_SDHI_SCC_CKSEL 0x80c
#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
#define RENESAS_SDHI_SCC_RVSCNTL 0x810
#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
#define RENESAS_SDHI_SCC_RVSCNTL 0x810
#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
#define RENESAS_SDHI_SCC_RVSREQ 0x814
#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
#define RENESAS_SDHI_SCC_SMPCMP 0x818
#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
#define RENESAS_SDHI_SCC_TMPPORT3 0x828
#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0 3
#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1 2
#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2 1
#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3 0
#define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK 0x3
#define RENESAS_SDHI_SCC_TMPPORT4 0x82c
#define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
#define RENESAS_SDHI_SCC_TMPPORT5 0x830
#define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
#define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
#define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
#define RENESAS_SDHI_SCC_TMPPORT6 0x834
#define RENESAS_SDHI_SCC_TMPPORT7 0x838
#define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
#define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
#define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
#define RENESAS_SDHI_MAX_TAP 3
static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
{
/* read mode */
tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
(RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
RENESAS_SDHI_SCC_TMPPORT5);
/* access start and stop */
tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
RENESAS_SDHI_SCC_TMPPORT4);
tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
}
static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
{
/* write mode */
tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
(RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
RENESAS_SDHI_SCC_TMPPORT5);
tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
/* access start and stop */
tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
RENESAS_SDHI_SCC_TMPPORT4);
tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
}
static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
{
u32 calib_code;
if (!priv->adjust_hs400_enable)
return;
if (!priv->needs_adjust_hs400)
return;
/*